[RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Sam Ravnborg]

The following is the current set of patches so far to support
PBL for the skov-arm9cpu.

The pwm is not really part of this - but it is part of the story.
The patch-set was triggered when someone reported a bug in the 
atmel pwm code. The code did not build - so I ported it over.
Now I wanted to boot the target, but at91bootstrap no longer
supports the at91sam9263. So I decided to try to make it work
in barebox. I have tried this before and failed - but it should
be possible...

What I have made is modelled on top of all the great work
for other more modern atmel bouards.

This is an RFC - because the code does not yet work :-(
It fails to mount the SD Card - for reasons I am yet to discover.

Most of the code is attempted to be generic so we can use it
for other targets.

Feedback on the general structure would be nice.
But otherwise just consider this a short status that something
is in the works and I may return to this later - no promises
on the timeframe though.

	Sam

Sam Ravnborg (8):
      pwm: atmel: Fix build and update
      ARM: at91: Provide at91_mux_pio_pin for use in lowlevel
      ARM: at91: Add at91sam9 xload_mmc for PBL use
      ARM: at91: Add extra register definitions
      ARM: at91: Add lowlevel helpers for at91sam9263
      ARM: at91: Make sdramc.h useable in multi image builds
      ARM: at91: Add initialize function to sdramc
      ARM: at91: Add xload support to skov-arm9cpu

 arch/arm/boards/skov-arm9cpu/lowlevel.c            | 148 +++-----
 arch/arm/mach-at91/Kconfig                         |   4 +-
 arch/arm/mach-at91/Makefile                        |   4 +-
 arch/arm/mach-at91/at91sam9_sdramc_ll.c            |  67 ++++
 arch/arm/mach-at91/at91sam9_xload_mmc.c            | 115 +++++++
 arch/arm/mach-at91/include/mach/at91_pmc.h         |   2 +
 arch/arm/mach-at91/include/mach/at91sam9263.h      |  14 +
 .../mach-at91/include/mach/at91sam9263_matrix.h    |  23 +-
 arch/arm/mach-at91/include/mach/at91sam926x.h      |   2 +
 arch/arm/mach-at91/include/mach/at91sam9_sdramc.h  | 165 ++++++---
 arch/arm/mach-at91/include/mach/gpio.h             |  25 ++
 arch/arm/mach-at91/include/mach/sam92_ll.h         |  54 +++
 arch/arm/mach-at91/include/mach/xload.h            |   4 +
 arch/arm/mach-at91/sam9263_ll.c                    | 216 ++++++++++++
 drivers/pwm/pwm-atmel.c                            | 383 +++++++++++++++------
 images/Makefile.at91                               |   5 +
 16 files changed, 981 insertions(+), 250 deletions(-)



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[PATCH v1 1/8] pwm: atmel: Fix build and update

[Sam Ravnborg]

The pwm-atmel driver was not updated to use the atomic api and did not
build.

Update the driver from linux kernel 5.16-rc7 and adapt to barebox
to get the latest fixes including the conversion to atomic api.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 drivers/pwm/pwm-atmel.c | 383 ++++++++++++++++++++++++++++++----------
 1 file changed, 285 insertions(+), 98 deletions(-)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 648f75fb7..9ec81e18b 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -55,15 +55,7 @@
 #define PWMV2_CPRD		0x0C
 #define PWMV2_CPRDUPD		0x10
 
-/*
- * Max value for duty and period
- *
- * Although the duty and period register is 32 bit,
- * however only the LSB 16 bits are significant.
- */
-#define PWM_MAX_DTY		0xFFFF
-#define PWM_MAX_PRD		0xFFFF
-#define PRD_MAX_PRES		10
+#define PWM_MAX_PRES		10
 
 struct atmel_pwm_registers {
 	u8 period;
@@ -72,30 +64,53 @@ struct atmel_pwm_registers {
 	u8 duty_upd;
 };
 
-struct atmel_pwm;
+struct atmel_pwm_config {
+	u32 period_bits;
+};
 
-struct atmel_pwm_chip {
-	struct pwm_chip chip;
-	struct atmel_pwm *atmel;
+struct atmel_pwm_data {
+	struct atmel_pwm_registers regs;
+	struct atmel_pwm_config cfg;
 };
 
-struct atmel_pwm {
-	struct atmel_pwm_chip atmel_pwm_chip[PWM_CHANNELS];
-	const struct atmel_pwm_registers *regs;
+struct atmel_pwm_chip {
+	struct pwm_chip chips[PWM_CHANNELS];
 	struct clk *clk;
 	void __iomem *base;
 	struct device_d *dev;
+	const struct atmel_pwm_data *data;
+
+	/*
+	 * The hardware supports a mechanism to update a channel's duty cycle at
+	 * the end of the currently running period. When such an update is
+	 * pending we delay disabling the PWM until the new configuration is
+	 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
+	 * might not result in an inactive output.
+	 * This bitmask tracks for which channels an update is pending in
+	 * hardware.
+	 */
+	u32 update_pending;
+
+	/* Protects .update_pending */
+	spinlock_t lock;
 };
 
 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
 {
-	return container_of(chip, struct atmel_pwm_chip, chip);
+	struct pwm_chip (*chips)[4] = (void *)&chip[-chip->id];
+	return container_of(chips, struct atmel_pwm_chip, chips);
+}
+
+static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
+				  unsigned long offset)
+{
+	return readl_relaxed(chip->base + offset);
 }
 
 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
 				    unsigned long offset, unsigned long val)
 {
-	writel(val, chip->atmel->base + offset);
+	writel_relaxed(val, chip->base + offset);
 }
 
 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
@@ -103,7 +118,7 @@ static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
 {
 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 
-	return readl(chip->atmel->base + base + offset);
+	return atmel_pwm_readl(chip, base + offset);
 }
 
 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
@@ -112,24 +127,95 @@ static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
 {
 	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 
-	writel(val, chip->atmel->base + base + offset);
+	atmel_pwm_writel(chip, base + offset, val);
+}
+
+static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
+{
+	/*
+	 * Each channel that has its bit in ISR set started a new period since
+	 * ISR was cleared and so there is no more update pending.  Note that
+	 * reading ISR clears it, so this needs to handle all channels to not
+	 * loose information.
+	 */
+	u32 isr = atmel_pwm_readl(chip, PWM_ISR);
+
+	chip->update_pending &= ~isr;
+}
+
+static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+	spin_lock(&chip->lock);
+
+	/*
+	 * Clear pending flags in hardware because otherwise there might still
+	 * be a stale flag in ISR.
+	 */
+	atmel_pwm_update_pending(chip);
+
+	chip->update_pending |= (1 << ch);
+
+	spin_unlock(&chip->lock);
+}
+
+static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+	int ret = 0;
+
+	spin_lock(&chip->lock);
+
+	if (chip->update_pending & (1 << ch)) {
+		atmel_pwm_update_pending(chip);
+
+		if (chip->update_pending & (1 << ch))
+			ret = 1;
+	}
+
+	spin_unlock(&chip->lock);
+
+	return ret;
+}
+
+static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
+{
+	unsigned long timeout = get_time_ns() + 2 * HZ;
+	int ret;
+
+	while ((ret = atmel_pwm_test_pending(chip, ch)) &&
+	       !is_timeout(get_time_ns(), timeout))
+		udelay(100);
+
+	return ret ? -ETIMEDOUT : 0;
 }
 
-static int atmel_pwm_calculate_cprd_and_pres(struct atmel_pwm_chip *atmel_pwm,
-					     int period,
+static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
+					     unsigned long clkrate,
+					     const struct pwm_state *state,
 					     unsigned long *cprd, u32 *pres)
 {
-	unsigned long long cycles = period;
+	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+	unsigned long long cycles = state->period_ns;
+	int shift;
+
 	/* Calculate the period cycles and prescale value */
-	cycles *= clk_get_rate(atmel_pwm->atmel->clk);
+	cycles *= clkrate;
 	do_div(cycles, NSEC_PER_SEC);
 
-	for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
-		(*pres)++;
+	/*
+	 * The register for the period length is cfg.period_bits bits wide.
+	 * So for each bit the number of clock cycles is wider divide the input
+	 * clock frequency by two using pres and shift cprd accordingly.
+	 */
+	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
 
-	if (*pres > PRD_MAX_PRES) {
-		dev_err(atmel_pwm->atmel->dev, "pres exceeds the maximum value\n");
+	if (shift > PWM_MAX_PRES) {
+		dev_err(atmel_pwm->dev, "pres exceeds the maximum value\n");
 		return -EINVAL;
+	} else if (shift > 0) {
+		*pres = shift;
+		cycles >>= *pres;
+	} else {
+		*pres = 0;
 	}
 
 	*cprd = cycles;
@@ -137,137 +223,238 @@ static int atmel_pwm_calculate_cprd_and_pres(struct atmel_pwm_chip *atmel_pwm,
 	return 0;
 }
 
-static void atmel_pwm_calculate_cdty(int duty, int period,
-				     unsigned long cprd, unsigned long *cdty)
+static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
+				     unsigned long clkrate, unsigned long cprd,
+				     u32 pres, unsigned long *cdty)
 {
-	unsigned long long cycles = duty;
+	unsigned long long cycles = state->duty_ns;
 
-	cycles *= cprd;
-	do_div(cycles, period);
+	cycles *= clkrate;
+	do_div(cycles, NSEC_PER_SEC);
+	cycles >>= pres;
 	*cdty = cprd - cycles;
 }
 
-static void atmel_pwm_set_cprd_cdty(struct atmel_pwm_chip *atmel_pwm, int ch,
+static void atmel_pwm_update_cdty(struct pwm_chip *chip, unsigned long cdty)
+{
+	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+	u32 val;
+
+	if (atmel_pwm->data->regs.duty_upd ==
+	    atmel_pwm->data->regs.period_upd) {
+		val = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+		val &= ~PWM_CMR_UPD_CDTY;
+		atmel_pwm_ch_writel(atmel_pwm, chip->id, PWM_CMR, val);
+	}
+
+	atmel_pwm_ch_writel(atmel_pwm, chip->id,
+			    atmel_pwm->data->regs.duty_upd, cdty);
+	atmel_pwm_set_pending(atmel_pwm, chip->id);
+}
+
+static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
 				    unsigned long cprd, unsigned long cdty)
 {
-	const struct atmel_pwm_registers *regs = atmel_pwm->atmel->regs;
+	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 
-	atmel_pwm_ch_writel(atmel_pwm, ch, regs->duty, cdty);
-	atmel_pwm_ch_writel(atmel_pwm, ch, regs->period, cprd);
+	atmel_pwm_ch_writel(atmel_pwm, chip->id,
+			    atmel_pwm->data->regs.duty, cdty);
+	atmel_pwm_ch_writel(atmel_pwm, chip->id,
+			    atmel_pwm->data->regs.period, cprd);
 }
 
-static int atmel_pwm_config(struct pwm_chip *chip, int duty_ns, int period_ns)
+static void atmel_pwm_disable(struct pwm_chip *chip, bool disable_clk)
 {
 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
-	unsigned long cprd, cdty;
-	u32 pres, val;
-	int ret;
-	int ch;
+	unsigned long timeout;
 
-	ch = atmel_pwm->chip.id;
-	ret = atmel_pwm_calculate_cprd_and_pres(atmel_pwm, period_ns, &cprd, &pres);
-	if (ret)
-		return ret;
+	atmel_pwm_wait_nonpending(atmel_pwm, chip->id);
 
-	atmel_pwm_calculate_cdty(duty_ns, period_ns, cprd, &cdty);
+	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << chip->id);
 
-	/* It is necessary to preserve CPOL, inside CMR */
-	val = atmel_pwm_ch_readl(atmel_pwm, ch, PWM_CMR);
-	val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
-	/* Assuming normal polarity */
-	val &= ~PWM_CMR_CPOL;
+	/*
+	 * Wait for the PWM channel disable operation to be effective before
+	 * stopping the clock.
+	 */
+	timeout = get_time_ns() + 2 * HZ;
 
-	atmel_pwm_ch_writel(atmel_pwm, ch, PWM_CMR, val);
-	atmel_pwm_set_cprd_cdty(atmel_pwm, ch, cprd, cdty);
+	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << chip->id)) &&
+	       !is_timeout(get_time_ns(), timeout))
+		udelay(100);
 
-	return 0;
+	if (disable_clk)
+		clk_disable(atmel_pwm->clk);
 }
 
-static int atmel_pwm_enable(struct pwm_chip *chip)
+static int atmel_pwm_apply(struct pwm_chip *chip, const struct pwm_state *state)
 {
 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+	struct pwm_state cstate;
+	unsigned long cprd, cdty;
+	u32 pres, val;
+	int ret;
 
-	atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << atmel_pwm->chip.id);
-	return 0;
-}
+	cstate = chip->state;
 
-static void atmel_pwm_disable(struct pwm_chip *chip)
-{
-	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
+	if (state->p_enable) {
+		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
+
+		if (cstate.p_enable &&
+		    cstate.polarity == state->polarity &&
+		    cstate.period_ns == state->period_ns) {
+			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+
+			cprd = atmel_pwm_ch_readl(atmel_pwm, chip->id,
+						  atmel_pwm->data->regs.period);
+			pres = cmr & PWM_CMR_CPRE_MSK;
+
+			atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
+			atmel_pwm_update_cdty(chip, cdty);
+			return 0;
+		}
+
+		ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
+							&pres);
+		if (ret) {
+			dev_err(atmel_pwm->dev,
+				"failed to calculate cprd and prescaler\n");
+			return ret;
+		}
+
+		atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
 
-	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << atmel_pwm->chip.id);
+		if (cstate.p_enable) {
+			atmel_pwm_disable(chip, false);
+		} else {
+			ret = clk_enable(atmel_pwm->clk);
+			if (ret) {
+				dev_err(atmel_pwm->dev, "failed to enable clock\n");
+				return ret;
+			}
+		}
+
+		/* It is necessary to preserve CPOL, inside CMR */
+		val = atmel_pwm_ch_readl(atmel_pwm, chip->id, PWM_CMR);
+		val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
+		if (state->polarity == PWM_POLARITY_NORMAL)
+			val &= ~PWM_CMR_CPOL;
+		else
+			val |= PWM_CMR_CPOL;
+		atmel_pwm_ch_writel(atmel_pwm, chip->id, PWM_CMR, val);
+		atmel_pwm_set_cprd_cdty(chip, cprd, cdty);
+		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << chip->id);
+	} else if (cstate.p_enable) {
+		atmel_pwm_disable(chip, true);
+	}
+
+	return 0;
 }
 
-static struct pwm_ops atmel_pwm_ops = {
-	.config = atmel_pwm_config,
-	.enable = atmel_pwm_enable,
-	.disable = atmel_pwm_disable,
+static const struct pwm_ops atmel_pwm_ops = {
+	.apply = atmel_pwm_apply,
 };
 
-static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
-	.period		= PWMV1_CPRD,
-	.period_upd	= PWMV1_CUPD,
-	.duty		= PWMV1_CDTY,
-	.duty_upd	= PWMV1_CUPD,
+static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 16 bits to keep period and duty. */
+		.period_bits	= 16,
+	},
+};
+
+static const struct atmel_pwm_data atmel_sama5_pwm_data = {
+	.regs = {
+		.period		= PWMV2_CPRD,
+		.period_upd	= PWMV2_CPRDUPD,
+		.duty		= PWMV2_CDTY,
+		.duty_upd	= PWMV2_CDTYUPD,
+	},
+	.cfg = {
+		/* 16 bits to keep period and duty. */
+		.period_bits	= 16,
+	},
 };
 
-static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
-	.period		= PWMV2_CPRD,
-	.period_upd	= PWMV2_CPRDUPD,
-	.duty		= PWMV2_CDTY,
-	.duty_upd	= PWMV2_CDTYUPD,
+static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 32 bits to keep period and duty. */
+		.period_bits	= 32,
+	},
 };
 
 static const struct of_device_id atmel_pwm_dt_ids[] = {
 	{
 		.compatible = "atmel,at91sam9rl-pwm",
-		.data = &atmel_pwm_regs_v1,
+		.data = &atmel_sam9rl_pwm_data,
 	}, {
 		.compatible = "atmel,sama5d3-pwm",
-		.data = &atmel_pwm_regs_v2,
+		.data = &atmel_sama5_pwm_data,
 	}, {
 		.compatible = "atmel,sama5d2-pwm",
-		.data = &atmel_pwm_regs_v2,
+		.data = &atmel_sama5_pwm_data,
+	}, {
+		.compatible = "microchip,sam9x60-pwm",
+		.data = &mchp_sam9x60_pwm_data,
 	}, {
 		/* sentinel */
 	},
 };
 
+static int id = -1;
+
 static int atmel_pwm_probe(struct device_d *dev)
 {
-	const struct atmel_pwm_registers *regs;
-	struct atmel_pwm *atmel_pwm;
-	struct resource *res;
+	const struct atmel_pwm_data *data;
+	struct atmel_pwm_chip *atmel_pwm;
+	struct resource *iores;
+	const char *alias;
 	int ret;
 	int i;
 
-	ret = dev_get_drvdata(dev, (const void **)&regs);
+	ret = dev_get_drvdata(dev, (const void **)&data);
 	if (ret)
 		return ret;
 
 	atmel_pwm = xzalloc(sizeof(*atmel_pwm));
-	atmel_pwm->regs = regs;
+	atmel_pwm->data = data;
 	atmel_pwm->dev = dev;
 	atmel_pwm->clk = clk_get(dev, "pwm_clk");
 	if (IS_ERR(atmel_pwm->clk))
 		return PTR_ERR(atmel_pwm->clk);
 
-	res = dev_request_mem_resource(dev, 0);
-	if (IS_ERR(res))
-		return PTR_ERR(res);
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
 
-	atmel_pwm->base = IOMEM(res->start);
+	atmel_pwm->base = IOMEM(iores->start);
+	alias = of_alias_get(dev->device_node);
+	if (!alias)
+		id++;
 
 	for (i = 0; i < PWM_CHANNELS; i++) {
-		struct atmel_pwm_chip *chip = &atmel_pwm->atmel_pwm_chip[i];
-		chip->chip.ops = &atmel_pwm_ops;
-		chip->chip.devname = basprintf("pwm%d", i);
-		chip->chip.id = i;
-		chip->atmel = atmel_pwm;
-
-		ret = pwmchip_add(&chip->chip, dev);
-		if (ret < 0) {
-			dev_err(dev, "failed to add pwm chip[%d] %d\n", i, ret);
+		struct pwm_chip *chip = &atmel_pwm->chips[i];
+
+		if (alias)
+			chip->devname = basprintf("%sch%u", alias, i + 1);
+		else
+			chip->devname = basprintf("pwm%uch%u", id, i + 1);
+
+		chip->ops = &atmel_pwm_ops;
+		chip->id = i;
+		ret = pwmchip_add(chip, dev);
+		if (ret) {
+			dev_err(dev, "failed to add pwm chip %d\n", ret);
 			return ret;
 		}
 	}
-- 
2.34.1


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[PATCH v1 2/8] ARM: at91: Provide at91_mux_pio_pin for use in lowlevel

[Sam Ravnborg]

Lowlevel init code may wish the ability to configure pins, e.g. for low
level debug UART. The pinctrl-at91 driver already exports an
at91_mux_pin function, but that one is only usable after driver
probe. Instead, provide an at91_mux_pio_pin function, which can be used
at all times.

This is similar to the already existing at91_mux_pio3_pin function

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/mach-at91/include/mach/gpio.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index ddd6971e3..7f84f41e5 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -151,6 +151,31 @@ static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
 	return (pdsr & mask) != 0;
 }
 
+static inline void at91_mux_pio_pin(void __iomem *pio, unsigned mask,
+				    enum at91_mux mux, int gpio_state)
+{
+	at91_mux_disable_interrupt(pio, mask);
+
+	switch(mux) {
+	case AT91_MUX_GPIO:
+		at91_mux_gpio_enable(pio, mask);
+		break;
+	case AT91_MUX_PERIPH_A:
+		at91_mux_set_A_periph(pio, mask);
+		break;
+	case AT91_MUX_PERIPH_B:
+		at91_mux_set_B_periph(pio, mask);
+		break;
+	default:
+		/* ignore everything else */
+		break;
+	}
+	if (mux != AT91_MUX_GPIO)
+		at91_mux_gpio_disable(pio, mask);
+
+	at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP);
+}
+
 static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask,
 				     enum at91_mux mux, int gpio_state)
 {
-- 
2.34.1


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[PATCH v1 3/8] ARM: at91: Add at91sam9 xload_mmc for PBL use

[Sam Ravnborg]

Add xload support to at91sam9263 similar to what is already
present for the sama5d3.
The xload supports reading barebox.bin from a SDCARD from the
PBL and load the full barebox.bin and starts it.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/mach-at91/Makefile             |   1 +
 arch/arm/mach-at91/at91sam9_xload_mmc.c | 115 ++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/xload.h |   4 +
 3 files changed, 120 insertions(+)
 create mode 100644 arch/arm/mach-at91/at91sam9_xload_mmc.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bfdc89f68..72805d6ef 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -17,6 +17,7 @@ obj-y += at91sam9_reset.o
 obj-y += at91sam9g45_reset.o
 obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o
 pbl-$(CONFIG_AT91_MCI_PBL) +=  xload-mmc.o
+pbl-$(CONFIG_AT91_MCI_PBL) +=  at91sam9_xload_mmc.o
 
 obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
 obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o
diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c
new file mode 100644
index 000000000..b1b46b317
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <pbl.h>
+
+#include <linux/sizes.h>
+#include <asm/cache.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/xload.h>
+#include <mach/gpio.h>
+
+typedef void (*func)(int zero, int arch, void *params);
+
+/*
+ * Load barebox.bin and start executing the first byte in the barebox image.
+ * barebox.bin is loaded to AT91_CHIPSELECT_1.
+ *
+ * To be able to load barebox.bin do a minimal init of the pheriferals
+ * used by MCI.
+ * This functions runs in PBL code and uses the PBL variant of the
+ * atmel_mci driver.
+ */
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+					  bool slot_b)
+{
+	void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA);
+	void *buf = (void *)AT91_CHIPSELECT_1;
+	void __iomem *base;
+	struct pbl_bio bio;
+	int ret;
+
+	at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA);
+
+	if (mmc_id == 0) {
+		base = IOMEM(AT91SAM9263_BASE_MCI0);
+
+		/* CLK */
+		at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0);
+
+		if (!slot_b) {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		} else {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		}
+
+		at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC),  AT91SAM9263_ID_MCI0);
+	} else {
+		base = IOMEM(AT91SAM9263_BASE_MCI1);
+
+		/* CLK */
+		at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0);
+
+		if (!slot_b) {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		} else {
+			/* CMD */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+			/* DAT0 to DAT3 */
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+			at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+		}
+
+		at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC),  AT91SAM9263_ID_MCI1);
+	}
+
+	ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b);
+	if (ret) {
+		pr_err("atmci_start_image: bio init faild: %d\n", ret);
+		goto out_panic;
+	}
+
+	ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M);
+	if (ret < 0) {
+		pr_err("pbl_fat_load: error %d\n", ret);
+		goto out_panic;
+	}
+
+	sync_caches_for_execution();
+
+	((func)buf)(0, 0, NULL);
+
+out_panic:
+	panic("FAT chainloading failed\n");
+}
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
index e9336d59c..1256358dd 100644
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ b/arch/arm/mach-at91/include/mach/xload.h
@@ -14,4 +14,8 @@ int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
 int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
 		      unsigned int clock, unsigned int slot);
 
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+					  bool slot_b);
+
+
 #endif /* __MACH_XLOAD_H */
-- 
2.34.1


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[PATCH v1 4/8] ARM: at91: Add extra register definitions

[Sam Ravnborg]

Copied from at91bootstrap. Required in subsequent patches.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/mach-at91/include/mach/at91_pmc.h    |   2 +
 arch/arm/mach-at91/include/mach/at91sam9263.h |  14 +++
 .../include/mach/at91sam9263_matrix.h         |  23 +++-
 arch/arm/mach-at91/include/mach/at91sam926x.h |   2 +
 .../mach-at91/include/mach/at91sam9_sdramc.h  | 108 +++++++++++++++++-
 5 files changed, 141 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2860ea485..c5ce0f82a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -170,6 +170,8 @@
 #define			AT91_PMC_IPLLA_1		(1 <<  8)
 #define			AT91_PMC_IPLLA_2		(2 <<  8)
 #define			AT91_PMC_IPLLA_3		(3 <<  8)
+#define		AT91SAM9_PMC_ICPPLLA	(1 << 0)
+#define		AT91SAM9_PMC_ICPPLLB	(1 << 16)
 
 
 #define AT91_PMC_PROT		0xe4			/* Write Protect Mode Register [some SAM9] */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 2ea9aadaf..229f8d16b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -108,4 +108,18 @@
 #define AT91SAM9263_DMAC_BASE	0x00800000	/* DMA Controller */
 #define AT91SAM9263_UHP_BASE	0x00a00000	/* USB Host controller */
 
+/*
+ * External memory
+ */
+#define AT91SAM9263_BASE_EBI0_CS0	0x10000000
+#define AT91SAM9263_BASE_EBI0_CS1	0x20000000	/* EBI0 SDRAMC */
+#define AT91SAM9263_BASE_EBI0_CS2	0x30000000
+#define AT91SAM9263_BASE_EBI0_CS3	0x40000000	/* EBI0 NANDFlash */
+#define AT91SAM9263_BASE_EBI0_CS4	0x50000000	/* Compact Flash Slot 0 */
+#define AT91SAM9263_BASE_EBI0_CS5	0x60000000	/* Compact Flash Slot 1 */
+#define AT91SAM9263_BASE_EBI1_CS0	0x70000000
+#define AT91SAM9263_BASE_EBI1_CS1	0x80000000	/* EBI1 SDRAMC */
+#define AT91SAM9263_BASE_EBI1_CS2	0x90000000	/* EBI1 NANDFlash */
+
+
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 2f10ce096..837cceb41 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -25,7 +25,7 @@
 #define			AT91SAM9263_MATRIX_ULBT_SINGLE		(1 << 0)
 #define			AT91SAM9263_MATRIX_ULBT_FOUR		(2 << 0)
 #define			AT91SAM9263_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91SAM9263_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#define			AT91SAM9263_MATRIX_ULBT_SIXTEEN		(4 << 0)
 
 #define AT91SAM9263_MATRIX_SCFG0	(0x40)	/* Slave Configuration Register 0 */
 #define AT91SAM9263_MATRIX_SCFG1	(0x44)	/* Slave Configuration Register 1 */
@@ -35,12 +35,22 @@
 #define AT91SAM9263_MATRIX_SCFG5	(0x54)	/* Slave Configuration Register 5 */
 #define AT91SAM9263_MATRIX_SCFG6	(0x58)	/* Slave Configuration Register 6 */
 #define AT91SAM9263_MATRIX_SCFG7	(0x5C)	/* Slave Configuration Register 7 */
-#define		AT91SAM9263_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
+#define		AT91SAM9263_MATRIX_SLOT_CYCLE	(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
+#define		AT91SAM9263_MATRIX_SLOT_CYCLE_(x)	(x << 0)
 #define		AT91SAM9263_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
 #define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
 #define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
 #define			AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
 #define		AT91SAM9263_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I	(0x0 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D	(0x1 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC		(0x2 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC		(0x3 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_2DGC		(0x4 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_ISI		(0x5 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_DMA		(0x6 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC		(0x7 << 18)
+#define			AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB		(0x8 << 18)
 #define		AT91SAM9263_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
 #define			AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
 #define			AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
@@ -62,14 +72,23 @@
 #define AT91SAM9263_MATRIX_PRAS7	(0xB8)	/* Priority Register A for Slave 7 */
 #define AT91SAM9263_MATRIX_PRBS7	(0xBC)	/* Priority Register B for Slave 7 */
 #define		AT91SAM9263_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
+#define		AT91SAM9263_MATRIX_M0PR_(x)	(x << 0)	/* ARM926EJ-S Instruction priority */
 #define		AT91SAM9263_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
+#define		AT91SAM9263_MATRIX_M1PR_(x)	(x << 4)	/* ARM926EJ-S Data priority */
 #define		AT91SAM9263_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
+#define		AT91SAM9263_MATRIX_M2PR_(x)	(x << 8)	/* PDC priority */
 #define		AT91SAM9263_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
+#define		AT91SAM9263_MATRIX_M3PR_(x)	(x << 12)	/* LCDC priority */
 #define		AT91SAM9263_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
+#define		AT91SAM9263_MATRIX_M4PR_(x)	(x << 16)	/* 2DGC priority */
 #define		AT91SAM9263_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
+#define		AT91SAM9263_MATRIX_M5PR_(x)	(x << 20)	/* ISI priority */
 #define		AT91SAM9263_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
+#define		AT91SAM9263_MATRIX_M6PR_(x)	(x << 24)	/* DMA priority */
 #define		AT91SAM9263_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
+#define		AT91SAM9263_MATRIX_M7PR_(x)	(x << 28)	/* EMAC priority */
 #define		AT91SAM9263_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
+#define		AT91SAM9263_MATRIX_M8PR_(x)	(x << 0)	/* USB Priority */
 
 #define AT91SAM9263_MATRIX_MRCR	(0x100)	/* Master Remap Control Register */
 #define		AT91SAM9263_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
index 8ef83010d..ae7e224a7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
@@ -7,4 +7,6 @@
 #define AT91SAM926X_BASE_RSTC	0xfffffd00
 #define AT91SAM926X_BASE_WDT	0xfffffd40
 
+#define AT91SAM926X_ID_SYS	1	/* System Controller Interrupt */
+
 #endif /* __MACH_AT91SAM926X_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 80effe214..c34668d7b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -47,12 +47,108 @@
 #define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
 #define			AT91_SDRAMC_DBW_32	(0 << 7)
 #define			AT91_SDRAMC_DBW_16	(1 << 7)
-#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
-#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
-#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
-#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
-#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
-#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_TWR	(0xF << 8)	/* Number of Write Recovery Time Cycles */
+#define 	AT91_SDRAMC_TWR_0		(0x0 << 8)
+#define 	AT91_SDRAMC_TWR_1		(0x1 << 8)
+#define 	AT91_SDRAMC_TWR_2		(0x2 << 8)
+#define 	AT91_SDRAMC_TWR_3		(0x3 << 8)
+#define 	AT91_SDRAMC_TWR_4		(0x4 << 8)
+#define 	AT91_SDRAMC_TWR_5		(0x5 << 8)
+#define 	AT91_SDRAMC_TWR_6		(0x6 << 8)
+#define 	AT91_SDRAMC_TWR_7		(0x7 << 8)
+#define 	AT91_SDRAMC_TWR_8		(0x8 << 8)
+#define 	AT91_SDRAMC_TWR_9		(0x9 << 8)
+#define 	AT91_SDRAMC_TWR_10		(0xA << 8)
+#define 	AT91_SDRAMC_TWR_11		(0xB << 8)
+#define 	AT91_SDRAMC_TWR_12		(0xC << 8)
+#define 	AT91_SDRAMC_TWR_13		(0xD << 8)
+#define 	AT91_SDRAMC_TWR_14		(0xE << 8)
+#define 	AT91_SDRAMC_TWR_15		(0xF << 8)
+#define AT91_SDRAMC_TRC	(0xF << 12)	/* Number of Row Cycle Delay Time Cycles */
+#define 	AT91_SDRAMC_TRC_0		(0x0 << 12)
+#define 	AT91_SDRAMC_TRC_1		(0x1 << 12)
+#define 	AT91_SDRAMC_TRC_2		(0x2 << 12)
+#define 	AT91_SDRAMC_TRC_3		(0x3 << 12)
+#define 	AT91_SDRAMC_TRC_4		(0x4 << 12)
+#define 	AT91_SDRAMC_TRC_5		(0x5 << 12)
+#define 	AT91_SDRAMC_TRC_6		(0x6 << 12)
+#define 	AT91_SDRAMC_TRC_7		(0x7 << 12)
+#define 	AT91_SDRAMC_TRC_8		(0x8 << 12)
+#define 	AT91_SDRAMC_TRC_9		(0x9 << 12)
+#define 	AT91_SDRAMC_TRC_10		(0xA << 12)
+#define 	AT91_SDRAMC_TRC_11		(0xB << 12)
+#define 	AT91_SDRAMC_TRC_12		(0xC << 12)
+#define 	AT91_SDRAMC_TRC_13		(0xD << 12)
+#define 	AT91_SDRAMC_TRC_14		(0xE << 12)
+#define 	AT91_SDRAMC_TRC_15		(0xF << 12)
+#define AT91_SDRAMC_TRP	(0xF << 16)	/* Number of Row Precharge Delay Time Cycles */
+#define 	AT91_SDRAMC_TRP_0		(0x0 << 16)
+#define 	AT91_SDRAMC_TRP_1		(0x1 << 16)
+#define 	AT91_SDRAMC_TRP_2		(0x2 << 16)
+#define 	AT91_SDRAMC_TRP_3		(0x3 << 16)
+#define 	AT91_SDRAMC_TRP_4		(0x4 << 16)
+#define 	AT91_SDRAMC_TRP_5		(0x5 << 16)
+#define 	AT91_SDRAMC_TRP_6		(0x6 << 16)
+#define 	AT91_SDRAMC_TRP_7		(0x7 << 16)
+#define 	AT91_SDRAMC_TRP_8		(0x8 << 16)
+#define 	AT91_SDRAMC_TRP_9		(0x9 << 16)
+#define 	AT91_SDRAMC_TRP_10		(0xA << 16)
+#define 	AT91_SDRAMC_TRP_11		(0xB << 16)
+#define 	AT91_SDRAMC_TRP_12		(0xC << 16)
+#define 	AT91_SDRAMC_TRP_13		(0xD << 16)
+#define 	AT91_SDRAMC_TRP_14		(0xE << 16)
+#define 	AT91_SDRAMC_TRP_15		(0xF << 16)
+#define AT91_SDRAMC_TRCD	(0xF << 20)	/* Number of Row to Column Delay Time Cycles */
+#define 	AT91_SDRAMC_TRCD_0		(0x0 << 20)
+#define 	AT91_SDRAMC_TRCD_1		(0x1 << 20)
+#define 	AT91_SDRAMC_TRCD_2		(0x2 << 20)
+#define 	AT91_SDRAMC_TRCD_3		(0x3 << 20)
+#define 	AT91_SDRAMC_TRCD_4		(0x4 << 20)
+#define 	AT91_SDRAMC_TRCD_5		(0x5 << 20)
+#define 	AT91_SDRAMC_TRCD_6		(0x6 << 20)
+#define 	AT91_SDRAMC_TRCD_7		(0x7 << 20)
+#define 	AT91_SDRAMC_TRCD_8		(0x8 << 20)
+#define 	AT91_SDRAMC_TRCD_9		(0x9 << 20)
+#define 	AT91_SDRAMC_TRCD_10		(0xA << 20)
+#define 	AT91_SDRAMC_TRCD_11		(0xB << 20)
+#define 	AT91_SDRAMC_TRCD_12		(0xC << 20)
+#define 	AT91_SDRAMC_TRCD_13		(0xD << 20)
+#define 	AT91_SDRAMC_TRCD_14		(0xE << 20)
+#define 	AT91_SDRAMC_TRCD_15		(0xF << 20)
+#define AT91_SDRAMC_TRAS	(0xF << 24)	/* Number of Active to Precharge Delay Time Cycles */
+#define 	AT91_SDRAMC_TRAS_0		(0x0 << 24)
+#define 	AT91_SDRAMC_TRAS_1		(0x1 << 24)
+#define 	AT91_SDRAMC_TRAS_2		(0x2 << 24)
+#define 	AT91_SDRAMC_TRAS_3		(0x3 << 24)
+#define 	AT91_SDRAMC_TRAS_4		(0x4 << 24)
+#define 	AT91_SDRAMC_TRAS_5		(0x5 << 24)
+#define 	AT91_SDRAMC_TRAS_6		(0x6 << 24)
+#define 	AT91_SDRAMC_TRAS_7		(0x7 << 24)
+#define 	AT91_SDRAMC_TRAS_8		(0x8 << 24)
+#define 	AT91_SDRAMC_TRAS_9		(0x9 << 24)
+#define 	AT91_SDRAMC_TRAS_10		(0xA << 24)
+#define 	AT91_SDRAMC_TRAS_11		(0xB << 24)
+#define 	AT91_SDRAMC_TRAS_12		(0xC << 24)
+#define 	AT91_SDRAMC_TRAS_13		(0xD << 24)
+#define 	AT91_SDRAMC_TRAS_14		(0xE << 24)
+#define 	AT91_SDRAMC_TRAS_15		(0xF << 24)
+#define AT91_SDRAMC_TXS	(0xF << 28)	/* Number of Exit Self Refresh to Active Delay Time Cycles */
+#define 	AT91_SDRAMC_TXSR_0		(0x0 << 28)
+#define 	AT91_SDRAMC_TXSR_1		(0x1 << 28)
+#define 	AT91_SDRAMC_TXSR_2		(0x2 << 28)
+#define 	AT91_SDRAMC_TXSR_3		(0x3 << 28)
+#define 	AT91_SDRAMC_TXSR_4		(0x4 << 28)
+#define 	AT91_SDRAMC_TXSR_5		(0x5 << 28)
+#define 	AT91_SDRAMC_TXSR_6		(0x6 << 28)
+#define 	AT91_SDRAMC_TXSR_7		(0x7 << 28)
+#define 	AT91_SDRAMC_TXSR_8		(0x8 << 28)
+#define 	AT91_SDRAMC_TXSR_9		(0x9 << 28)
+#define 	AT91_SDRAMC_TXSR_10		(0xA << 28)
+#define 	AT91_SDRAMC_TXSR_11		(0xB << 28)
+#define 	AT91_SDRAMC_TXSR_12		(0xC << 28)
+#define 	AT91_SDRAMC_TXSR_13		(0xD << 28)
+#define 	AT91_SDRAMC_TXSR_14		(0xE << 28)
+#define 	AT91_SDRAMC_TXSR_15		(0xF << 28)
 
 #define AT91_SDRAMC_LPR		0x10	/* SDRAM Controller Low Power Register */
 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
-- 
2.34.1


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[PATCH v1 5/8] ARM: at91: Add lowlevel helpers for at91sam9263

[Sam Ravnborg]

Add lowlevel helpers like we already have for sama5d2 etc.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/mach-at91/Makefile                |   1 +
 arch/arm/mach-at91/include/mach/sam92_ll.h |  54 ++++++
 arch/arm/mach-at91/sam9263_ll.c            | 216 +++++++++++++++++++++
 3 files changed, 271 insertions(+)
 create mode 100644 arch/arm/mach-at91/include/mach/sam92_ll.h
 create mode 100644 arch/arm/mach-at91/sam9263_ll.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 72805d6ef..56c2a3170 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -31,6 +31,7 @@ ifeq ($(CONFIG_OFDEVICE),)
 obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
 obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o sama5d3_devices.o
 endif
+lwl-$(CONFIG_SOC_AT91SAM9263)	+= sam9263_ll.o
 lwl-$(CONFIG_SOC_SAMA5D2)	+= sama5d2_ll.o
 obj-$(CONFIG_SOC_SAMA5D2)	+= sama5d2.o
 lwl-$(CONFIG_SOC_SAMA5D3)	+= sama5d3_ll.o
diff --git a/arch/arm/mach-at91/include/mach/sam92_ll.h b/arch/arm/mach-at91/include/mach/sam92_ll.h
new file mode 100644
index 000000000..f5cef197d
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sam92_ll.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_SAM92_LL_H__
+#define __MACH_SAM92_LL_H__
+
+#include <debug_ll.h>
+#include <common.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/debug_ll.h>
+#include <mach/early_udelay.h>
+#include <mach/iomux.h>
+
+struct sam92_pmc_config {
+	unsigned int diva;
+	unsigned int mula;
+};
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config);
+
+static inline void sam92_pmc_enable_periph_clock(int clk)
+{
+	at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), clk);
+}
+
+/* requires relocation */
+static inline void sam92_udelay_init(unsigned int msc)
+{
+	early_udelay_init(IOMEM(AT91SAM926X_BASE_PMC), IOMEM(AT91SAM9263_BASE_PIT),
+			  AT91SAM926X_ID_SYS, msc, 0);
+}
+
+static inline void sam92_dbgu_setup_ll(unsigned int mck)
+{
+	void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOC);
+
+	// Setup clock for pio
+	sam92_pmc_enable_periph_clock(AT91SAM9263_ID_PIOCDE);
+
+	// Setup DBGU uart
+	at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC30), AT91_MUX_PERIPH_A, GPIO_PULL_UP); // DRXD
+	at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC31), AT91_MUX_PERIPH_A, 0); // DTXD
+
+	// Setup dbgu
+	at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), mck, CONFIG_BAUDRATE);
+	pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1));
+	putc_ll('#');
+}
+
+#endif
diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c
new file mode 100644
index 000000000..11c399b66
--- /dev/null
+++ b/arch/arm/mach-at91/sam9263_ll.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+// SPDX-FileCopyrightText: 2017, Microchip Corporation
+
+#include <mach/at91sam9263_matrix.h>
+#include <mach/barebox-arm.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/sam92_ll.h>
+
+static void sam9263_pmc_init(const struct sam92_pmc_config *config)
+{
+	at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), 0);
+
+	/* Initialize PLL charge pump, must be done before PLLAR/PLLBR */
+	at91_pmc_init_pll(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9_PMC_ICPPLLA | AT91SAM9_PMC_ICPPLLB);
+
+	/* Setting PLL A and divider A */
+	at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC),
+			  AT91_PMC_MUL_(config->mula) |
+			  AT91_PMC_OUT_2 |		// 190 to 240 MHz		
+			  config->diva,			// Divider
+			  0);
+
+	/* Selection of Master Clock and Processor Clock */
+	 
+	/* PCK = PLLA = 2 * MCK */
+	at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+			 AT91_PMC_CSS_SLOW
+			 | AT91_PMC_PRES_1
+			 | AT91SAM9_PMC_MDIV_2
+			 | AT91_PMC_PDIV_1,
+			 0);
+
+	/* Switch MCK on PLLA output */
+	at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+			 AT91_PMC_CSS_PLLA
+			 | AT91_PMC_PRES_1
+			 | AT91SAM9_PMC_MDIV_2
+			 | AT91_PMC_PDIV_1,
+			 0);
+}
+
+static inline void matrix_wr(unsigned int offset, const unsigned int value)
+{
+	writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset));
+}
+
+static void sam9263_matrix_init(void)
+{
+	/* Bus Matrix Master Configuration Register */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN);	/* OHCI */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* ISI */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* 2D */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* DMAC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR);	/* MACB */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN);	/* LCDC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE);	/* PDC */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* DBUS */
+	matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT);	/* IBUS */
+
+	/* Bus Matrix Slave Configuration Registers */
+
+	/* ROM */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG0,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* RAM80K */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG1,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* RAM16K */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG2,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(16));
+
+	/* PERIPHERALS */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG3,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+	/* EBI0 */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG4,
+		  AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+	/* EBI1 */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG5,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(64));
+
+	/* APB */
+	matrix_wr(AT91SAM9263_MATRIX_SCFG6,
+		  AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+		  | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D
+		  | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+		  | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+	/* ROM */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS0,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(3)
+		  | AT91SAM9263_MATRIX_M6PR_(2)
+		  | AT91SAM9263_MATRIX_M7PR_(3));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0));
+
+	/* RAM80K */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS1,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(2)
+		  | AT91SAM9263_MATRIX_M2PR_(1)
+		  | AT91SAM9263_MATRIX_M3PR_(3)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(0));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2));
+
+       /* RAM16K */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS2,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(3)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0));
+
+	/* PERIPHERALS */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS3,
+		  AT91SAM9263_MATRIX_M0PR_(0)
+		  | AT91SAM9263_MATRIX_M1PR_(1)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(2)
+		  | AT91SAM9263_MATRIX_M4PR_(1)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3));
+
+	/* EBI0 */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS4,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(3)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(2)
+		  | AT91SAM9263_MATRIX_M4PR_(3)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(0)
+		  | AT91SAM9263_MATRIX_M7PR_(1));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2));
+
+	/* EBI1 */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS5,
+		  AT91SAM9263_MATRIX_M0PR_(0)
+		  | AT91SAM9263_MATRIX_M1PR_(1)
+		  | AT91SAM9263_MATRIX_M2PR_(0)
+		  | AT91SAM9263_MATRIX_M3PR_(0)
+		  | AT91SAM9263_MATRIX_M4PR_(3)
+		  | AT91SAM9263_MATRIX_M5PR_(2)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(2));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1));
+
+	/* APB */
+	matrix_wr(AT91SAM9263_MATRIX_PRAS6,
+		  AT91SAM9263_MATRIX_M0PR_(1)
+		  | AT91SAM9263_MATRIX_M1PR_(0)
+		  | AT91SAM9263_MATRIX_M2PR_(2)
+		  | AT91SAM9263_MATRIX_M3PR_(1)
+		  | AT91SAM9263_MATRIX_M4PR_(0)
+		  | AT91SAM9263_MATRIX_M5PR_(0)
+		  | AT91SAM9263_MATRIX_M6PR_(3)
+		  | AT91SAM9263_MATRIX_M7PR_(3));
+
+	matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2));
+}
+
+static void sam9263_rstc_init(void)
+{
+	writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR));
+}
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config)
+{
+	arm_cpu_lowlevel_init();
+	at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT));
+	sam9263_pmc_init(config);
+	sam9263_matrix_init();
+	sam9263_rstc_init();
+}
-- 
2.34.1


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[PATCH v1 6/8] ARM: at91: Make sdramc.h useable in multi image builds

[Sam Ravnborg]

There is no need to ifdef out all the static inlines as the headers
no longer conflicts. Drop the ifdefs so we can now use the header
in multi image builds.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 .../mach-at91/include/mach/at91sam9_sdramc.h  | 45 ++-----------------
 1 file changed, 4 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index c34668d7b..fe76f60b0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -177,6 +177,10 @@
 
 #ifndef __ASSEMBLY__
 #include <io.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+
 static inline u32 at91_get_sdram_size(void *base)
 {
 	u32 val;
@@ -203,14 +207,11 @@ static inline u32 at91_get_sdram_size(void *base)
 	return size;
 }
 
-
 static inline bool at91_is_low_power_sdram(void *base)
 {
 	return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
 }
 
-#ifdef CONFIG_SOC_AT91SAM9260
-#include <mach/at91sam9260.h>
 static inline u32 at91sam9260_get_sdram_size(void)
 {
 	return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
@@ -220,20 +221,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
 {
 	return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
 }
-#else
-static inline u32 at91sam9260_get_sdram_size(void)
-{
-	return 0;
-}
-
-static inline bool at91sam9260_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
 
-#ifdef CONFIG_SOC_AT91SAM9261
-#include <mach/at91sam9261.h>
 static inline u32 at91sam9261_get_sdram_size(void)
 {
 	return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
@@ -243,20 +231,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
 {
 	return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
 }
-#else
-static inline u32 at91sam9261_get_sdram_size(void)
-{
-	return 0;
-}
-
-static inline bool at91sam9261_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
 
-#ifdef CONFIG_SOC_AT91SAM9263
-#include <mach/at91sam9263.h>
 static inline u32 at91sam9263_get_sdram_size(int bank)
 {
 	switch (bank) {
@@ -280,18 +255,6 @@ static inline bool at91sam9263_is_low_power_sdram(int bank)
 		return false;
 	}
 }
-#else
-static inline u32 at91sam9263_get_sdram_size(int bank)
-{
-	return 0;
-}
-
-static inline bool at91sam9263_is_low_power_sdram(void)
-{
-	return false;
-}
-#endif
 
 #endif
-
 #endif
-- 
2.34.1


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[PATCH v1 7/8] ARM: at91: Add initialize function to sdramc

[Sam Ravnborg]

Port the sdramc initialize function from at91bootstrap.
It is needed from lowlevel code and is a replacement for the
sdramc init code in at91sam926x_board_init.h

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/mach-at91/Makefile                   |  2 +-
 arch/arm/mach-at91/at91sam9_sdramc_ll.c       | 67 +++++++++++++++++++
 .../mach-at91/include/mach/at91sam9_sdramc.h  | 12 ++++
 3 files changed, 80 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-at91/at91sam9_sdramc_ll.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 56c2a3170..390d49d03 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 obj-y += setup.o aic.o
-lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o
+lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o
 lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
 
 ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
new file mode 100644
index 000000000..b43654364
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+#include <mach/at91sam9_sdramc.h>
+
+static inline void sdramc_wr(const struct at91sam9_sdramc_config *config,
+			     unsigned int offset,
+			     const unsigned int value)
+{
+	writel(value, config->sdramc + offset);
+}
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+			       unsigned int sdram_address)
+{
+	unsigned int i;
+
+	/* Step#1 SDRAM feature must be in the configuration register */
+	sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
+
+	/* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
+
+	/* Step#3 The SDRAM memory type must be set in the Memory Device Register */
+	sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
+
+	/* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
+	for (i = 0; i < 1000; i++) ;
+
+	/* Step#5 A NOP command is issued to the SDRAM devices */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
+	writel(0x00000000, sdram_address);
+
+	/* Step#6 An All Banks Precharge command is issued to the SDRAM devices  */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+	writel(0x00000000, sdram_address);
+
+	for (i = 0; i < 10000; i++) ;
+
+	/* Step#7 Eight auto-refresh cycles are provided */
+	for (i = 0; i < 8; i++) {
+		sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+		writel(0x00000001 + i, sdram_address + 4 + 4 * i);
+	}
+
+	/*  Pause cycles */
+	for (i = 0; i < 1000; i++) ;
+
+	/* Step#8 A Mode Register set (MRS) cyscle is issued to program the SDRAM parameters(TCSR, PASR, DS) */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+	writel(0xcafedede, sdram_address + 0x24);
+
+	/*  Pause cycles */
+	for (i = 0; i < 1000; i++) ;
+
+	/* Step#9 For mobile SDRAM initialization, an Extended Mode Register set cycle is issued to ... */
+
+	/* Step#10 The application must go into Normal Mode, setting Mode to 0 in the Mode Register
+	   and perform a write access at any location in the SDRAM. */
+	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);	// Set Normal mode
+	writel(0x00000000, sdram_address);	// Perform Normal mode
+
+	/* Step#11 Write the refresh rate into the count field in the SDRAMC Refresh Timer Rgister. */
+	sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
+
+	return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index fe76f60b0..0e05387aa 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -181,6 +181,18 @@
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9263.h>
 
+struct at91sam9_sdramc_config {
+	void __iomem *sdramc;
+	unsigned int mr;
+	unsigned int tr;
+	unsigned int cr;
+	unsigned int lpr;
+	unsigned int mdr;
+};
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+			       unsigned int sdram_address);
+
 static inline u32 at91_get_sdram_size(void *base)
 {
 	u32 val;
-- 
2.34.1


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[PATCH v1 8/8] ARM: at91: Add xload support to skov-arm9cpu

[Sam Ravnborg]

This updates skov-arm9cpu with xload support, and we can now
use barebox as a replacment for at91bootstrap.

Only boot via SD card is supported.

NOTE: Actual status
[x] dbgu support in pbl works (can print)
[x] Other init stuff ifdeffed out - from at91bootstrap
[ ] Check what the original code used for div/mul - there is some confusion
[ ] load barebox.bin and boots it. Right now mount fails
[ ] barebox.bin can start a linux kernel
[ ] support default SD card boots and nfsboot
[x] update Kconfig to work with xload
[x] xload image support

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
---
 arch/arm/boards/skov-arm9cpu/lowlevel.c | 148 ++++++++----------------
 arch/arm/mach-at91/Kconfig              |   4 +-
 images/Makefile.at91                    |   5 +
 3 files changed, 55 insertions(+), 102 deletions(-)

diff --git a/arch/arm/boards/skov-arm9cpu/lowlevel.c b/arch/arm/boards/skov-arm9cpu/lowlevel.c
index d335953a7..b408246b6 100644
--- a/arch/arm/boards/skov-arm9cpu/lowlevel.c
+++ b/arch/arm/boards/skov-arm9cpu/lowlevel.c
@@ -1,115 +1,69 @@
 // SPDX-License-Identifier: GPL-2.0
-// PDX-FileCopyrightText: 2018 Sam Ravnborg <sam@ravnborg.org>
+// PDX-FileCopyrightText: 2022 Sam Ravnborg <sam@ravnborg.org>
 
-#include <linux/sizes.h>
+#include <debug_ll.h>
 
 #include <asm/barebox-arm.h>
 
-#include <mach/at91sam926x_board_init.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/sam92_ll.h>
+#include <mach/xload.h>
 
-#define MASTER_PLL_MUL		171
-#define MASTER_PLL_DIV		14
+/* MCK = 20 MHz */
+#define MAIN_CLOCK	200000000
+#define MASTER_CLOCK	(MAIN_CLOCK / 2)	/* PMC_MCKR divides by 2 */
 
-static void __bare_init skovarm9cpu_board_config(struct at91sam926x_board_cfg *cfg)
+static void sam9263_sdramc_init(unsigned int mck)
 {
-	/* Disable Watchdog */
-	cfg->wdt_mr =
-		AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
-		AT91_WDT_WDV |
-		AT91_WDT_WDDIS |
-		AT91_WDT_WDD;
+	const struct at91sam9_sdramc_config config =
+	{
+		.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0),
+		.mr = 0,
+		.tr = (mck * 7) / 1000000, // TODO 140 versus 0x13c (316)?
+		.cr = AT91_SDRAMC_NC_10 | AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_2
+		      | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32
+		      | AT91_SDRAMC_TWR_2 | AT91_SDRAMC_TRC_7
+		      | AT91_SDRAMC_TRP_2 | AT91_SDRAMC_TRCD_2
+		      | AT91_SDRAMC_TRAS_5 | AT91_SDRAMC_TXSR_8,
+		.lpr = 0,
+		.mdr = AT91_SDRAMC_MD_SDRAM,
+	};
+
+	/* Define PDC[31:16] as DATA[31:16] */
+	at91_mux_gpio_disable(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000);
+	/* No pull-up for D[31:16] */
+	at91_mux_set_pullup(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000, true);
+	/* PD16 to PD31 are pheripheral A */
+	at91_mux_set_A_periph(IOMEM(AT91SAM9263_BASE_PIOD), 0xffff0000);
 
-	/* define PDC[31:16] as DATA[31:16] */
-	cfg->ebi_pio_pdr = 0xFFFF0000;
-	/* no pull-up for D[31:16] */
-	cfg->ebi_pio_ppudr = 0xFFFF0000;
 	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-	cfg->ebi_csa =
-		AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
-		AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
+	writel(AT91SAM9263_MATRIX_EBI0_DBPUC
+	       | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V
+	       | AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC,
+	       IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA));
 
-	cfg->smc_cs = 0;
-	cfg->smc_mode =
-		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		AT91_SMC_DBW_16 |
-		AT91_SMC_TDFMODE |
-		AT91_SMC_TDF_(6);
-	cfg->smc_cycle =
-		AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
-	cfg->smc_pulse =
-		AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
-		AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
-	cfg->smc_setup =
-		AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
-		AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
-
-	cfg->pmc_mor =
-		AT91_PMC_MOSCEN |
-		(255 << 8);		/* Main Oscillator Start-up Time */
-	cfg->pmc_pllar =
-		AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
-		AT91_PMC_OUT |
-		AT91_PMC_PLLCOUNT |	/* PLL Counter */
-		(2 << 28) |		/* PLL Clock Frequency Range */
-		((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
-	/* PCK/2 = MCK Master Clock from PLLA */
-	cfg->pmc_mckr1 =
-		AT91_PMC_CSS_SLOW |
-		AT91_PMC_PRES_1 |
-		AT91SAM9_PMC_MDIV_2 |
-		AT91_PMC_PDIV_1;
-	/* PCK/2 = MCK Master Clock from PLLA */
-	cfg->pmc_mckr2 =
-		AT91_PMC_CSS_PLLA |
-		AT91_PMC_PRES_1 |
-		AT91SAM9_PMC_MDIV_2 |
-		AT91_PMC_PDIV_1;
-
-	/* SDRAM */
-	/* SDRAMC_TR - Refresh Timer register */
-	cfg->sdrc_tr1 = 0x13C;
-	/* SDRAMC_CR - Configuration register*/
-	cfg->sdrc_cr =
-		AT91_SDRAMC_NC_10 |	/* Assume 128MiB */
-		AT91_SDRAMC_NR_13 |
-		AT91_SDRAMC_NB_4 |
-		AT91_SDRAMC_CAS_3 |
-		AT91_SDRAMC_DBW_32 |
-		(1 <<  8) |		/* Write Recovery Delay */
-		(7 << 12) |		/* Row Cycle Delay */
-		(2 << 16) |		/* Row Precharge Delay */
-		(2 << 20) |		/* Row to Column Delay */
-		(5 << 24) |		/* Active to Precharge Delay */
-		(1 << 28);		/* Exit Self Refresh to Active Delay */
-
-	/* Memory Device Register -> SDRAM */
-	cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
-	/* SDRAM_TR */
-	cfg->sdrc_tr2 = 1200;
-
-	/* user reset enable */
-	cfg->rstc_rmr =
-		AT91_RSTC_KEY |
-		AT91_RSTC_PROCRST |
-		AT91_RSTC_RSTTYP_WAKEUP |
-		AT91_RSTC_RSTTYP_WATCHDOG;
+	at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1);
 }
 
-static void __bare_init skov_arm9cpu_init(void *fdt)
+ENTRY_FUNCTION(start_skov_arm9cpu_xload_mmc, r0, r1, r2)
 {
-	struct at91sam926x_board_cfg cfg;
+	const struct sam92_pmc_config sam92_pmc_config = {
+		/* X-tal is 16.000 MHz so 16 / 4 * (31 + 1) = 200 */
+		.diva = 14,
+		.mula = 171,
+	};
+	sam9263_lowlevel_init(&sam92_pmc_config);
+	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
 
-	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
-	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
-	cfg.ebi_pio_is_peripha = true;
-	cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+	relocate_to_current_adr();
+	setup_c();
 
-	skovarm9cpu_board_config(&cfg);
-	at91sam9263_board_init(&cfg);
+	sam92_dbgu_setup_ll(MASTER_CLOCK);
 
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
-			  fdt);
+	sam92_udelay_init(MASTER_CLOCK);
+	sam9263_sdramc_init(MASTER_CLOCK);
+	sam9263_atmci_start_image(1, MASTER_CLOCK, 0);
 }
 
 extern char __dtb_at91_skov_arm9cpu_start[];
@@ -118,10 +72,6 @@ ENTRY_FUNCTION(start_skov_arm9cpu, r0, r1, r2)
 {
 	void *fdt;
 
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
 	fdt = __dtb_at91_skov_arm9cpu_start + get_runtime_offset();
-
-	skov_arm9cpu_init(fdt);
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9263_get_sdram_size(0), fdt);
 }
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bc55b1c4e..f5f674d82 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -577,9 +577,7 @@ config MACH_SKOV_ARM9CPU
 	select SOC_AT91SAM9263
 	select OFDEVICE
 	select COMMON_CLK_OF_PROVIDER
-	select HAVE_AT91_USB_CLK
-	select HAVE_AT91_BOOTSTRAP
-	select AT91SAM926X_BOARD_INIT
+	select MCI_ATMEL_PBL
 	help
 	  Say y here if you are using SKOV's ARM9 CPU board
 
diff --git a/images/Makefile.at91 b/images/Makefile.at91
index 71cc959f5..9a33d3bb9 100644
--- a/images/Makefile.at91
+++ b/images/Makefile.at91
@@ -47,6 +47,11 @@ FILE_barebox-groboards-sama5d27-giantboard-xload-mmc.img = start_sama5d27_giantb
 MAX_PBL_IMAGE_SIZE_start_sama5d27_giantboard_xload_mmc = 0xffff
 image-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += barebox-groboards-sama5d27-giantboard-xload-mmc.img
 
+pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu_xload_mmc
+FILE_barebox-skov-arm9cpu-xload-mmc.img = start_skov_arm9cpu_xload_mmc.pblb
+MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
+image-$(CONFIG_MACH_SKOV_ARM9CPU) += barebox-skov-arm9cpu-xload-mmc.img
+
 pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu
 FILE_barebox-skov-arm9cpu.img = start_skov_arm9cpu.pblb
 MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
-- 
2.34.1


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Re: [PATCH v1 7/8] ARM: at91: Add initialize function to sdramc

[Ahmad Fatoum]

Hello Sam,

On 15.05.22 21:38, Sam Ravnborg wrote:
> +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> +			       unsigned int sdram_address)
> +{
> +	unsigned int i;
> +
> +	/* Step#1 SDRAM feature must be in the configuration register */
> +	sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
> +
> +	/* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
> +
> +	/* Step#3 The SDRAM memory type must be set in the Memory Device Register */
> +	sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
> +
> +	/* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
> +	for (i = 0; i < 1000; i++) ;

This and similar instances below must be replaced by proper delays.
You can use early_udelay for this as you already initialize the PIT.

Did you test SDRAM worked with this setup? I assumed this to be at least
one of the reasons current at91bootstrap fails to work with current compilers
for the 9263. (Newer SoCs use a different DRAM controller and thus a different
driver that doesn't use compile-time removable delay loops).

> +
> +	/* Step#5 A NOP command is issued to the SDRAM devices */
> +	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
> +	writel(0x00000000, sdram_address);
> +
> +	/* Step#6 An All Banks Precharge command is issued to the SDRAM devices  */
> +	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
> +	writel(0x00000000, sdram_address);
> +
> +	for (i = 0; i < 10000; i++) ;
> +
> +	/* Step#7 Eight auto-refresh cycles are provided */
> +	for (i = 0; i < 8; i++) {
> +		sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
> +		writel(0x00000001 + i, sdram_address + 4 + 4 * i);
> +	}
> +
> +	/*  Pause cycles */
> +	for (i = 0; i < 1000; i++) ;
> +
> +	/* Step#8 A Mode Register set (MRS) cyscle is issued to program the SDRAM parameters(TCSR, PASR, DS) */
> +	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
> +	writel(0xcafedede, sdram_address + 0x24);
> +
> +	/*  Pause cycles */
> +	for (i = 0; i < 1000; i++) ;
> +
> +	/* Step#9 For mobile SDRAM initialization, an Extended Mode Register set cycle is issued to ... */
> +
> +	/* Step#10 The application must go into Normal Mode, setting Mode to 0 in the Mode Register
> +	   and perform a write access at any location in the SDRAM. */
> +	sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);	// Set Normal mode
> +	writel(0x00000000, sdram_address);	// Perform Normal mode
> +
> +	/* Step#11 Write the refresh rate into the count field in the SDRAMC Refresh Timer Rgister. */
> +	sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
> +
> +	return 0;
> +}
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> index fe76f60b0..0e05387aa 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> @@ -181,6 +181,18 @@
>  #include <mach/at91sam9261.h>
>  #include <mach/at91sam9263.h>
>  
> +struct at91sam9_sdramc_config {
> +	void __iomem *sdramc;
> +	unsigned int mr;
> +	unsigned int tr;
> +	unsigned int cr;
> +	unsigned int lpr;
> +	unsigned int mdr;
> +};
> +
> +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> +			       unsigned int sdram_address);
> +
>  static inline u32 at91_get_sdram_size(void *base)
>  {
>  	u32 val;


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Re: [PATCH v1 8/8] ARM: at91: Add xload support to skov-arm9cpu

[Ahmad Fatoum]

Hello Sam,

On 15.05.22 21:38, Sam Ravnborg wrote:
> This updates skov-arm9cpu with xload support, and we can now
> use barebox as a replacment for at91bootstrap.
> 
> Only boot via SD card is supported.
> 
> NOTE: Actual status
> [x] dbgu support in pbl works (can print)
> [x] Other init stuff ifdeffed out - from at91bootstrap
> [ ] Check what the original code used for div/mul - there is some confusion
> [ ] load barebox.bin and boots it. Right now mount fails

Is your SD-Card perhaps 2G or smaller? The AT91 PBL MCI functions
assume high capacity (> 2G). It's a quite ugly thing, but
finding out whether a card is High-Capacity or not happens
during init phase and as we don't redo init in PBL...

High Capacity cards reference start block offset in sectors, while
older cards use bytes. On i.MX, barebox just reads at offset 0
and all is good, but on AT91, we need to do random access, so
we need to decide whether to use sectors or bytes. Currently,
the driver hardcodes the sector assumption. I found this to be
the lesser evil to the alternative: having a full MMC stack in PBL. 

If that's indeed your issue, there's a heuristic possible:
Try to mount for High-Capacity, if that fails, assume non-high
capacity and try again. It's not 100%, but it's better than status quo.

> -static void __bare_init skov_arm9cpu_init(void *fdt)
> +ENTRY_FUNCTION(start_skov_arm9cpu_xload_mmc, r0, r1, r2)
>  {
> -	struct at91sam926x_board_cfg cfg;
> +	const struct sam92_pmc_config sam92_pmc_config = {
> +		/* X-tal is 16.000 MHz so 16 / 4 * (31 + 1) = 200 */
> +		.diva = 14,
> +		.mula = 171,
> +	};
> +	sam9263_lowlevel_init(&sam92_pmc_config);

This is needlessly fragile. Compiler is within rights to never push
this to stack and to regenerate a relocation entry here that points
at .data, which has not yet been relocated.

> +	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);

Both sam9263_lowlevel_init and arm_cpu_lowlevel_init are global functions,
so LR will be pushed to stack in-between, yet stack is only initialized here
after.

Also ENTRY_FUNCTION is __naked on ARM32, so it's a bad idea to do more
than the absolutely necessary stuff here as GCC can generate very unexpected
code when it decides to spill to stack inside a naked function.

We have ENTRY_FUNCTION_WITHSTACK now that removes this footgun.
Please use that instead.

>  
> -	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
> -	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
> -	cfg.ebi_pio_is_peripha = true;
> -	cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
> +	relocate_to_current_adr();
> +	setup_c();

My preference would be set up ENTRY_FUNCTION_WITHSTACK, so you don't have
to write naked code. Call arm_cpu_lowlevel_init() first thing, so you have
active I-Cache. Then relocate and setup_c and only then do the SoC-specific setup.

> +pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu_xload_mmc
> +FILE_barebox-skov-arm9cpu-xload-mmc.img = start_skov_arm9cpu_xload_mmc.pblb
> +MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
> +image-$(CONFIG_MACH_SKOV_ARM9CPU) += barebox-skov-arm9cpu-xload-mmc.img
> +
>  pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu
>  FILE_barebox-skov-arm9cpu.img = start_skov_arm9cpu.pblb
>  MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000

Unrelated to your patch, but you might know the answer: Why is there a max PBL memory size here?
AFAIK, you use at91bootstrap to chainload barebox into DRAM, why do you need
a PBL size limit then?

Cheers,
Ahmad



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Re: [PATCH v1 7/8] ARM: at91: Add initialize function to sdramc

[Sam Ravnborg]

Hi Ahmad,

On Mon, May 16, 2022 at 12:47:52PM +0200, Ahmad Fatoum wrote:
> Hello Sam,
> 
> On 15.05.22 21:38, Sam Ravnborg wrote:
> > +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
> > +			       unsigned int sdram_address)
> > +{
> > +	unsigned int i;
> > +
> > +	/* Step#1 SDRAM feature must be in the configuration register */
> > +	sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
> > +
> > +	/* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
> > +
> > +	/* Step#3 The SDRAM memory type must be set in the Memory Device Register */
> > +	sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
> > +
> > +	/* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
> > +	for (i = 0; i < 1000; i++) ;
> 
> This and similar instances below must be replaced by proper delays.
> You can use early_udelay for this as you already initialize the PIT.
> 
> Did you test SDRAM worked with this setup? I assumed this to be at least
> one of the reasons current at91bootstrap fails to work with current compilers
> for the 9263. (Newer SoCs use a different DRAM controller and thus a different
> driver that doesn't use compile-time removable delay loops).

Thanks, I already looked at these with a question mark in my head but
then forgot about them - will fix.

And no - this is not yet tested, just ported from at91bootstrap.

	Sam

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Re: [PATCH v1 8/8] ARM: at91: Add xload support to skov-arm9cpu

[Sam Ravnborg]

Hi Ahmad,

On Mon, May 16, 2022 at 01:15:42PM +0200, Ahmad Fatoum wrote:
> Hello Sam,

Thanks for your feedback - very appreciated!

> 
> On 15.05.22 21:38, Sam Ravnborg wrote:
> > This updates skov-arm9cpu with xload support, and we can now
> > use barebox as a replacment for at91bootstrap.
> > 
> > Only boot via SD card is supported.
> > 
> > NOTE: Actual status
> > [x] dbgu support in pbl works (can print)
> > [x] Other init stuff ifdeffed out - from at91bootstrap
> > [ ] Check what the original code used for div/mul - there is some confusion
> > [ ] load barebox.bin and boots it. Right now mount fails
> 
> Is your SD-Card perhaps 2G or smaller? The AT91 PBL MCI functions
> assume high capacity (> 2G). It's a quite ugly thing, but
> finding out whether a card is High-Capacity or not happens
> during init phase and as we don't redo init in PBL...

>From the at91sam9263 datasheet:
"Boot ROM does not support high capacity SDCards."
 
Sounds like a very plausible explanation - and gives me something to go
after.

> High Capacity cards reference start block offset in sectors, while
> older cards use bytes. On i.MX, barebox just reads at offset 0
> and all is good, but on AT91, we need to do random access, so
> we need to decide whether to use sectors or bytes. Currently,
> the driver hardcodes the sector assumption. I found this to be
> the lesser evil to the alternative: having a full MMC stack in PBL. 
> 
> If that's indeed your issue, there's a heuristic possible:
> Try to mount for High-Capacity, if that fails, assume non-high
> capacity and try again. It's not 100%, but it's better than status quo.

I will try to find a nice way to tell that we shall go for a non-high
capacity in the first place.
And then I will dig into the sector versus byte thing afterwards.

> 
> > -static void __bare_init skov_arm9cpu_init(void *fdt)
> > +ENTRY_FUNCTION(start_skov_arm9cpu_xload_mmc, r0, r1, r2)
> >  {
> > -	struct at91sam926x_board_cfg cfg;
> > +	const struct sam92_pmc_config sam92_pmc_config = {
> > +		/* X-tal is 16.000 MHz so 16 / 4 * (31 + 1) = 200 */
> > +		.diva = 14,
> > +		.mula = 171,
> > +	};
> > +	sam9263_lowlevel_init(&sam92_pmc_config);
> 
> This is needlessly fragile. Compiler is within rights to never push
> this to stack and to regenerate a relocation entry here that points
> at .data, which has not yet been relocated.
> 
> > +	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE);
> 
> Both sam9263_lowlevel_init and arm_cpu_lowlevel_init are global functions,
> so LR will be pushed to stack in-between, yet stack is only initialized here
> after.
> 
> Also ENTRY_FUNCTION is __naked on ARM32, so it's a bad idea to do more
> than the absolutely necessary stuff here as GCC can generate very unexpected
> code when it decides to spill to stack inside a naked function.
> 
> We have ENTRY_FUNCTION_WITHSTACK now that removes this footgun.
> Please use that instead.
> 
> >  
> > -	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
> > -	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
> > -	cfg.ebi_pio_is_peripha = true;
> > -	cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
> > +	relocate_to_current_adr();
> > +	setup_c();
> 
> My preference would be set up ENTRY_FUNCTION_WITHSTACK, so you don't have
> to write naked code. Call arm_cpu_lowlevel_init() first thing, so you have
> active I-Cache. Then relocate and setup_c and only then do the SoC-specific setup.

Thanks - again very useful feedback. I will go along these lines.
> 
> > +pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu_xload_mmc
> > +FILE_barebox-skov-arm9cpu-xload-mmc.img = start_skov_arm9cpu_xload_mmc.pblb
> > +MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
> > +image-$(CONFIG_MACH_SKOV_ARM9CPU) += barebox-skov-arm9cpu-xload-mmc.img
> > +
> >  pblb-$(CONFIG_MACH_SKOV_ARM9CPU) += start_skov_arm9cpu
> >  FILE_barebox-skov-arm9cpu.img = start_skov_arm9cpu.pblb
> >  MAX_PBL_MEMORY_SIZE_start_skov_arm9cpu = 0x12000
> 
> Unrelated to your patch, but you might know the answer: Why is there a max PBL memory size here?
> AFAIK, you use at91bootstrap to chainload barebox into DRAM, why do you need
> a PBL size limit then?
The limit is from the old days where we tried to squeeze barebox into
the SRAM, so it could be used as the only bootloader - dropping the need
for at91bootstrap.
The new approach where we do a PBL barebox and then a full barebox is
much easier when you have first understood the concept.

I will drop the size restriction in my next patch stack.

We see other at91sam boards with the same restrictions due to the same
history. I think we can safely assume there is no use for barebox as
at91bootstrap and we can drop the size restrictions.
But then I am not happy to edit old boards that I cannot tests.

I have an at91sam9263-ek board and will update the board support
when I have skov-arm9cpu done. Focus is on the skov board first, as I
have more HW to play with here.

	Sam

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Re: [PATCH v1 8/8] ARM: at91: Add xload support to skov-arm9cpu

[Ahmad Fatoum]

Hello Sam,

On 16.05.22 17:28, Sam Ravnborg wrote:
> Hi Ahmad,
> 
> On Mon, May 16, 2022 at 01:15:42PM +0200, Ahmad Fatoum wrote:
>> Hello Sam,
> 
> Thanks for your feedback - very appreciated!

:)

>> Is your SD-Card perhaps 2G or smaller? The AT91 PBL MCI functions
>> assume high capacity (> 2G). It's a quite ugly thing, but
>> finding out whether a card is High-Capacity or not happens
>> during init phase and as we don't redo init in PBL...
> 
> From the at91sam9263 datasheet:
> "Boot ROM does not support high capacity SDCards."
>  
> Sounds like a very plausible explanation - and gives me something to go
> after.

Try toggling priv->highcapacity_card = 1; in atmel_mci_pbl.c

The original in atmel-sdhci-pbl.c had a comment:

 // FIXME can we determine this without leaving SD transfer mode? 
 priv->highcapacity_card = 1;                                  

>> High Capacity cards reference start block offset in sectors, while
>> older cards use bytes. On i.MX, barebox just reads at offset 0
>> and all is good, but on AT91, we need to do random access, so
>> we need to decide whether to use sectors or bytes. Currently,
>> the driver hardcodes the sector assumption. I found this to be
>> the lesser evil to the alternative: having a full MMC stack in PBL. 
>>
>> If that's indeed your issue, there's a heuristic possible:
>> Try to mount for High-Capacity, if that fails, assume non-high
>> capacity and try again. It's not 100%, but it's better than status quo.
> 
> I will try to find a nice way to tell that we shall go for a non-high
> capacity in the first place.
> And then I will dig into the sector versus byte thing afterwards.

It's probably best we move this setting into the _bio_init functions,
so callers are aware of the limitation and can e.g. for the 9263
always hardcode it as false. Heuristic would be nice to have,
but apparently it's not required for your use case.

>> Unrelated to your patch, but you might know the answer: Why is there a max PBL memory size here?
>> AFAIK, you use at91bootstrap to chainload barebox into DRAM, why do you need
>> a PBL size limit then?
> The limit is from the old days where we tried to squeeze barebox into
> the SRAM, so it could be used as the only bootloader - dropping the need
> for at91bootstrap.
> The new approach where we do a PBL barebox and then a full barebox is
> much easier when you have first understood the concept.
> 
> I will drop the size restriction in my next patch stack.
> 
> We see other at91sam boards with the same restrictions due to the same
> history. I think we can safely assume there is no use for barebox as
> at91bootstrap and we can drop the size restrictions.
> But then I am not happy to edit old boards that I cannot tests.
> 
> I have an at91sam9263-ek board and will update the board support
> when I have skov-arm9cpu done. Focus is on the skov board first, as I
> have more HW to play with here.

Ye, doing the change for your board only is fine by me. I just
wondered when I looked at the code. Thanks for clearing this up.

Cheers,
Ahmad

> 
> 	Sam
> 


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Re: [PATCH v1 8/8] ARM: at91: Add xload support to skov-arm9cpu

[Ahmad Fatoum]

On 16.05.22 17:35, Ahmad Fatoum wrote:
>> I will try to find a nice way to tell that we shall go for a non-high
>> capacity in the first place.
>> And then I will dig into the sector versus byte thing afterwards.
> 
> It's probably best we move this setting into the _bio_init functions,
> so callers are aware of the limitation and can e.g. for the 9263
> always hardcode it as false. Heuristic would be nice to have,
> but apparently it's not required for your use case.

Of course, I mean *out* of the _bio_init functions. Perhaps as a function
you can call *_bio_set_highcapacity(false);


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Re: [RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Sam Ravnborg]

On Sun, May 15, 2022 at 09:37:59PM +0200, Sam Ravnborg wrote:
> The following is the current set of patches so far to support
> PBL for the skov-arm9cpu.
> 
> The pwm is not really part of this - but it is part of the story.
> The patch-set was triggered when someone reported a bug in the 
> atmel pwm code. The code did not build - so I ported it over.
> Now I wanted to boot the target, but at91bootstrap no longer
> supports the at91sam9263. So I decided to try to make it work
> in barebox. I have tried this before and failed - but it should
> be possible...
> 
> What I have made is modelled on top of all the great work
> for other more modern atmel bouards.
> 
> This is an RFC - because the code does not yet work :-(
> It fails to mount the SD Card - for reasons I am yet to discover.

Hi Ahmad et al.

Just a quick update for you and the list.
I followed all your good suggestions and with this the PBL works and
loads barebox :-)

There are a few points on the TODO list I will address before posting a
v2, but just wanted to share the good news. No promises on the timeline
for an updated version - if anyone by chance would benefit from it
earlier then please let me know.

	Sam

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Re: [RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Sam Ravnborg]

Hi Ahmad,
On Sun, May 15, 2022 at 09:37:59PM +0200, Sam Ravnborg wrote:
> The following is the current set of patches so far to support
> PBL for the skov-arm9cpu.
...
> This is an RFC - because the code does not yet work :-(
> It fails to mount the SD Card - for reasons I am yet to discover.
> 
> Most of the code is attempted to be generic so we can use it
> for other targets.

I noticed you posted an issue on at91bootstrap about the sdram driver
today where you wrote that you are looking into at91samxxx bootstrap.

I have something that works - and I can post an updated series tomorrow.
I was planning to get my drm driver functional again and update the
binding before posting v2 - so I had a complete barebox + linux kernel
solution. But as weather is good, there is less time for hacking.

Let me know if it is of any help to post something.
Knowing your speed you may already be far ahead of what I made :-)

	Sam

Re: [RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Ahmad Fatoum]

Hello Sam,

On 28.06.22 21:23, Sam Ravnborg wrote:
> Hi Ahmad,
> On Sun, May 15, 2022 at 09:37:59PM +0200, Sam Ravnborg wrote:
>> The following is the current set of patches so far to support
>> PBL for the skov-arm9cpu.
> ...
>> This is an RFC - because the code does not yet work :-(
>> It fails to mount the SD Card - for reasons I am yet to discover.
>>
>> Most of the code is attempted to be generic so we can use it
>> for other targets.
> 
> I noticed you posted an issue on at91bootstrap about the sdram driver
> today where you wrote that you are looking into at91samxxx bootstrap.
> 
> I have something that works - and I can post an updated series tomorrow.
> I was planning to get my drm driver functional again and update the
> binding before posting v2 - so I had a complete barebox + linux kernel
> solution. But as weather is good, there is less time for hacking.
> 
> Let me know if it is of any help to post something.
> Knowing your speed you may already be far ahead of what I made :-)

No hurry. I figured we give the Atmel guys a heads up that the older
platforms are broken. I am not actively working on this.

Cheers,
Ahmad





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Re: [RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Sam Ravnborg]

Hi Ahmad,

On Tue, Jun 28, 2022 at 11:12:39PM +0200, Ahmad Fatoum wrote:
> Hello Sam,
> 
> On 28.06.22 21:23, Sam Ravnborg wrote:
> > Hi Ahmad,
> > On Sun, May 15, 2022 at 09:37:59PM +0200, Sam Ravnborg wrote:
> >> The following is the current set of patches so far to support
> >> PBL for the skov-arm9cpu.
> > ...
> >> This is an RFC - because the code does not yet work :-(
> >> It fails to mount the SD Card - for reasons I am yet to discover.
> >>
> >> Most of the code is attempted to be generic so we can use it
> >> for other targets.
> > 
> > I noticed you posted an issue on at91bootstrap about the sdram driver
> > today where you wrote that you are looking into at91samxxx bootstrap.
> > 
> > I have something that works - and I can post an updated series tomorrow.
> > I was planning to get my drm driver functional again and update the
> > binding before posting v2 - so I had a complete barebox + linux kernel
> > solution. But as weather is good, there is less time for hacking.
> > 
> > Let me know if it is of any help to post something.
> > Knowing your speed you may already be far ahead of what I made :-)
> 
> No hurry. I figured we give the Atmel guys a heads up that the older
> platforms are broken. I am not actively working on this.
OK, thanks for the quick update.
I already went ahead and posted what I have as the commits was ready,
so it was quick to do. You can just ignore, but ofc any comments are
welcome and I consider most of the patches ready.

	Sam

Re: [RFC PATCH v1 0/8] ARM: at91: Add pbl support to skov-arm9cpu

[Ahmad Fatoum]

Hi Sam,

On 28.06.22 23:18, Sam Ravnborg wrote:
> Hi Ahmad,
> 
> On Tue, Jun 28, 2022 at 11:12:39PM +0200, Ahmad Fatoum wrote:
>> Hello Sam,
>>
>> On 28.06.22 21:23, Sam Ravnborg wrote:
>>> Hi Ahmad,
>>> On Sun, May 15, 2022 at 09:37:59PM +0200, Sam Ravnborg wrote:
>>>> The following is the current set of patches so far to support
>>>> PBL for the skov-arm9cpu.
>>> ...
>>>> This is an RFC - because the code does not yet work :-(
>>>> It fails to mount the SD Card - for reasons I am yet to discover.
>>>>
>>>> Most of the code is attempted to be generic so we can use it
>>>> for other targets.
>>>
>>> I noticed you posted an issue on at91bootstrap about the sdram driver
>>> today where you wrote that you are looking into at91samxxx bootstrap.
>>>
>>> I have something that works - and I can post an updated series tomorrow.
>>> I was planning to get my drm driver functional again and update the
>>> binding before posting v2 - so I had a complete barebox + linux kernel
>>> solution. But as weather is good, there is less time for hacking.
>>>
>>> Let me know if it is of any help to post something.
>>> Knowing your speed you may already be far ahead of what I made :-)
>>
>> No hurry. I figured we give the Atmel guys a heads up that the older
>> platforms are broken. I am not actively working on this.
> OK, thanks for the quick update.
> I already went ahead and posted what I have as the commits was ready,
> so it was quick to do. You can just ignore, but ofc any comments are
> welcome and I consider most of the patches ready.

I agree, Looked good from a quick glance. I will give this a more thorough
review tomorrow.

Cheers,
Ahmad

> 
> 	Sam
> 


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Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
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