* [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:06 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros Denis Orlov
` (17 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
QEMU is able to emulate malta machine with a variety of MIPS CPUs,
including MIPS64 ones, so allow to compile barebox for such
configurations.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 70d85690da..ab8c8cf176 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -70,8 +70,11 @@ config MACH_MIPS_MALTA
select CSRC_R4K_LIB
select DRIVER_SERIAL_NS16550
select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_CPU_MIPS64_R2
select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select HAS_DEBUG_LL
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config
2023-06-05 20:10 ` [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config Denis Orlov
@ 2023-06-06 8:06 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:06 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> QEMU is able to emulate malta machine with a variety of MIPS CPUs,
> including MIPS64 ones, so allow to compile barebox for such
> configurations.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/Kconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 70d85690da..ab8c8cf176 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -70,8 +70,11 @@ config MACH_MIPS_MALTA
> select CSRC_R4K_LIB
> select DRIVER_SERIAL_NS16550
> select SYS_HAS_CPU_MIPS32_R1
> + select SYS_HAS_CPU_MIPS64_R1
> select SYS_HAS_CPU_MIPS32_R2
> + select SYS_HAS_CPU_MIPS64_R2
> select SYS_SUPPORTS_32BIT_KERNEL
> + select SYS_SUPPORTS_64BIT_KERNEL
> select SYS_SUPPORTS_BIG_ENDIAN
> select SYS_SUPPORTS_LITTLE_ENDIAN
> select HAS_DEBUG_LL
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
2023-06-05 20:10 ` [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:03 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled Denis Orlov
` (16 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
KSEG macro is not available when compiling with CONFIG_64BIT enabled, so
use CKSEG instead.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boards/qemu-malta/lowlevel.S | 4 ++--
arch/mips/mach-malta/pci.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
index 98821e0426..541d62fc2a 100644
--- a/arch/mips/boards/qemu-malta/lowlevel.S
+++ b/arch/mips/boards/qemu-malta/lowlevel.S
@@ -56,14 +56,14 @@ __start:
*/
/* move GT64120 registers to 0x1be00000 */
- li t1, KSEG1ADDR(GT_DEF_BASE)
+ li t1, CKSEG1ADDR(GT_DEF_BASE)
li t0, GT_LD(MIPS_GT_BASE)
sw t0, GT_ISD_OFS(t1)
/*
* setup MEM-to-PCI0 mapping
*/
- li t1, KSEG1ADDR(MIPS_GT_BASE)
+ li t1, CKSEG1ADDR(MIPS_GT_BASE)
/* setup PCI0 io window */
li t0, GT_LD(0x18000000)
diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
index 113b94fe23..0ab239f509 100644
--- a/arch/mips/mach-malta/pci.c
+++ b/arch/mips/mach-malta/pci.c
@@ -136,7 +136,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
static resource_size_t gt64xxx_res_start(struct pci_bus *bus,
resource_size_t res_addr)
{
- return KSEG0ADDR(res_addr);
+ return CKSEG0ADDR(res_addr);
}
struct pci_ops gt64xxx_pci0_ops = {
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros
2023-06-05 20:10 ` [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros Denis Orlov
@ 2023-06-06 8:03 ` Ahmad Fatoum
2023-06-06 9:14 ` Denis Orlov
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:03 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> KSEG macro is not available when compiling with CONFIG_64BIT enabled, so
> use CKSEG instead.
If they're interchangeable, why do we need KSEG?
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
> ---
> arch/mips/boards/qemu-malta/lowlevel.S | 4 ++--
> arch/mips/mach-malta/pci.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
> index 98821e0426..541d62fc2a 100644
> --- a/arch/mips/boards/qemu-malta/lowlevel.S
> +++ b/arch/mips/boards/qemu-malta/lowlevel.S
> @@ -56,14 +56,14 @@ __start:
> */
>
> /* move GT64120 registers to 0x1be00000 */
> - li t1, KSEG1ADDR(GT_DEF_BASE)
> + li t1, CKSEG1ADDR(GT_DEF_BASE)
> li t0, GT_LD(MIPS_GT_BASE)
> sw t0, GT_ISD_OFS(t1)
>
> /*
> * setup MEM-to-PCI0 mapping
> */
> - li t1, KSEG1ADDR(MIPS_GT_BASE)
> + li t1, CKSEG1ADDR(MIPS_GT_BASE)
>
> /* setup PCI0 io window */
> li t0, GT_LD(0x18000000)
> diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
> index 113b94fe23..0ab239f509 100644
> --- a/arch/mips/mach-malta/pci.c
> +++ b/arch/mips/mach-malta/pci.c
> @@ -136,7 +136,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
> static resource_size_t gt64xxx_res_start(struct pci_bus *bus,
> resource_size_t res_addr)
> {
> - return KSEG0ADDR(res_addr);
> + return CKSEG0ADDR(res_addr);
> }
>
> struct pci_ops gt64xxx_pci0_ops = {
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros
2023-06-06 8:03 ` Ahmad Fatoum
@ 2023-06-06 9:14 ` Denis Orlov
0 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-06 9:14 UTC (permalink / raw)
To: Ahmad Fatoum
On Tue, 6 Jun 2023 at 11:03, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> On 05.06.23 22:10, Denis Orlov wrote:
> > KSEG macro is not available when compiling with CONFIG_64BIT enabled, so
> > use CKSEG instead.
>
> If they're interchangeable, why do we need KSEG?
Hmm, I think maybe we don't. We can replace every instance of KSEG with
CKSEG without any change in functionality, except for the fact that the
latter will compile with 64BIT enabled. Overall, it seems that a lot of
MIPS-specific headers were taken from Linux as is back when the support
for MIPS was being added to barebox. Those were already old and crufty
back then but there are also a lot of definitions that we neither need
nor use, yet which unnecessarily complicate the code. I might try
cleaning up those headers sometime in the future.
Regards,
Denis
>
> >
> > Signed-off-by: Denis Orlov <denorl2009@gmail.com>
> > ---
> > arch/mips/boards/qemu-malta/lowlevel.S | 4 ++--
> > arch/mips/mach-malta/pci.c | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
> > index 98821e0426..541d62fc2a 100644
> > --- a/arch/mips/boards/qemu-malta/lowlevel.S
> > +++ b/arch/mips/boards/qemu-malta/lowlevel.S
> > @@ -56,14 +56,14 @@ __start:
> > */
> >
> > /* move GT64120 registers to 0x1be00000 */
> > - li t1, KSEG1ADDR(GT_DEF_BASE)
> > + li t1, CKSEG1ADDR(GT_DEF_BASE)
> > li t0, GT_LD(MIPS_GT_BASE)
> > sw t0, GT_ISD_OFS(t1)
> >
> > /*
> > * setup MEM-to-PCI0 mapping
> > */
> > - li t1, KSEG1ADDR(MIPS_GT_BASE)
> > + li t1, CKSEG1ADDR(MIPS_GT_BASE)
> >
> > /* setup PCI0 io window */
> > li t0, GT_LD(0x18000000)
> > diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
> > index 113b94fe23..0ab239f509 100644
> > --- a/arch/mips/mach-malta/pci.c
> > +++ b/arch/mips/mach-malta/pci.c
> > @@ -136,7 +136,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
> > static resource_size_t gt64xxx_res_start(struct pci_bus *bus,
> > resource_size_t res_addr)
> > {
> > - return KSEG0ADDR(res_addr);
> > + return CKSEG0ADDR(res_addr);
> > }
> >
> > struct pci_ops gt64xxx_pci0_ops = {
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
2023-06-05 20:10 ` [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config Denis Orlov
2023-06-05 20:10 ` [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:08 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions Denis Orlov
` (15 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Use CKSEG instead of KSEG, allowing it to compile on 64BIT
configurations. Also make sure that we do not truncate target
relocation address by writing it into a 32-bit wide variable.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/lib/reloc.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index b084a88be7..3c845a9663 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -108,8 +108,7 @@ static void apply_reloc(unsigned int type, void *addr, long off)
void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
{
- unsigned long addr, length, bss_len;
- u32 relocaddr, new_stack;
+ unsigned long addr, length, bss_len, relocaddr, new_stack;
uint8_t *buf;
unsigned int type;
long off;
@@ -121,9 +120,9 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
length = __bss_stop - __image_start;
relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K);
if (IS_ENABLED(CONFIG_MMU)) {
- relocaddr = KSEG0ADDR(relocaddr);
+ relocaddr = CKSEG0ADDR(relocaddr);
} else {
- relocaddr = KSEG1ADDR(relocaddr);
+ relocaddr = CKSEG1ADDR(relocaddr);
}
new_stack = relocaddr - MALLOC_SIZE - 16;
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled
2023-06-05 20:10 ` [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled Denis Orlov
@ 2023-06-06 8:08 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:08 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> Use CKSEG instead of KSEG, allowing it to compile on 64BIT
> configurations. Also make sure that we do not truncate target
> relocation address by writing it into a 32-bit wide variable.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewd-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/lib/reloc.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
> index b084a88be7..3c845a9663 100644
> --- a/arch/mips/lib/reloc.c
> +++ b/arch/mips/lib/reloc.c
> @@ -108,8 +108,7 @@ static void apply_reloc(unsigned int type, void *addr, long off)
>
> void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
> {
> - unsigned long addr, length, bss_len;
> - u32 relocaddr, new_stack;
> + unsigned long addr, length, bss_len, relocaddr, new_stack;
> uint8_t *buf;
> unsigned int type;
> long off;
> @@ -121,9 +120,9 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
> length = __bss_stop - __image_start;
> relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K);
> if (IS_ENABLED(CONFIG_MMU)) {
> - relocaddr = KSEG0ADDR(relocaddr);
> + relocaddr = CKSEG0ADDR(relocaddr);
> } else {
> - relocaddr = KSEG1ADDR(relocaddr);
> + relocaddr = CKSEG1ADDR(relocaddr);
> }
> new_stack = relocaddr - MALLOC_SIZE - 16;
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (2 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:13 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 05/17] MIPS: pbl: use o32/n64 compatible " Denis Orlov
` (14 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This allows to write generic assembly code that will compile under both
o32 and n64 ABIs, as otherwise the register definitions would conflict.
Taken from Linux kernel sources, commit 'MIPS: O32: Provide definition
of registers ta0 .. ta3.' (3ba1e543ab4b02640d396098f2f6a199560d5f2d).
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/include/asm/regdef.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 1300251661..df87582e8e 100644
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -3,6 +3,8 @@
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ * written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
@@ -27,9 +29,13 @@
#define t2 $10
#define t3 $11
#define t4 $12
+#define ta0 $12
#define t5 $13
+#define ta1 $13
#define t6 $14
+#define ta2 $14
#define t7 $15
+#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions
2023-06-05 20:10 ` [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions Denis Orlov
@ 2023-06-06 8:13 ` Ahmad Fatoum
2023-06-06 9:38 ` Denis Orlov
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:13 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> This allows to write generic assembly code that will compile under both
> o32 and n64 ABIs, as otherwise the register definitions would conflict.
>
> Taken from Linux kernel sources, commit 'MIPS: O32: Provide definition
> of registers ta0 .. ta3.' (3ba1e543ab4b02640d396098f2f6a199560d5f2d).
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
I must say, this file looks odd though. _MIPS_SIM is apparently
defined by the compiler and it's compared against _MIPS_SIM_ABI32,
which barebox defines...
> ---
> arch/mips/include/asm/regdef.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
> index 1300251661..df87582e8e 100644
> --- a/arch/mips/include/asm/regdef.h
> +++ b/arch/mips/include/asm/regdef.h
> @@ -3,6 +3,8 @@
> * Copyright (C) 1985 MIPS Computer Systems, Inc.
> * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
> * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
> + * Copyright (C) 2011 Wind River Systems,
> + * written by Ralf Baechle <ralf@linux-mips.org>
> */
> #ifndef _ASM_REGDEF_H
> #define _ASM_REGDEF_H
> @@ -27,9 +29,13 @@
> #define t2 $10
> #define t3 $11
> #define t4 $12
> +#define ta0 $12
> #define t5 $13
> +#define ta1 $13
> #define t6 $14
> +#define ta2 $14
> #define t7 $15
> +#define ta3 $15
> #define s0 $16 /* callee saved */
> #define s1 $17
> #define s2 $18
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions
2023-06-06 8:13 ` Ahmad Fatoum
@ 2023-06-06 9:38 ` Denis Orlov
0 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-06 9:38 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, 6 Jun 2023 at 11:13, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> On 05.06.23 22:10, Denis Orlov wrote:
> > This allows to write generic assembly code that will compile under both
> > o32 and n64 ABIs, as otherwise the register definitions would conflict.
> >
> > Taken from Linux kernel sources, commit 'MIPS: O32: Provide definition
> > of registers ta0 .. ta3.' (3ba1e543ab4b02640d396098f2f6a199560d5f2d).
> >
> > Signed-off-by: Denis Orlov <denorl2009@gmail.com>
>
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> I must say, this file looks odd though. _MIPS_SIM is apparently
> defined by the compiler and it's compared against _MIPS_SIM_ABI32,
> which barebox defines...
AFAICS, the compiler defines _MIPS_SIM with the value of some number,
_MIPS_SIM_ABI32, on the other hand, gives a symbolic representation
(as another define) for this number. This just adds more sense to what
we are actually comparing against. But this header also seems to be
quite old, maybe nowadays there is a better way to check for those.
Regards,
Denis
>
> > ---
> > arch/mips/include/asm/regdef.h | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
> > index 1300251661..df87582e8e 100644
> > --- a/arch/mips/include/asm/regdef.h
> > +++ b/arch/mips/include/asm/regdef.h
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 1985 MIPS Computer Systems, Inc.
> > * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
> > * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
> > + * Copyright (C) 2011 Wind River Systems,
> > + * written by Ralf Baechle <ralf@linux-mips.org>
> > */
> > #ifndef _ASM_REGDEF_H
> > #define _ASM_REGDEF_H
> > @@ -27,9 +29,13 @@
> > #define t2 $10
> > #define t3 $11
> > #define t4 $12
> > +#define ta0 $12
> > #define t5 $13
> > +#define ta1 $13
> > #define t6 $14
> > +#define ta2 $14
> > #define t7 $15
> > +#define ta3 $15
> > #define s0 $16 /* callee saved */
> > #define s1 $17
> > #define s2 $18
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 05/17] MIPS: pbl: use o32/n64 compatible register definitions
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (3 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:20 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 06/17] MIPS: pbl: fix linking errors with CONFIG_64BIT Denis Orlov
` (13 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This allows to compile PBL code with n64 ABI, which we use when
CONFIG_64BIT is set.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/include/asm/pbl_macros.h | 28 ++++++++++++++--------------
arch/mips/include/asm/pbl_nmon.h | 10 +++++-----
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index c62910ff60..e60af38442 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -30,9 +30,9 @@
.set noreorder
li t9, \addr
li t8, \val
- lw t7, 0(t9)
- or t7, t8
- sw t7, 0(t9)
+ lw ta3, 0(t9)
+ or ta3, t8
+ sw ta3, 0(t9)
.set pop
.endm
@@ -41,10 +41,10 @@
.set noreorder
li t9, \addr
li t8, \clr
- lw t7, 0(t9)
+ lw ta3, 0(t9)
not t8, t8
- and t7, t8
- sw t7, 0(t9)
+ and ta3, t8
+ sw ta3, 0(t9)
.set pop
.endm
@@ -123,15 +123,15 @@
#define WSIZE 4
copy_loop:
/* copy from source address [a0] */
- lw t4, WSIZE * 0(a0)
- lw t5, WSIZE * 1(a0)
- lw t6, WSIZE * 2(a0)
- lw t7, WSIZE * 3(a0)
+ lw ta0, WSIZE * 0(a0)
+ lw ta1, WSIZE * 1(a0)
+ lw ta2, WSIZE * 2(a0)
+ lw ta3, WSIZE * 3(a0)
/* copy to target address [a1] */
- sw t4, WSIZE * 0(a1)
- sw t5, WSIZE * 1(a1)
- sw t6, WSIZE * 2(a1)
- sw t7, WSIZE * 3(a1)
+ sw ta0, WSIZE * 0(a1)
+ sw ta1, WSIZE * 1(a1)
+ sw ta2, WSIZE * 2(a1)
+ sw ta3, WSIZE * 3(a1)
addi a0, WSIZE * 4
subu t3, a0, a2
blez t3, copy_loop
diff --git a/arch/mips/include/asm/pbl_nmon.h b/arch/mips/include/asm/pbl_nmon.h
index 0e4ec39967..7c8ec9d204 100644
--- a/arch/mips/include/asm/pbl_nmon.h
+++ b/arch/mips/include/asm/pbl_nmon.h
@@ -39,12 +39,12 @@
.set push
.set reorder
- move t6, a0
- li t5, 32
+ move ta2, a0
+ li ta1, 32
202:
- addi t5, t5, -4
- srlv a0, t6, t5
+ addi ta1, ta1, -4
+ srlv a0, ta2, ta1
/* output one hex digit */
andi a0, a0, 15
@@ -57,7 +57,7 @@
debug_ll_outc_a0
- bgtz t5, 202b
+ bgtz ta1, 202b
.set pop
#endif /* CONFIG_DEBUG_LL */
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 05/17] MIPS: pbl: use o32/n64 compatible register definitions
2023-06-05 20:10 ` [PATCH 05/17] MIPS: pbl: use o32/n64 compatible " Denis Orlov
@ 2023-06-06 8:20 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:20 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> This allows to compile PBL code with n64 ABI, which we use when
> CONFIG_64BIT is set.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/include/asm/pbl_macros.h | 28 ++++++++++++++--------------
> arch/mips/include/asm/pbl_nmon.h | 10 +++++-----
> 2 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
> index c62910ff60..e60af38442 100644
> --- a/arch/mips/include/asm/pbl_macros.h
> +++ b/arch/mips/include/asm/pbl_macros.h
> @@ -30,9 +30,9 @@
> .set noreorder
> li t9, \addr
> li t8, \val
> - lw t7, 0(t9)
> - or t7, t8
> - sw t7, 0(t9)
> + lw ta3, 0(t9)
> + or ta3, t8
> + sw ta3, 0(t9)
> .set pop
> .endm
>
> @@ -41,10 +41,10 @@
> .set noreorder
> li t9, \addr
> li t8, \clr
> - lw t7, 0(t9)
> + lw ta3, 0(t9)
> not t8, t8
> - and t7, t8
> - sw t7, 0(t9)
> + and ta3, t8
> + sw ta3, 0(t9)
> .set pop
> .endm
>
> @@ -123,15 +123,15 @@
> #define WSIZE 4
> copy_loop:
> /* copy from source address [a0] */
> - lw t4, WSIZE * 0(a0)
> - lw t5, WSIZE * 1(a0)
> - lw t6, WSIZE * 2(a0)
> - lw t7, WSIZE * 3(a0)
> + lw ta0, WSIZE * 0(a0)
> + lw ta1, WSIZE * 1(a0)
> + lw ta2, WSIZE * 2(a0)
> + lw ta3, WSIZE * 3(a0)
> /* copy to target address [a1] */
> - sw t4, WSIZE * 0(a1)
> - sw t5, WSIZE * 1(a1)
> - sw t6, WSIZE * 2(a1)
> - sw t7, WSIZE * 3(a1)
> + sw ta0, WSIZE * 0(a1)
> + sw ta1, WSIZE * 1(a1)
> + sw ta2, WSIZE * 2(a1)
> + sw ta3, WSIZE * 3(a1)
> addi a0, WSIZE * 4
> subu t3, a0, a2
> blez t3, copy_loop
> diff --git a/arch/mips/include/asm/pbl_nmon.h b/arch/mips/include/asm/pbl_nmon.h
> index 0e4ec39967..7c8ec9d204 100644
> --- a/arch/mips/include/asm/pbl_nmon.h
> +++ b/arch/mips/include/asm/pbl_nmon.h
> @@ -39,12 +39,12 @@
> .set push
> .set reorder
>
> - move t6, a0
> - li t5, 32
> + move ta2, a0
> + li ta1, 32
>
> 202:
> - addi t5, t5, -4
> - srlv a0, t6, t5
> + addi ta1, ta1, -4
> + srlv a0, ta2, ta1
>
> /* output one hex digit */
> andi a0, a0, 15
> @@ -57,7 +57,7 @@
>
> debug_ll_outc_a0
>
> - bgtz t5, 202b
> + bgtz ta1, 202b
>
> .set pop
> #endif /* CONFIG_DEBUG_LL */
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 06/17] MIPS: pbl: fix linking errors with CONFIG_64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (4 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 05/17] MIPS: pbl: use o32/n64 compatible " Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros Denis Orlov
` (12 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
For some reasons, object file format was not passed to the linker when
linking PBL, leading for a bunch of "ABI is incompatible with that of
the selected emulation" errors. Fix it, and also remove duplicate flags
being passed when linking barebox proper.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/Makefile | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 345e703d33..bad6e574c4 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -45,8 +45,8 @@ mips-ldflags-y += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL
endif
KBUILD_LDFLAGS += $(mips-ldflags-y) -m $(ld-emul)
-LDFLAGS_barebox += $(mips-ldflags-y)
-LDFLAGS_pbl += $(mips-ldflags-y)
+LDFLAGS_barebox += $(KBUILD_LDFLAGS)
+LDFLAGS_pbl += $(KBUILD_LDFLAGS)
#
# CPU-dependent compiler/assembler options for optimization.
@@ -100,7 +100,7 @@ KBUILD_CFLAGS += $(cflags-y)
lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds
-cmd_barebox__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_barebox) -o $@ \
+cmd_barebox__ ?= $(LD) $(LDFLAGS_barebox) -o $@ \
-T $(BAREBOX_LDS) \
--whole-archive $(BAREBOX_OBJS) --no-whole-archive \
$(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^); \
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (5 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 06/17] MIPS: pbl: fix linking errors with CONFIG_64BIT Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:23 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT Denis Orlov
` (11 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Use PTR_* for various arithmetic operations on pointers, and also use
PTR_LA instead of simple 'la' instruction, as it will correctly handle
loading 64-bit addresses from non-32-bit-compatible virtual memory
segments.
This fixes "la used to load 64-bit address; recommend using dla instead"
warnings when compiling assembly code with CONFIG_64BIT.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/start.S | 2 +-
arch/mips/include/asm/asm.h | 10 +++++-----
arch/mips/include/asm/debug_ll_ns16550.h | 6 +++---
arch/mips/include/asm/pbl_macros.h | 22 +++++++++++-----------
arch/mips/lib/genex.S | 8 ++++----
5 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index c1cd2d9dd5..5f134f9ae9 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -34,7 +34,7 @@ EXPORT(_start)
move a0, s0
move a1, s1
move a2, s2
- la v0, relocate_code
+ PTR_LA v0, relocate_code
jal v0
nop
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 69931662ff..c699542a55 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -94,10 +94,10 @@ EXPORT(symbol)
copy_to_link_location symbol; \
stack_setup; \
\
- la a0, __dtb_ ## dtb##_start; \
- la a1, __dtb_ ## dtb##_end; \
- li a2, ram_size; \
- la v0, pbl_main_entry; \
+ PTR_LA a0, __dtb_ ## dtb##_start; \
+ PTR_LA a1, __dtb_ ## dtb##_end; \
+ PTR_LI a2, ram_size; \
+ PTR_LA v0, pbl_main_entry; \
jal v0; \
nop; \
\
@@ -122,7 +122,7 @@ EXPORT(symbol)
/* Call some code from .text section. \
* It is needed to keep same linker script for \
* all images. */ \
- la v0, mips_dead_end; \
+ PTR_LA v0, mips_dead_end; \
jal v0; \
nop;
diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
index 703bfaee77..7cfd844cb6 100644
--- a/arch/mips/include/asm/debug_ll_ns16550.h
+++ b/arch/mips/include/asm/debug_ll_ns16550.h
@@ -60,7 +60,7 @@ static inline void PUTC_LL(char ch)
.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR
#ifdef CONFIG_DEBUG_LL
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
li t1, UART_LCR_DLAB /* DLAB on */
sb t1, UART_LCR(t0) /* Write it out */
@@ -83,7 +83,7 @@ static inline void PUTC_LL(char ch)
.set push
.set reorder
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
201: lbu t1, UART_LSR(t0) /* get line status */
andi t1, t1, UART_LSR_THRE /* check for transmitter empty */
@@ -126,7 +126,7 @@ static inline void PUTC_LL(char ch)
.set push
.set reorder
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
/* get line status and check for data present */
lbu t1, UART_LSR(t0)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index e60af38442..1fba690c8c 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -73,7 +73,7 @@
.macro pbl_probe_mem ret1 ret2 addr
.set push
.set noreorder
- la \ret1, \addr
+ PTR_LA \ret1, \addr
sw zero, 0(\ret1)
li \ret2, 0x12345678
sw \ret2, 0(\ret1)
@@ -97,7 +97,7 @@
move \temp, ra # preserve ra beforehand
bal 255f
nop
-255: addiu \rd, ra, \label - 255b # label is assumed to be
+255: PTR_ADDIU \rd, ra, \label - 255b # label is assumed to be
move ra, \temp # within pc +/- 32KB
.set pop
.endm
@@ -110,15 +110,15 @@
ADR a0, \start_addr, t1 /* a0 <- pc-relative
position of start_addr */
- la a1, \start_addr /* a1 <- link (RAM) start_addr address */
+ PTR_LA a1, \start_addr /* a1 <- link (RAM) start_addr address */
beq a0, a1, copy_loop_exit
nop
- la t0, \start_addr
- la t1, __bss_start
- subu t2, t1, t0 /* t2 <- size of pbl */
- addu a2, a0, t2 /* a2 <- source end address */
+ PTR_LA t0, \start_addr
+ PTR_LA t1, __bss_start
+ PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */
+ PTR_ADDU a2, a0, t2 /* a2 <- source end address */
#define WSIZE 4
copy_loop:
@@ -132,10 +132,10 @@
sw ta1, WSIZE * 1(a1)
sw ta2, WSIZE * 2(a1)
sw ta3, WSIZE * 3(a1)
- addi a0, WSIZE * 4
- subu t3, a0, a2
+ PTR_ADDI a0, WSIZE * 4
+ PTR_SUBU t3, a0, a2
blez t3, copy_loop
- addi a1, WSIZE * 4
+ PTR_ADDI a1, WSIZE * 4
copy_loop_exit:
@@ -196,7 +196,7 @@
.set noreorder
/* set stack pointer; reserve four 32-bit argument slots */
- la sp, (TEXT_BASE - MALLOC_SIZE - 16)
+ PTR_LA sp, (TEXT_BASE - MALLOC_SIZE - 16)
.set pop
.endm
diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
index d75a652e4d..b9d18fc394 100644
--- a/arch/mips/lib/genex.S
+++ b/arch/mips/lib/genex.S
@@ -14,7 +14,7 @@
/* Exception vector */
NESTED(handle_reserved, 0, sp)
SAVE_ALL
- la k0, barebox_exc_handler
+ PTR_LA k0, barebox_exc_handler
jal k0
move a0, sp
/* will never return here */
@@ -24,10 +24,10 @@ NESTED(handle_reserved, 0, sp)
NESTED(except_vec3_generic, 0, sp)
.set noat
mfc0 k1, CP0_CAUSE
- la k0, exception_handlers
+ PTR_LA k0, exception_handlers
andi k1, k1, 0x7c
- addu k0, k0, k1
- lw k0, (k0)
+ PTR_ADDU k0, k0, k1
+ PTR_L k0, (k0)
nop
jr k0
nop
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros
2023-06-05 20:10 ` [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros Denis Orlov
@ 2023-06-06 8:23 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:23 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> Use PTR_* for various arithmetic operations on pointers, and also use
> PTR_LA instead of simple 'la' instruction, as it will correctly handle
> loading 64-bit addresses from non-32-bit-compatible virtual memory
> segments.
>
> This fixes "la used to load 64-bit address; recommend using dla instead"
> warnings when compiling assembly code with CONFIG_64BIT.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/boot/start.S | 2 +-
> arch/mips/include/asm/asm.h | 10 +++++-----
> arch/mips/include/asm/debug_ll_ns16550.h | 6 +++---
> arch/mips/include/asm/pbl_macros.h | 22 +++++++++++-----------
> arch/mips/lib/genex.S | 8 ++++----
> 5 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
> index c1cd2d9dd5..5f134f9ae9 100644
> --- a/arch/mips/boot/start.S
> +++ b/arch/mips/boot/start.S
> @@ -34,7 +34,7 @@ EXPORT(_start)
> move a0, s0
> move a1, s1
> move a2, s2
> - la v0, relocate_code
> + PTR_LA v0, relocate_code
> jal v0
> nop
>
> diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
> index 69931662ff..c699542a55 100644
> --- a/arch/mips/include/asm/asm.h
> +++ b/arch/mips/include/asm/asm.h
> @@ -94,10 +94,10 @@ EXPORT(symbol)
> copy_to_link_location symbol; \
> stack_setup; \
> \
> - la a0, __dtb_ ## dtb##_start; \
> - la a1, __dtb_ ## dtb##_end; \
> - li a2, ram_size; \
> - la v0, pbl_main_entry; \
> + PTR_LA a0, __dtb_ ## dtb##_start; \
> + PTR_LA a1, __dtb_ ## dtb##_end; \
> + PTR_LI a2, ram_size; \
> + PTR_LA v0, pbl_main_entry; \
> jal v0; \
> nop; \
> \
> @@ -122,7 +122,7 @@ EXPORT(symbol)
> /* Call some code from .text section. \
> * It is needed to keep same linker script for \
> * all images. */ \
> - la v0, mips_dead_end; \
> + PTR_LA v0, mips_dead_end; \
> jal v0; \
> nop;
>
> diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
> index 703bfaee77..7cfd844cb6 100644
> --- a/arch/mips/include/asm/debug_ll_ns16550.h
> +++ b/arch/mips/include/asm/debug_ll_ns16550.h
> @@ -60,7 +60,7 @@ static inline void PUTC_LL(char ch)
>
> .macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR
> #ifdef CONFIG_DEBUG_LL
> - la t0, DEBUG_LL_UART_ADDR
> + PTR_LA t0, DEBUG_LL_UART_ADDR
>
> li t1, UART_LCR_DLAB /* DLAB on */
> sb t1, UART_LCR(t0) /* Write it out */
> @@ -83,7 +83,7 @@ static inline void PUTC_LL(char ch)
> .set push
> .set reorder
>
> - la t0, DEBUG_LL_UART_ADDR
> + PTR_LA t0, DEBUG_LL_UART_ADDR
>
> 201: lbu t1, UART_LSR(t0) /* get line status */
> andi t1, t1, UART_LSR_THRE /* check for transmitter empty */
> @@ -126,7 +126,7 @@ static inline void PUTC_LL(char ch)
> .set push
> .set reorder
>
> - la t0, DEBUG_LL_UART_ADDR
> + PTR_LA t0, DEBUG_LL_UART_ADDR
>
> /* get line status and check for data present */
> lbu t1, UART_LSR(t0)
> diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
> index e60af38442..1fba690c8c 100644
> --- a/arch/mips/include/asm/pbl_macros.h
> +++ b/arch/mips/include/asm/pbl_macros.h
> @@ -73,7 +73,7 @@
> .macro pbl_probe_mem ret1 ret2 addr
> .set push
> .set noreorder
> - la \ret1, \addr
> + PTR_LA \ret1, \addr
> sw zero, 0(\ret1)
> li \ret2, 0x12345678
> sw \ret2, 0(\ret1)
> @@ -97,7 +97,7 @@
> move \temp, ra # preserve ra beforehand
> bal 255f
> nop
> -255: addiu \rd, ra, \label - 255b # label is assumed to be
> +255: PTR_ADDIU \rd, ra, \label - 255b # label is assumed to be
> move ra, \temp # within pc +/- 32KB
> .set pop
> .endm
> @@ -110,15 +110,15 @@
> ADR a0, \start_addr, t1 /* a0 <- pc-relative
> position of start_addr */
>
> - la a1, \start_addr /* a1 <- link (RAM) start_addr address */
> + PTR_LA a1, \start_addr /* a1 <- link (RAM) start_addr address */
>
> beq a0, a1, copy_loop_exit
> nop
>
> - la t0, \start_addr
> - la t1, __bss_start
> - subu t2, t1, t0 /* t2 <- size of pbl */
> - addu a2, a0, t2 /* a2 <- source end address */
> + PTR_LA t0, \start_addr
> + PTR_LA t1, __bss_start
> + PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */
> + PTR_ADDU a2, a0, t2 /* a2 <- source end address */
>
> #define WSIZE 4
> copy_loop:
> @@ -132,10 +132,10 @@
> sw ta1, WSIZE * 1(a1)
> sw ta2, WSIZE * 2(a1)
> sw ta3, WSIZE * 3(a1)
> - addi a0, WSIZE * 4
> - subu t3, a0, a2
> + PTR_ADDI a0, WSIZE * 4
> + PTR_SUBU t3, a0, a2
> blez t3, copy_loop
> - addi a1, WSIZE * 4
> + PTR_ADDI a1, WSIZE * 4
>
> copy_loop_exit:
>
> @@ -196,7 +196,7 @@
> .set noreorder
>
> /* set stack pointer; reserve four 32-bit argument slots */
> - la sp, (TEXT_BASE - MALLOC_SIZE - 16)
> + PTR_LA sp, (TEXT_BASE - MALLOC_SIZE - 16)
>
> .set pop
> .endm
> diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
> index d75a652e4d..b9d18fc394 100644
> --- a/arch/mips/lib/genex.S
> +++ b/arch/mips/lib/genex.S
> @@ -14,7 +14,7 @@
> /* Exception vector */
> NESTED(handle_reserved, 0, sp)
> SAVE_ALL
> - la k0, barebox_exc_handler
> + PTR_LA k0, barebox_exc_handler
> jal k0
> move a0, sp
> /* will never return here */
> @@ -24,10 +24,10 @@ NESTED(handle_reserved, 0, sp)
> NESTED(except_vec3_generic, 0, sp)
> .set noat
> mfc0 k1, CP0_CAUSE
> - la k0, exception_handlers
> + PTR_LA k0, exception_handlers
> andi k1, k1, 0x7c
> - addu k0, k0, k1
> - lw k0, (k0)
> + PTR_ADDU k0, k0, k1
> + PTR_L k0, (k0)
> nop
> jr k0
> nop
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (6 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:35 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode Denis Orlov
` (10 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Use CKSEG1ADDR for it to be properly converted to the 64-bit
sign-extended address when building with CONFIG_64BIT set.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/mach-malta/include/mach/mach-gt64120.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h b/arch/mips/mach-malta/include/mach/mach-gt64120.h
index e7d230655c..20ac4d94d6 100644
--- a/arch/mips/mach-malta/include/mach/mach-gt64120.h
+++ b/arch/mips/mach-malta/include/mach/mach-gt64120.h
@@ -12,6 +12,6 @@
#define MIPS_GT_BASE 0x1be00000
-#define GT64120_BASE 0xbbe00000
+#define GT64120_BASE CKSEG1ADDR(MIPS_GT_BASE)
#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT
2023-06-05 20:10 ` [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT Denis Orlov
@ 2023-06-06 8:35 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:35 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> Use CKSEG1ADDR for it to be properly converted to the 64-bit
> sign-extended address when building with CONFIG_64BIT set.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewd-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/mach-malta/include/mach/mach-gt64120.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h b/arch/mips/mach-malta/include/mach/mach-gt64120.h
> index e7d230655c..20ac4d94d6 100644
> --- a/arch/mips/mach-malta/include/mach/mach-gt64120.h
> +++ b/arch/mips/mach-malta/include/mach/mach-gt64120.h
> @@ -12,6 +12,6 @@
>
> #define MIPS_GT_BASE 0x1be00000
>
> -#define GT64120_BASE 0xbbe00000
> +#define GT64120_BASE CKSEG1ADDR(MIPS_GT_BASE)
>
> #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (7 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:36 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 10/17] MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT Denis Orlov
` (9 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Do not (accidentally?) truncate addresses when setting them in the
handler array.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/main_entry.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 2c18bc81c3..d061a0e987 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -22,7 +22,7 @@ unsigned long exception_handlers[32];
static void set_except_vector(int n, void *addr)
{
- unsigned handler = (unsigned long) addr;
+ unsigned long handler = (unsigned long) addr;
exception_handlers[n] = handler;
}
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode
2023-06-05 20:10 ` [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode Denis Orlov
@ 2023-06-06 8:36 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:36 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> Do not (accidentally?) truncate addresses when setting them in the
> handler array.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/boot/main_entry.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
> index 2c18bc81c3..d061a0e987 100644
> --- a/arch/mips/boot/main_entry.c
> +++ b/arch/mips/boot/main_entry.c
> @@ -22,7 +22,7 @@ unsigned long exception_handlers[32];
>
> static void set_except_vector(int n, void *addr)
> {
> - unsigned handler = (unsigned long) addr;
> + unsigned long handler = (unsigned long) addr;
>
> exception_handlers[n] = handler;
Nitpick: This could be combined into one line, but you need not resend
just for this change.
> }
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 10/17] MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (8 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value " Denis Orlov
` (8 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Fixes "warning: cast from pointer to integer of different size"
messages.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/include/asm/dma.h | 16 +++++++++-------
arch/mips/include/asm/io.h | 2 +-
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index 62d9c7c548..d7570cce71 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -25,18 +25,20 @@ static inline void *dma_alloc(size_t size)
#define dma_alloc_coherent dma_alloc_coherent
static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
{
- void *ret;
+ void *ptr;
+ unsigned long virt;
- ret = xmemalign(PAGE_SIZE, size);
+ ptr = xmemalign(PAGE_SIZE, size);
+ memset(ptr, 0, size);
- memset(ret, 0, size);
+ virt = (unsigned long)ptr;
if (dma_handle)
- *dma_handle = CPHYSADDR(ret);
+ *dma_handle = CPHYSADDR(virt);
- dma_flush_range((unsigned long)ret, (unsigned long)(ret + size));
+ dma_flush_range(virt, virt + size);
- return (void *)CKSEG1ADDR(ret);
+ return (void *)CKSEG1ADDR(virt);
}
#define dma_free_coherent dma_free_coherent
@@ -44,7 +46,7 @@ static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle,
size_t size)
{
if (IS_ENABLED(CONFIG_MMU) && vaddr)
- free((void *)CKSEG0ADDR(vaddr));
+ free((void *)CKSEG0ADDR((unsigned long)vaddr));
else
free(vaddr);
}
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index a3acbd7017..9c856c7b15 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -30,7 +30,7 @@ void dma_inv_range(unsigned long, unsigned long);
#define virt_to_phys virt_to_phys
static inline unsigned long virt_to_phys(const void *address)
{
- return (unsigned long)CPHYSADDR(address);
+ return CPHYSADDR((unsigned long)address);
}
/*
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (9 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 10/17] MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 9:04 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing " Denis Orlov
` (7 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
The code that uses TEXT_BASE will fail on reading truncated 32-bit
address if running with 64BIT enabled. As we only support running from
compatibility segments (i.e. no 'proper' 64-bit base addresses), simply
make sure the value is sign-extended when passing it as a define.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/Makefile | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index bad6e574c4..65a00379ab 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_GS232) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap
-KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
+ifdef CONFIG_64BIT
+MIPS_TEXT_BASE = $(subst 0x,0xffffffff,$(CONFIG_TEXT_BASE))
+else
+MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE)
+endif
+
+KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE)
ifndef CONFIG_MODULES
# Add cleanup flags
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
2023-06-05 20:10 ` [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value " Denis Orlov
@ 2023-06-06 9:04 ` Ahmad Fatoum
2023-06-06 9:23 ` Denis Orlov
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 9:04 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> The code that uses TEXT_BASE will fail on reading truncated 32-bit
> address if running with 64BIT enabled. As we only support running from
> compatibility segments (i.e. no 'proper' 64-bit base addresses), simply
> make sure the value is sign-extended when passing it as a define.
Below is not really a sign extension. e.g. 0x0000_0000 would be turned
into 0xffff_ffff_0000_0000. Is that ok?
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
> ---
> arch/mips/Makefile | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index bad6e574c4..65a00379ab 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS
> cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap
> cflags-$(CONFIG_CPU_GS232) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap
>
> -KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
> +ifdef CONFIG_64BIT
> +MIPS_TEXT_BASE = $(subst 0x,0xffffffff,$(CONFIG_TEXT_BASE))
> +else
> +MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE)
> +endif
> +
> +KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE)
>
> ifndef CONFIG_MODULES
> # Add cleanup flags
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
2023-06-06 9:04 ` Ahmad Fatoum
@ 2023-06-06 9:23 ` Denis Orlov
2023-06-09 6:40 ` Ahmad Fatoum
0 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-06 9:23 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, 6 Jun 2023 at 12:04, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> On 05.06.23 22:10, Denis Orlov wrote:
> > The code that uses TEXT_BASE will fail on reading truncated 32-bit
> > address if running with 64BIT enabled. As we only support running from
> > compatibility segments (i.e. no 'proper' 64-bit base addresses), simply
> > make sure the value is sign-extended when passing it as a define.
>
> Below is not really a sign extension. e.g. 0x0000_0000 would be turned
> into 0xffff_ffff_0000_0000. Is that ok?
Yeah, we can only handle KSEG0/KSEG1 segments, i.e. text base should be
somewhere in 0x8000_0000/0xa000_0000. So for those, this might be
considered a sign extension, I guess.
Regards,
Denis
>
> >
> > Signed-off-by: Denis Orlov <denorl2009@gmail.com>
> > ---
> > arch/mips/Makefile | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> > index bad6e574c4..65a00379ab 100644
> > --- a/arch/mips/Makefile
> > +++ b/arch/mips/Makefile
> > @@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS
> > cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap
> > cflags-$(CONFIG_CPU_GS232) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap
> >
> > -KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
> > +ifdef CONFIG_64BIT
> > +MIPS_TEXT_BASE = $(subst 0x,0xffffffff,$(CONFIG_TEXT_BASE))
> > +else
> > +MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE)
> > +endif
> > +
> > +KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE)
> >
> > ifndef CONFIG_MODULES
> > # Add cleanup flags
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
2023-06-06 9:23 ` Denis Orlov
@ 2023-06-09 6:40 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-09 6:40 UTC (permalink / raw)
To: Denis Orlov; +Cc: barebox
On 06.06.23 11:23, Denis Orlov wrote:
> On Tue, 6 Jun 2023 at 12:04, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>>
>> On 05.06.23 22:10, Denis Orlov wrote:
>>> The code that uses TEXT_BASE will fail on reading truncated 32-bit
>>> address if running with 64BIT enabled. As we only support running from
>>> compatibility segments (i.e. no 'proper' 64-bit base addresses), simply
>>> make sure the value is sign-extended when passing it as a define.
>>
>> Below is not really a sign extension. e.g. 0x0000_0000 would be turned
>> into 0xffff_ffff_0000_0000. Is that ok?
>
> Yeah, we can only handle KSEG0/KSEG1 segments, i.e. text base should be
> somewhere in 0x8000_0000/0xa000_0000. So for those, this might be
> considered a sign extension, I guess.
Hmm, ok.
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> Regards,
> Denis
>
>>
>>>
>>> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
>>> ---
>>> arch/mips/Makefile | 8 +++++++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>>> index bad6e574c4..65a00379ab 100644
>>> --- a/arch/mips/Makefile
>>> +++ b/arch/mips/Makefile
>>> @@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS
>>> cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap
>>> cflags-$(CONFIG_CPU_GS232) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap
>>>
>>> -KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
>>> +ifdef CONFIG_64BIT
>>> +MIPS_TEXT_BASE = $(subst 0x,0xffffffff,$(CONFIG_TEXT_BASE))
>>> +else
>>> +MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE)
>>> +endif
>>> +
>>> +KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE)
>>>
>>> ifndef CONFIG_MODULES
>>> # Add cleanup flags
>>
>> --
>> Pengutronix e.K. | |
>> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
>> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
>> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (10 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value " Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 9:06 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 13/17] MIPS: traps: fix passing wrong sp when returning from exception Denis Orlov
` (6 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This allows using addresses from XKPHYS segment. This is needed as we
access hardware registers through this segment in 64BIT configuration,
but this also lets us peek/poke bigger memory address space using
commands that work with memory on 64BIT.
With this commit, malta with 64-bit CPU finally boots into 64BIT barebox
in QEMU.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/start.S | 2 ++
arch/mips/include/asm/pbl_macros.h | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index 5f134f9ae9..30828ad9ef 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -26,6 +26,8 @@ EXPORT(_start)
mips_disable_interrupts
+ mips64_enable_64bit_addressing
+
copy_to_link_location _start
stack_setup
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 1fba690c8c..ce169a1554 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -152,6 +152,17 @@
.set pop
.endm
+ .macro mips64_enable_64bit_addressing
+#ifdef CONFIG_64BIT
+ .set push
+ .set noreorder
+ mfc0 k0, CP0_STATUS
+ or k0, ST0_KX
+ mtc0 k0, CP0_STATUS
+ .set pop
+#endif
+ .endm
+
.macro mips_barebox_10h
.set push
.set noreorder
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
2023-06-05 20:10 ` [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing " Denis Orlov
@ 2023-06-06 9:06 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 9:06 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> This allows using addresses from XKPHYS segment. This is needed as we
> access hardware registers through this segment in 64BIT configuration,
> but this also lets us peek/poke bigger memory address space using
> commands that work with memory on 64BIT.
>
> With this commit, malta with 64-bit CPU finally boots into 64BIT barebox
> in QEMU.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/boot/start.S | 2 ++
> arch/mips/include/asm/pbl_macros.h | 11 +++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
> index 5f134f9ae9..30828ad9ef 100644
> --- a/arch/mips/boot/start.S
> +++ b/arch/mips/boot/start.S
> @@ -26,6 +26,8 @@ EXPORT(_start)
>
> mips_disable_interrupts
>
> + mips64_enable_64bit_addressing
> +
> copy_to_link_location _start
>
> stack_setup
> diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
> index 1fba690c8c..ce169a1554 100644
> --- a/arch/mips/include/asm/pbl_macros.h
> +++ b/arch/mips/include/asm/pbl_macros.h
> @@ -152,6 +152,17 @@
> .set pop
> .endm
>
> + .macro mips64_enable_64bit_addressing
> +#ifdef CONFIG_64BIT
> + .set push
> + .set noreorder
> + mfc0 k0, CP0_STATUS
> + or k0, ST0_KX
> + mtc0 k0, CP0_STATUS
> + .set pop
> +#endif
> + .endm
> +
> .macro mips_barebox_10h
> .set push
> .set noreorder
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 13/17] MIPS: traps: fix passing wrong sp when returning from exception
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (11 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing " Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location Denis Orlov
` (5 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This code seems to have been working on 32-bit builds by accident.
However it totally broke on 64 bits, resulting in "restoring" some
garbage into registers.
The reason the code worked on 32 bits is this. When we are entering the
barebox_exc_handler() function, we are passing in a register the current
stack pointer as an argument (which corresponds to the regs parameter).
On o32 ABI the space for arguments passed in registers is reserved on
the stack by the caller. So, when we are taking the address of regs in
the body of the function, we have to put this argument on the stack,
into the first reserved slot. However, this slot is located exactly at
the current 'sp' and thus the address of regs happens to be the same as
its value!
On n64 ABI, however, the arguments passed in registers are saved onto
the stack on the callee side, so we end up with the wrong value being
used as the stack pointer.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/lib/traps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index ff0a54af8e..45694fe7ef 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -173,7 +173,7 @@ void barebox_exc_handler(struct pt_regs *regs)
"move\t$29, %0\n\t"
"j\tret_from_exception"
:/* no outputs */
- :"r" (®s));
+ :"r" (regs));
/* Unreached */
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (12 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 13/17] MIPS: traps: fix passing wrong sp when returning from exception Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 9:07 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 15/17] MIPS: add 64-bit support for optimized string functions Denis Orlov
` (4 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This may speed up this code a little on MIPS64, however this also allows
us to get rid of unnecessary macro definition there, simplifying the
code a tiny bit.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/include/asm/pbl_macros.h | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index ce169a1554..f8629d3f2c 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -120,22 +120,21 @@
PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */
PTR_ADDU a2, a0, t2 /* a2 <- source end address */
-#define WSIZE 4
copy_loop:
/* copy from source address [a0] */
- lw ta0, WSIZE * 0(a0)
- lw ta1, WSIZE * 1(a0)
- lw ta2, WSIZE * 2(a0)
- lw ta3, WSIZE * 3(a0)
+ LONG_L ta0, LONGSIZE * 0(a0)
+ LONG_L ta1, LONGSIZE * 1(a0)
+ LONG_L ta2, LONGSIZE * 2(a0)
+ LONG_L ta3, LONGSIZE * 3(a0)
/* copy to target address [a1] */
- sw ta0, WSIZE * 0(a1)
- sw ta1, WSIZE * 1(a1)
- sw ta2, WSIZE * 2(a1)
- sw ta3, WSIZE * 3(a1)
- PTR_ADDI a0, WSIZE * 4
+ LONG_S ta0, LONGSIZE * 0(a1)
+ LONG_S ta1, LONGSIZE * 1(a1)
+ LONG_S ta2, LONGSIZE * 2(a1)
+ LONG_S ta3, LONGSIZE * 3(a1)
+ PTR_ADDI a0, LONGSIZE * 4
PTR_SUBU t3, a0, a2
blez t3, copy_loop
- PTR_ADDI a1, WSIZE * 4
+ PTR_ADDI a1, LONGSIZE * 4
copy_loop_exit:
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location
2023-06-05 20:10 ` [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location Denis Orlov
@ 2023-06-06 9:07 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 9:07 UTC (permalink / raw)
To: Denis Orlov, barebox
On 05.06.23 22:10, Denis Orlov wrote:
> This may speed up this code a little on MIPS64, however this also allows
> us to get rid of unnecessary macro definition there, simplifying the
> code a tiny bit.
>
> Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> arch/mips/include/asm/pbl_macros.h | 21 ++++++++++-----------
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
> index ce169a1554..f8629d3f2c 100644
> --- a/arch/mips/include/asm/pbl_macros.h
> +++ b/arch/mips/include/asm/pbl_macros.h
> @@ -120,22 +120,21 @@
> PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */
> PTR_ADDU a2, a0, t2 /* a2 <- source end address */
>
> -#define WSIZE 4
> copy_loop:
> /* copy from source address [a0] */
> - lw ta0, WSIZE * 0(a0)
> - lw ta1, WSIZE * 1(a0)
> - lw ta2, WSIZE * 2(a0)
> - lw ta3, WSIZE * 3(a0)
> + LONG_L ta0, LONGSIZE * 0(a0)
> + LONG_L ta1, LONGSIZE * 1(a0)
> + LONG_L ta2, LONGSIZE * 2(a0)
> + LONG_L ta3, LONGSIZE * 3(a0)
> /* copy to target address [a1] */
> - sw ta0, WSIZE * 0(a1)
> - sw ta1, WSIZE * 1(a1)
> - sw ta2, WSIZE * 2(a1)
> - sw ta3, WSIZE * 3(a1)
> - PTR_ADDI a0, WSIZE * 4
> + LONG_S ta0, LONGSIZE * 0(a1)
> + LONG_S ta1, LONGSIZE * 1(a1)
> + LONG_S ta2, LONGSIZE * 2(a1)
> + LONG_S ta3, LONGSIZE * 3(a1)
> + PTR_ADDI a0, LONGSIZE * 4
> PTR_SUBU t3, a0, a2
> blez t3, copy_loop
> - PTR_ADDI a1, WSIZE * 4
> + PTR_ADDI a1, LONGSIZE * 4
>
> copy_loop_exit:
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 15/17] MIPS: add 64-bit support for optimized string functions
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (13 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 16/17] MIPS: make setjmp/longjmp/initjmp available in 64BIT builds Denis Orlov
` (3 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
This adds macro definitions and a bit of code that allow to properly
utilise doubleword instructions on mips64. These changes are taken
directly from Linux sources. Also switch some o32-specific register
definitions to generic ones for this code to actually compile for n64
ABI.
While at it, this also removes an unused macro define.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/Kconfig | 1 -
arch/mips/lib/memcpy.S | 37 ++++++++++++++++++++++++++++++++-----
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ab8c8cf176..de2f539cc1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -376,7 +376,6 @@ config NMON_HELP
config MIPS_OPTIMIZED_STRING_FUNCTIONS
bool "use assembler optimized string functions"
- depends on !64BIT
default y
help
Say yes here to use assembler optimized memcpy / memset functions.
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index cee0319dcf..5c01dbdcd3 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -20,7 +20,26 @@
#define src a1
#define len a2
-#define LOADK lw /* No exception */
+#ifdef CONFIG_64BIT
+
+#define LOAD(reg, addr) ld reg, addr
+#define LOADL(reg, addr) ldl reg, addr
+#define LOADR(reg, addr) ldr reg, addr
+#define STOREL(reg, addr) sdl reg, addr
+#define STORER(reg, addr) sdr reg, addr
+#define STORE(reg, addr) sd reg, addr
+#define ADD daddu
+#define SUB dsubu
+#define SRL dsrl
+#define SRA dsra
+#define SLL dsll
+#define SLLV dsllv
+#define SRLV dsrlv
+#define NBYTES 8
+#define LOG_NBYTES 3
+
+#else
+
#define LOAD(reg, addr) lw reg, addr
#define LOADL(reg, addr) lwl reg, addr
#define LOADR(reg, addr) lwr reg, addr
@@ -37,6 +56,8 @@
#define NBYTES 4
#define LOG_NBYTES 2
+#endif /* CONFIG_64BIT */
+
#define LOADB(reg, addr) lb reg, addr
#define STOREB(reg, addr) sb reg, addr
@@ -101,8 +122,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
LOAD(t2, UNIT(2)(src))
LOAD(t3, UNIT(3)(src))
SUB len, len, 8*NBYTES
- LOAD(t4, UNIT(4)(src))
- LOAD(t7, UNIT(5)(src))
+ LOAD(ta0, UNIT(4)(src))
+ LOAD(ta3, UNIT(5)(src))
STORE(t0, UNIT(0)(dst))
STORE(t1, UNIT(1)(dst))
LOAD(t0, UNIT(6)(src))
@@ -111,8 +132,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
ADD dst, dst, 8*NBYTES
STORE(t2, UNIT(-6)(dst))
STORE(t3, UNIT(-5)(dst))
- STORE(t4, UNIT(-4)(dst))
- STORE(t7, UNIT(-3)(dst))
+ STORE(ta0, UNIT(-4)(dst))
+ STORE(ta3, UNIT(-3)(dst))
STORE(t0, UNIT(-2)(dst))
STORE(t1, UNIT(-1)(dst))
bne len, rem, 1b
@@ -263,6 +284,12 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
COPY_BYTE(0)
COPY_BYTE(1)
+#ifdef CONFIG_64BIT
+ COPY_BYTE(2)
+ COPY_BYTE(3)
+ COPY_BYTE(4)
+ COPY_BYTE(5)
+#endif
LOADB(t0, NBYTES-2(src))
SUB len, len, 1
jr ra
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 16/17] MIPS: make setjmp/longjmp/initjmp available in 64BIT builds
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (14 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 15/17] MIPS: add 64-bit support for optimized string functions Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 17/17] MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT Denis Orlov
` (2 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Make the code compatible with 64-bit configurations by storing saved
register values with unsigned long type and using generic macros in
assembly code.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/Kconfig | 2 +-
arch/mips/include/asm/setjmp.h | 2 +-
arch/mips/lib/setjmp.S | 48 +++++++++++++++++-----------------
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index de2f539cc1..e05ee2d7f1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,7 @@ config MIPS
select HAVE_PBL_MULTI_IMAGES
select HAS_DMA
select ARCH_HAS_DATA_ABORT_MASK
+ select ARCH_HAS_SJLJ
select ELF
default y
@@ -305,7 +306,6 @@ choice
config 32BIT
bool "32-bit barebox"
depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
- select ARCH_HAS_SJLJ
help
Select this option if you want to build a 32-bit barebox.
diff --git a/arch/mips/include/asm/setjmp.h b/arch/mips/include/asm/setjmp.h
index 81f4d4c15f..39e01e27df 100644
--- a/arch/mips/include/asm/setjmp.h
+++ b/arch/mips/include/asm/setjmp.h
@@ -19,7 +19,7 @@ typedef struct __jmp_buf_internal_tag {
void *__sp;
/* Callee-saved registers s0 through s7. */
- int __regs[8];
+ unsigned long __regs[8];
/* The frame pointer. */
void *__fp;
diff --git a/arch/mips/lib/setjmp.S b/arch/mips/lib/setjmp.S
index b09a7c5529..42a2ec15a9 100644
--- a/arch/mips/lib/setjmp.S
+++ b/arch/mips/lib/setjmp.S
@@ -6,34 +6,34 @@
/* int setjmp (jmp_buf); */
LEAF(setjmp)
- sw ra, (0 * 4)(a0)
- sw sp, (1 * 4)(a0)
- sw s0, (2 * 4)(a0)
- sw s1, (3 * 4)(a0)
- sw s2, (4 * 4)(a0)
- sw s3, (5 * 4)(a0)
- sw s4, (6 * 4)(a0)
- sw s5, (7 * 4)(a0)
- sw s6, (8 * 4)(a0)
- sw s7, (9 * 4)(a0)
- sw fp, (10 * 4)(a0)
+ REG_S ra, (0 * SZREG)(a0)
+ REG_S sp, (1 * SZREG)(a0)
+ REG_S s0, (2 * SZREG)(a0)
+ REG_S s1, (3 * SZREG)(a0)
+ REG_S s2, (4 * SZREG)(a0)
+ REG_S s3, (5 * SZREG)(a0)
+ REG_S s4, (6 * SZREG)(a0)
+ REG_S s5, (7 * SZREG)(a0)
+ REG_S s6, (8 * SZREG)(a0)
+ REG_S s7, (9 * SZREG)(a0)
+ REG_S fp, (10 * SZREG)(a0)
move v0, zero
j ra
END(setjmp)
/* volatile void longjmp (jmp_buf, int); */
LEAF(longjmp)
- lw ra, (0 * 4)(a0)
- lw sp, (1 * 4)(a0)
- lw s0, (2 * 4)(a0)
- lw s1, (3 * 4)(a0)
- lw s2, (4 * 4)(a0)
- lw s3, (5 * 4)(a0)
- lw s4, (6 * 4)(a0)
- lw s5, (7 * 4)(a0)
- lw s6, (8 * 4)(a0)
- lw s7, (9 * 4)(a0)
- lw fp, (10 * 4)(a0)
+ REG_L ra, (0 * SZREG)(a0)
+ REG_L sp, (1 * SZREG)(a0)
+ REG_L s0, (2 * SZREG)(a0)
+ REG_L s1, (3 * SZREG)(a0)
+ REG_L s2, (4 * SZREG)(a0)
+ REG_L s3, (5 * SZREG)(a0)
+ REG_L s4, (6 * SZREG)(a0)
+ REG_L s5, (7 * SZREG)(a0)
+ REG_L s6, (8 * SZREG)(a0)
+ REG_L s7, (9 * SZREG)(a0)
+ REG_L fp, (10 * SZREG)(a0)
bne a1, zero, 1f
li a1, 1
1:
@@ -43,8 +43,8 @@ END(longjmp)
/* int initjmp(jmp_buf jmp, void __noreturn (*func)(void), void *stack_top); */
LEAF(initjmp)
- sw a1, (0 * 4)(a0)
- sw a2, (1 * 4)(a0)
+ REG_S a1, (0 * SZREG)(a0)
+ REG_S a2, (1 * SZREG)(a0)
move v0, zero
j ra
END(initjmp)
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 17/17] MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (15 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 16/17] MIPS: make setjmp/longjmp/initjmp available in 64BIT builds Denis Orlov
@ 2023-06-05 20:10 ` Denis Orlov
2023-06-06 8:02 ` [PATCH 00/17] MIPS: fix and improve 64BIT support Ahmad Fatoum
2023-06-09 6:43 ` Sascha Hauer
18 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-05 20:10 UTC (permalink / raw)
To: barebox; +Cc: Denis Orlov
Fix "cast from pointer to integer of different size" warnings by casting
pointers into unsigned long values when calculating sizes. While at it,
simplify code a bit, removing unnecessary variables and instead giving
another variable a more comprehensible name.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/main_entry-pbl.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
index 02ddd5ec24..f75ec03851 100644
--- a/arch/mips/boot/main_entry-pbl.c
+++ b/arch/mips/boot/main_entry-pbl.c
@@ -36,7 +36,7 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
void __section(.text_entry) pbl_main_entry(void *fdt, void *fdt_end,
u32 ram_size)
{
- u32 pg_start, pg_end, pg_len, fdt_len;
+ u32 piggy_len, fdt_len;
void *fdt_new;
void (*barebox)(void *fdt, u32 fdt_len, u32 ram_size);
@@ -45,13 +45,10 @@ void __section(.text_entry) pbl_main_entry(void *fdt, void *fdt_end,
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);
- pg_start = (u32)&input_data;
- pg_end = (u32)&input_data_end;
- pg_len = pg_end - pg_start;
+ piggy_len = (unsigned long)&input_data_end - (unsigned long)&input_data;
+ barebox_uncompress(&input_data, piggy_len);
- barebox_uncompress(&input_data, pg_len);
-
- fdt_len = (u32)fdt_end - (u32)fdt;
+ fdt_len = (unsigned long)fdt_end - (unsigned long)fdt;
fdt_new = (void *)PAGE_ALIGN_DOWN(TEXT_BASE - MALLOC_SIZE - STACK_SIZE - fdt_len);
memcpy(fdt_new, fdt, fdt_len);
--
2.41.0
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 00/17] MIPS: fix and improve 64BIT support
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (16 preceding siblings ...)
2023-06-05 20:10 ` [PATCH 17/17] MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT Denis Orlov
@ 2023-06-06 8:02 ` Ahmad Fatoum
2023-06-06 8:43 ` Denis Orlov
2023-06-09 6:43 ` Sascha Hauer
18 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2023-06-06 8:02 UTC (permalink / raw)
To: Denis Orlov, barebox
Hello Denis,
On 05.06.23 22:10, Denis Orlov wrote:
> The existing 64BIT support for MIPS was somewhat incomplete with no
> board having MIPS64 CPUs specified to be available as targets. Define
> Malta as supporting those and fix all the compilation and linking
> errors. Make some optional features available with 64BIT too.
Would be cool to test this in CI. Could you add:
- a defconfig that enables this board (I'd call it mips64_defconfig
and if another MIPS64 SoC is added, we will add it there, like
we do now for e.g. multi_v8_defconfig on ARM)
- a Labgrid env file that configures QEMU appropriately
See test/mips/qemu-malta_defconfig.yaml for an example
If you like, you can go further and send a patch adding it to
CI's test-labgrid-pytest.yml workflow, but I can do that too.
Cheers,
Ahmad
>
> Denis Orlov (17):
> MIPS: malta: allow to choose MIPS64 target CPU in config
> MIPS: malta: use CKSEG instead of KSEG macros
> MIPS: reloc: fix relocation with CONFIG_64BIT enabled
> MIPS: o32: provide ta0..ta3 register definitions
> MIPS: pbl: use o32/n64 compatible register definitions
> MIPS: pbl: fix linking errors with CONFIG_64BIT
> MIPS: use MIPS32/MIPS64 generic instruction macros
> MIPS: malta: fix GT64120 base virtual address on 64BIT
> MIPS: fix addresses of exception vectors in 64-bit mode
> MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT
> MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
> MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
> MIPS: traps: fix passing wrong sp when returning from exception
> MIPS: pbl_macros: use generic load/store macros in
> copy_to_link_location
> MIPS: add 64-bit support for optimized string functions
> MIPS: make setjmp/longjmp/initjmp available in 64BIT builds
> MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT
>
> arch/mips/Kconfig | 6 +-
> arch/mips/Makefile | 14 +++--
> arch/mips/boards/qemu-malta/lowlevel.S | 4 +-
> arch/mips/boot/main_entry-pbl.c | 11 ++--
> arch/mips/boot/main_entry.c | 2 +-
> arch/mips/boot/start.S | 4 +-
> arch/mips/include/asm/asm.h | 10 +--
> arch/mips/include/asm/debug_ll_ns16550.h | 6 +-
> arch/mips/include/asm/dma.h | 16 ++---
> arch/mips/include/asm/io.h | 2 +-
> arch/mips/include/asm/pbl_macros.h | 62 +++++++++++--------
> arch/mips/include/asm/pbl_nmon.h | 10 +--
> arch/mips/include/asm/regdef.h | 6 ++
> arch/mips/include/asm/setjmp.h | 2 +-
> arch/mips/lib/genex.S | 8 +--
> arch/mips/lib/memcpy.S | 37 +++++++++--
> arch/mips/lib/reloc.c | 7 +--
> arch/mips/lib/setjmp.S | 48 +++++++-------
> arch/mips/lib/traps.c | 2 +-
> .../mach-malta/include/mach/mach-gt64120.h | 2 +-
> arch/mips/mach-malta/pci.c | 2 +-
> 21 files changed, 156 insertions(+), 105 deletions(-)
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 00/17] MIPS: fix and improve 64BIT support
2023-06-06 8:02 ` [PATCH 00/17] MIPS: fix and improve 64BIT support Ahmad Fatoum
@ 2023-06-06 8:43 ` Denis Orlov
0 siblings, 0 replies; 36+ messages in thread
From: Denis Orlov @ 2023-06-06 8:43 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hello Ahmad,
On Tue, 6 Jun 2023 at 11:02, Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> Hello Denis,
>
> On 05.06.23 22:10, Denis Orlov wrote:
> > The existing 64BIT support for MIPS was somewhat incomplete with no
> > board having MIPS64 CPUs specified to be available as targets. Define
> > Malta as supporting those and fix all the compilation and linking
> > errors. Make some optional features available with 64BIT too.
>
> Would be cool to test this in CI. Could you add:
>
> - a defconfig that enables this board (I'd call it mips64_defconfig
> and if another MIPS64 SoC is added, we will add it there, like
> we do now for e.g. multi_v8_defconfig on ARM)
>
> - a Labgrid env file that configures QEMU appropriately
> See test/mips/qemu-malta_defconfig.yaml for an example
Good idea, will do that and send another patch a bit later.
>
> If you like, you can go further and send a patch adding it to
> CI's test-labgrid-pytest.yml workflow, but I can do that too.
Yeah, that sounds interesting, will also try to do that.
Regards,
Denis
>
> Cheers,
> Ahmad
>
> >
> > Denis Orlov (17):
> > MIPS: malta: allow to choose MIPS64 target CPU in config
> > MIPS: malta: use CKSEG instead of KSEG macros
> > MIPS: reloc: fix relocation with CONFIG_64BIT enabled
> > MIPS: o32: provide ta0..ta3 register definitions
> > MIPS: pbl: use o32/n64 compatible register definitions
> > MIPS: pbl: fix linking errors with CONFIG_64BIT
> > MIPS: use MIPS32/MIPS64 generic instruction macros
> > MIPS: malta: fix GT64120 base virtual address on 64BIT
> > MIPS: fix addresses of exception vectors in 64-bit mode
> > MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT
> > MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
> > MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
> > MIPS: traps: fix passing wrong sp when returning from exception
> > MIPS: pbl_macros: use generic load/store macros in
> > copy_to_link_location
> > MIPS: add 64-bit support for optimized string functions
> > MIPS: make setjmp/longjmp/initjmp available in 64BIT builds
> > MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT
> >
> > arch/mips/Kconfig | 6 +-
> > arch/mips/Makefile | 14 +++--
> > arch/mips/boards/qemu-malta/lowlevel.S | 4 +-
> > arch/mips/boot/main_entry-pbl.c | 11 ++--
> > arch/mips/boot/main_entry.c | 2 +-
> > arch/mips/boot/start.S | 4 +-
> > arch/mips/include/asm/asm.h | 10 +--
> > arch/mips/include/asm/debug_ll_ns16550.h | 6 +-
> > arch/mips/include/asm/dma.h | 16 ++---
> > arch/mips/include/asm/io.h | 2 +-
> > arch/mips/include/asm/pbl_macros.h | 62 +++++++++++--------
> > arch/mips/include/asm/pbl_nmon.h | 10 +--
> > arch/mips/include/asm/regdef.h | 6 ++
> > arch/mips/include/asm/setjmp.h | 2 +-
> > arch/mips/lib/genex.S | 8 +--
> > arch/mips/lib/memcpy.S | 37 +++++++++--
> > arch/mips/lib/reloc.c | 7 +--
> > arch/mips/lib/setjmp.S | 48 +++++++-------
> > arch/mips/lib/traps.c | 2 +-
> > .../mach-malta/include/mach/mach-gt64120.h | 2 +-
> > arch/mips/mach-malta/pci.c | 2 +-
> > 21 files changed, 156 insertions(+), 105 deletions(-)
> >
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 00/17] MIPS: fix and improve 64BIT support
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
` (17 preceding siblings ...)
2023-06-06 8:02 ` [PATCH 00/17] MIPS: fix and improve 64BIT support Ahmad Fatoum
@ 2023-06-09 6:43 ` Sascha Hauer
18 siblings, 0 replies; 36+ messages in thread
From: Sascha Hauer @ 2023-06-09 6:43 UTC (permalink / raw)
To: Denis Orlov; +Cc: barebox
On Mon, Jun 05, 2023 at 11:10:31PM +0300, Denis Orlov wrote:
> The existing 64BIT support for MIPS was somewhat incomplete with no
> board having MIPS64 CPUs specified to be available as targets. Define
> Malta as supporting those and fix all the compilation and linking
> errors. Make some optional features available with 64BIT too.
>
> Denis Orlov (17):
> MIPS: malta: allow to choose MIPS64 target CPU in config
> MIPS: malta: use CKSEG instead of KSEG macros
> MIPS: reloc: fix relocation with CONFIG_64BIT enabled
> MIPS: o32: provide ta0..ta3 register definitions
> MIPS: pbl: use o32/n64 compatible register definitions
> MIPS: pbl: fix linking errors with CONFIG_64BIT
> MIPS: use MIPS32/MIPS64 generic instruction macros
> MIPS: malta: fix GT64120 base virtual address on 64BIT
> MIPS: fix addresses of exception vectors in 64-bit mode
> MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT
> MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
> MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
> MIPS: traps: fix passing wrong sp when returning from exception
> MIPS: pbl_macros: use generic load/store macros in
> copy_to_link_location
> MIPS: add 64-bit support for optimized string functions
> MIPS: make setjmp/longjmp/initjmp available in 64BIT builds
> MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT
Applied, thanks
Sascha
>
> arch/mips/Kconfig | 6 +-
> arch/mips/Makefile | 14 +++--
> arch/mips/boards/qemu-malta/lowlevel.S | 4 +-
> arch/mips/boot/main_entry-pbl.c | 11 ++--
> arch/mips/boot/main_entry.c | 2 +-
> arch/mips/boot/start.S | 4 +-
> arch/mips/include/asm/asm.h | 10 +--
> arch/mips/include/asm/debug_ll_ns16550.h | 6 +-
> arch/mips/include/asm/dma.h | 16 ++---
> arch/mips/include/asm/io.h | 2 +-
> arch/mips/include/asm/pbl_macros.h | 62 +++++++++++--------
> arch/mips/include/asm/pbl_nmon.h | 10 +--
> arch/mips/include/asm/regdef.h | 6 ++
> arch/mips/include/asm/setjmp.h | 2 +-
> arch/mips/lib/genex.S | 8 +--
> arch/mips/lib/memcpy.S | 37 +++++++++--
> arch/mips/lib/reloc.c | 7 +--
> arch/mips/lib/setjmp.S | 48 +++++++-------
> arch/mips/lib/traps.c | 2 +-
> .../mach-malta/include/mach/mach-gt64120.h | 2 +-
> arch/mips/mach-malta/pci.c | 2 +-
> 21 files changed, 156 insertions(+), 105 deletions(-)
>
> --
> 2.41.0
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread