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From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 12/17] arm: move __mmu_cache_flush to bare_init section
Date: Thu, 29 Apr 2010 09:52:10 +0200	[thread overview]
Message-ID: <1272527535-17527-13-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1272527535-17527-1-git-send-email-s.hauer@pengutronix.de>

Instead of having seperate cache flush functions in the startup code
we want to call the generic functions. To accomplish this they have
to be in the bare_init section.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/cache-armv4.S |    2 ++
 arch/arm/cpu/cache-armv5.S |    2 ++
 arch/arm/cpu/cache-armv6.S |    3 +++
 arch/arm/cpu/cache-armv7.S |    2 ++
 4 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index a79cc27..3cec4dd 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
 		mov	pc, lr
 ENDPROC(__mmu_cache_off)
 
+.section ".text_bare_init.text"
 ENTRY(__mmu_cache_flush)
 		mrc	p15, 0, r6, c0, c0	@ get processor ID
 		mov	r2, #64*1024		@ default: 32K dcache size (*2)
@@ -73,6 +74,7 @@ no_cache_id:
 		mov	pc, lr
 ENDPROC(__mmu_cache_flush)
 
+.section ".text.text"
 /*
  *	dma_inv_range(start, end)
  *
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index f52bcb7..9fb320f 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
 		mov	pc, lr
 ENDPROC(__mmu_cache_off)
 
+.section ".text_bare_init.text"
 ENTRY(__mmu_cache_flush)
 1:		mrc	p15, 0, r15, c7, c14, 3	@ test,clean,invalidate D cache
 		bne	1b
@@ -48,6 +49,7 @@ ENTRY(__mmu_cache_flush)
 		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
 		mov	pc, lr
 ENDPROC(__mmu_cache_flush)
+.section ".text.text"
 
 /*
  *	dma_inv_range(start, end)
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index e3498bb..25476d5 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -31,6 +31,7 @@ __common_mmu_cache_on:
 		mrc	p15, 0, r0, c1, c0, 0	@ and read it back to
 		sub	pc, lr, r0, lsr #32	@ properly flush pipeline
 
+
 ENTRY(__mmu_cache_off)
 #ifdef CONFIG_MMU
 		mrc	p15, 0, r0, c1, c0
@@ -42,6 +43,7 @@ ENTRY(__mmu_cache_off)
 #endif
 		mov	pc, lr
 
+.section ".text_bare_init.text"
 ENTRY(__mmu_cache_flush)
 		mov	r1, #0
 		mcr	p15, 0, r1, c7, c14, 0	@ clean+invalidate D
@@ -50,6 +52,7 @@ ENTRY(__mmu_cache_flush)
 		mcr	p15, 0, r1, c7, c10, 4	@ drain WB
 		mov	pc, lr
 ENDPROC(__mmu_cache_flush)
+.section ".text.text"
 
 /*
  *	v6_dma_inv_range(start,end)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 9afa20d..a303dc1 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -49,6 +49,7 @@ ENTRY(__mmu_cache_off)
 		mov	pc, r12
 ENDPROC(__mmu_cache_on)
 
+.section ".text_bare_init.text"
 ENTRY(__mmu_cache_flush)
 		mrc	p15, 0, r10, c0, c1, 5	@ read ID_MMFR1
 		tst	r10, #0xf << 16		@ hierarchical cache (ARMv7)
@@ -105,6 +106,7 @@ iflush:
 		mcr	p15, 0, r10, c7, c5, 4	@ ISB
 		mov	pc, lr
 ENDPROC(__mmu_cache_flush)
+.section ".text.text"
 
 /*
  * cache_line_size - get the cache line size from the CSIDR register
-- 
1.7.0


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  parent reply	other threads:[~2010-04-29  7:52 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-29  7:51 patches for next v2 Sascha Hauer
2010-04-29  7:51 ` [PATCH 01/17] i.MX35 stack: Fix mc9sdz60 reset register offset Sascha Hauer
2010-04-29  7:52 ` [PATCH 02/17] ARM: use memalign in dma_alloc_coherent to assure alignment Sascha Hauer
2010-04-29  7:52 ` [PATCH 03/17] fsl_udc: make it work with MMU on Sascha Hauer
2010-04-29  7:52 ` [PATCH 04/17] Increase MAX_FILES to 128 Sascha Hauer
2010-04-29  7:52 ` [PATCH 05/17] fix _update scripts Sascha Hauer
2010-04-29  7:52 ` [PATCH 06/17] define __LINUX_ARM_ARCH__ for armv6 processors Sascha Hauer
2010-04-29  7:52 ` [PATCH 07/17] ARM: Add get_cr/set_cr functions Sascha Hauer
2010-04-29  7:52 ` [PATCH 08/17] ARM: update icache functions to use get_cr/set_cr Sascha Hauer
2010-04-29  7:52 ` [PATCH 09/17] pcm043: Speed up NAND controller before copying barebox image Sascha Hauer
2010-05-03 11:29   ` Peter Korsgaard
2010-05-03 13:09     ` Sascha Hauer
2010-04-29  7:52 ` [PATCH 10/17] add arm helper function to determine the program counter Sascha Hauer
2010-04-29  7:52 ` [PATCH 11/17] arm: remove unused variables from header file Sascha Hauer
2010-04-29  7:52 ` Sascha Hauer [this message]
2010-04-29  7:52 ` [PATCH 13/17] arm: reimplement startup code in C Sascha Hauer
2010-04-29  7:52 ` [PATCH 14/17] i.MX: remove __REG from esd controller regs. use readl/writel instead Sascha Hauer
2010-04-29  7:52 ` [PATCH 15/17] pcm043: reimplement lowlevel code in C Sascha Hauer
2010-04-29  7:52 ` [PATCH 16/17] i.MX35: Fix ahbclock calculation Sascha Hauer
2010-04-29  7:52 ` [PATCH 17/17] pcm038: reimplement lowlevel code in C Sascha Hauer

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