* [PATCH 0/6] AT91 fies and new soc & board
@ 2010-08-19 2:48 Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
Hi,
the following patches add the support of the at91sam9261 with the
ek ref board and the pm9261 from Ronetix
this also prepare the re-adding of the RM9200 in the mach-at91
mmccpu: fix typo in AT91_MAIN_CLOCK (2010-08-18 23:21:16 +0800)
are available in the git repository at:
git://git.jcrosoft.org/barebox.git at91
Jean-Christophe PLAGNIOL-VILLARD (6):
dm9000: allow to specify that no srom is present
at91: Introduction of at91sam9261 SOC.
at91: add Ronetix pm9261 board support
at91: rename clocksource.c -> at91sam926x_time.c
macb: introduce HAS_MACB configuration
at91: remove non used and obsolete at91rm9200 code
arch/arm/Kconfig | 5 -
arch/arm/Makefile | 3 +-
arch/arm/boards/at91sam9261ek/Makefile | 1 +
arch/arm/boards/at91sam9261ek/config.h | 110 +++
arch/arm/boards/at91sam9261ek/env/bin/_update | 36 +
arch/arm/boards/at91sam9261ek/env/bin/boot | 47 ++
arch/arm/boards/at91sam9261ek/env/bin/hush_hack | 1 +
arch/arm/boards/at91sam9261ek/env/bin/init | 38 +
.../at91sam9261ek/env/bin/update_barebox_xmodem | 26 +
.../arm/boards/at91sam9261ek/env/bin/update_kernel | 15 +
arch/arm/boards/at91sam9261ek/env/bin/update_root | 16 +
arch/arm/boards/at91sam9261ek/env/config | 28 +
arch/arm/boards/at91sam9261ek/init.c | 170 +++++
arch/arm/boards/pm9261/Makefile | 1 +
arch/arm/boards/pm9261/config.h | 110 +++
arch/arm/boards/pm9261/env/bin/_update | 36 +
arch/arm/boards/pm9261/env/bin/boot | 47 ++
arch/arm/boards/pm9261/env/bin/hush_hack | 1 +
arch/arm/boards/pm9261/env/bin/init | 38 +
.../boards/pm9261/env/bin/update_barebox_xmodem | 26 +
arch/arm/boards/pm9261/env/bin/update_kernel | 15 +
arch/arm/boards/pm9261/env/bin/update_root | 16 +
arch/arm/boards/pm9261/env/config | 28 +
arch/arm/boards/pm9261/init.c | 169 +++++
arch/arm/boards/scb9328/scb9328.c | 1 +
arch/arm/configs/at91sam9261ek_defconfig | 242 +++++++
arch/arm/configs/pm9261_defconfig | 250 +++++++
arch/arm/mach-at91/Kconfig | 33 +
arch/arm/mach-at91/Makefile | 7 +-
arch/arm/mach-at91/at91sam9261.c | 230 ++++++
arch/arm/mach-at91/at91sam9261_devices.c | 169 +++++
.../{clocksource.c => at91sam926x_time.c} | 0
arch/arm/mach-at91/include/mach/at91sam9261.h | 109 +++
.../mach-at91/include/mach/at91sam9261_matrix.h | 64 ++
arch/arm/mach-at91rm9200/Kconfig | 16 -
arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h | 762 --------------------
arch/arm/mach-at91rm9200/include/mach/hardware.h | 78 --
drivers/net/Kconfig | 5 +-
drivers/net/dm9000.c | 6 +-
include/dm9000.h | 1 +
40 files changed, 2088 insertions(+), 868 deletions(-)
create mode 100644 arch/arm/boards/at91sam9261ek/Makefile
create mode 100644 arch/arm/boards/at91sam9261ek/config.h
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/_update
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/boot
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/hush_hack
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/init
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_barebox_xmodem
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_kernel
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_root
create mode 100644 arch/arm/boards/at91sam9261ek/env/config
create mode 100644 arch/arm/boards/at91sam9261ek/init.c
create mode 100644 arch/arm/boards/pm9261/Makefile
create mode 100644 arch/arm/boards/pm9261/config.h
create mode 100644 arch/arm/boards/pm9261/env/bin/_update
create mode 100644 arch/arm/boards/pm9261/env/bin/boot
create mode 100644 arch/arm/boards/pm9261/env/bin/hush_hack
create mode 100644 arch/arm/boards/pm9261/env/bin/init
create mode 100644 arch/arm/boards/pm9261/env/bin/update_barebox_xmodem
create mode 100644 arch/arm/boards/pm9261/env/bin/update_kernel
create mode 100644 arch/arm/boards/pm9261/env/bin/update_root
create mode 100644 arch/arm/boards/pm9261/env/config
create mode 100644 arch/arm/boards/pm9261/init.c
create mode 100644 arch/arm/configs/at91sam9261ek_defconfig
create mode 100644 arch/arm/configs/pm9261_defconfig
create mode 100644 arch/arm/mach-at91/at91sam9261.c
create mode 100644 arch/arm/mach-at91/at91sam9261_devices.c
rename arch/arm/mach-at91/{clocksource.c => at91sam926x_time.c} (100%)
create mode 100644 arch/arm/mach-at91/include/mach/at91sam9261.h
create mode 100644 arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
delete mode 100644 arch/arm/mach-at91rm9200/Kconfig
delete mode 100644 arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h
delete mode 100644 arch/arm/mach-at91rm9200/include/mach/hardware.h
Best Regards,
J.
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/6] dm9000: allow to specify that no srom is present
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:32 ` Sascha Hauer
2010-08-19 6:40 ` [PATCH 1/6 v2] " Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 2/6] at91: Introduction of at91sam9261 SOC Jean-Christophe PLAGNIOL-VILLARD
` (4 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/scb9328/scb9328.c | 1 +
drivers/net/dm9000.c | 6 ++++--
include/dm9000.h | 1 +
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index e781393..3c04996 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -55,6 +55,7 @@ static struct dm9000_platform_data dm9000_data = {
.iobase = 0x16000000,
.iodata = 0x16000004,
.buswidth = DM9000_WIDTH_16,
+ .srom = 1;
};
static struct device_d dm9000_dev = {
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2062c66..5f61ddc 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -498,8 +498,10 @@ static int dm9000_probe(struct device_d *dev)
edev->send = dm9000_eth_send;
edev->recv = dm9000_eth_rx;
edev->halt = dm9000_eth_halt;
- edev->get_ethaddr = dm9000_get_ethaddr;
- edev->set_ethaddr = dm9000_set_ethaddr;
+ if (pdata->srom) {
+ edev->get_ethaddr = dm9000_get_ethaddr;
+ edev->set_ethaddr = dm9000_set_ethaddr;
+ }
/* RESET device */
dm9000_reset(priv);
diff --git a/include/dm9000.h b/include/dm9000.h
index 3cc5235..b4a04b1 100644
--- a/include/dm9000.h
+++ b/include/dm9000.h
@@ -10,6 +10,7 @@ struct dm9000_platform_data {
unsigned long iobase;
unsigned long iodata;
int buswidth;
+ int srom;
};
#endif /* __DM9000_H__ */
--
1.7.1
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/6] at91: Introduction of at91sam9261 SOC.
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:52 ` Sascha Hauer
2010-08-19 2:48 ` [PATCH 3/6] at91: add Ronetix pm9261 board support Jean-Christophe PLAGNIOL-VILLARD
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
AT91sam9261 series is an ARM 926ej-s SOC family clocked at 190/100MHz.
The first board that embeds at91sam9261 chip is the AT91SAM9261-EK.
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/Makefile | 1 +
arch/arm/boards/at91sam9261ek/Makefile | 1 +
arch/arm/boards/at91sam9261ek/config.h | 110 +++++++++
arch/arm/boards/at91sam9261ek/env/bin/_update | 36 +++
arch/arm/boards/at91sam9261ek/env/bin/boot | 47 ++++
arch/arm/boards/at91sam9261ek/env/bin/hush_hack | 1 +
arch/arm/boards/at91sam9261ek/env/bin/init | 38 +++
.../at91sam9261ek/env/bin/update_barebox_xmodem | 26 ++
.../arm/boards/at91sam9261ek/env/bin/update_kernel | 15 ++
arch/arm/boards/at91sam9261ek/env/bin/update_root | 16 ++
arch/arm/boards/at91sam9261ek/env/config | 28 +++
arch/arm/boards/at91sam9261ek/init.c | 170 ++++++++++++++
arch/arm/configs/at91sam9261ek_defconfig | 242 ++++++++++++++++++++
arch/arm/mach-at91/Kconfig | 23 ++
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/at91sam9261.c | 230 +++++++++++++++++++
arch/arm/mach-at91/at91sam9261_devices.c | 169 ++++++++++++++
arch/arm/mach-at91/include/mach/at91sam9261.h | 109 +++++++++
.../mach-at91/include/mach/at91sam9261_matrix.h | 64 +++++
19 files changed, 1327 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boards/at91sam9261ek/Makefile
create mode 100644 arch/arm/boards/at91sam9261ek/config.h
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/_update
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/boot
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/hush_hack
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/init
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_barebox_xmodem
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_kernel
create mode 100644 arch/arm/boards/at91sam9261ek/env/bin/update_root
create mode 100644 arch/arm/boards/at91sam9261ek/env/config
create mode 100644 arch/arm/boards/at91sam9261ek/init.c
create mode 100644 arch/arm/configs/at91sam9261ek_defconfig
create mode 100644 arch/arm/mach-at91/at91sam9261.c
create mode 100644 arch/arm/mach-at91/at91sam9261_devices.c
create mode 100644 arch/arm/mach-at91/include/mach/at91sam9261.h
create mode 100644 arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 4827fe9..7d2a118 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -52,6 +52,7 @@ machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
board-$(CONFIG_MACH_A9M2410) := a9m2410
board-$(CONFIG_MACH_A9M2440) := a9m2440
board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
+board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek
board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek
board-$(CONFIG_MACH_EDB9301) := edb93xx
board-$(CONFIG_MACH_EDB9302) := edb93xx
diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile
new file mode 100644
index 0000000..eb072c0
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/Makefile
@@ -0,0 +1 @@
+obj-y += init.o
diff --git a/arch/arm/boards/at91sam9261ek/config.h b/arch/arm/boards/at91sam9261ek/config.h
new file mode 100644
index 0000000..bc33227
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/config.h
@@ -0,0 +1,110 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+
+#define MASTER_PLL_MUL 171
+#define MASTER_PLL_DIV 14
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ AT91_PMC_PLLCOUNT | /* PLL Counter */ \
+ (2 << 28) | /* PLL Clock Frequency Range */ \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+ (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_EBI0_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1 0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_3 | \
+ AT91_SDRAMC_DBW_32 | \
+ (1 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (1 << 28)) /* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/_update b/arch/arm/boards/at91sam9261ek/env/bin/_update
new file mode 100644
index 0000000..014bce3
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+ echo "define \$part and \$image"
+ exit 1
+fi
+
+if [ ! -e "$part" ]; then
+ echo "Partition $part does not exist"
+ exit 1
+fi
+
+if [ $# = 1 ]; then
+ image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+ dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+ echo "update aborted"
+ exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/boot b/arch/arm/boards/at91sam9261ek/env/bin/boot
new file mode 100644
index 0000000..533dea7
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/boot
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+ root=nand
+ kernel=nand
+fi
+
+if [ x$1 = xnet ]; then
+ root=net
+ kernel=net
+fi
+
+if [ x$1 = xnor ]; then
+ root=nor
+ kernel=nor
+fi
+
+if [ x$ip = xdhcp ]; then
+ bootargs="$bootargs ip=dhcp"
+else
+ bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xnand ]; then
+ bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+elif [ x$root = xnor ]; then
+ bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+else
+ bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts"
+
+if [ $kernel = net ]; then
+ if [ x$ip = xdhcp ]; then
+ dhcp
+ fi
+ tftp $uimage uImage || exit 1
+ bootm uImage
+elif [ $kernel = nor ]; then
+ bootm /dev/nor0.kernel
+else
+ bootm /dev/nand0.kernel.bb
+fi
+
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/hush_hack b/arch/arm/boards/at91sam9261ek/env/bin/hush_hack
new file mode 100644
index 0000000..5fffa92
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/hush_hack
@@ -0,0 +1 @@
+nand -a /dev/nand0.*
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/init b/arch/arm/boards/at91sam9261ek/env/bin/init
new file mode 100644
index 0000000..eaa298d
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/init
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+if [ -e /dev/nor0 ]; then
+ addpart /dev/nor0 $nor_parts
+fi
+
+if [ -e /dev/nand0 ]; then
+ addpart /dev/nand0 $nand_parts
+
+ # Uh, oh, hush first expands wildcards and then starts executing
+ # commands. What a bug!
+ source /env/bin/hush_hack
+fi
+
+if [ -z $eth0.ethaddr ]; then
+ while [ -z $eth0.ethaddr ]; do
+ readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+ done
+ echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+ echo
+ echo "type update_kernel nor [<imagename>] to update kernel into flash"
+ echo "type update_root nor [<imagename>] to update rootfs into flash"
+ echo "type update_barebox_xmodem nor to update barebox into flash"
+ echo
+ exit
+fi
+
+boot
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/update_barebox_xmodem b/arch/arm/boards/at91sam9261ek/env/bin/update_barebox_xmodem
new file mode 100644
index 0000000..39818b5
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/update_barebox_xmodem
@@ -0,0 +1,26 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.barebox
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.barebox
+else
+ echo "usage: $0 nor|nand"
+ exit 1
+fi
+
+loadb -f barebox.bin -c
+
+unprotect $part
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing barebox.bin to $part"
+echo
+cp barebox.bin $part
+crc32 -f barebox.bin
+crc32 -f $part
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/update_kernel b/arch/arm/boards/at91sam9261ek/env/bin/update_kernel
new file mode 100644
index 0000000..05c822d
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/update_kernel
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.kernel.bb
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.kernel
+else
+ echo "usage: $0 nor|nand [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/arch/arm/boards/at91sam9261ek/env/bin/update_root b/arch/arm/boards/at91sam9261ek/env/bin/update_root
new file mode 100644
index 0000000..a751372
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$jffs2
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.root
+else
+ echo "usage: $0 nor|nand [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config
new file mode 100644
index 0000000..4b322ad
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/env/config
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+# can be either 'net', 'nor' or 'nand''
+kernel=net
+root=net
+
+uimage=uImage
+jffs2=root.jffs2
+
+autoboot_timeout=3
+
+nfsroot=""
+bootargs="console=ttyS0,115200"
+
+nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
+rootpart_nor="/dev/mtdblock3"
+
+#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
+#rootpart_nand="/dev/mtdblock7"
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=192.168.23.1
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
new file mode 100644
index 0000000..e3c5494
--- /dev/null
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <init.h>
+#include <environment.h>
+#include <asm/armlinux.h>
+#include <asm/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <nand.h>
+#include <linux/mtd/nand.h>
+#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/io.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/sam9_smc.h>
+#include <dm9000.h>
+
+static struct atmel_nand_data nand_pdata = {
+ .ale = 22,
+ .cle = 21,
+/* .det_pin = ... not connected */
+ .rdy_pin = AT91_PIN_PC15,
+ .enable_pin = AT91_PIN_PC14,
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
+ .bus_width_16 = 1,
+#else
+ .bus_width_16 = 0,
+#endif
+};
+
+static struct sam9_smc_config ek_nand_smc_config = {
+ .ncs_read_setup = 0,
+ .nrd_setup = 1,
+ .ncs_write_setup = 0,
+ .nwe_setup = 1,
+
+ .ncs_read_pulse = 3,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 3,
+ .nwe_pulse = 3,
+
+ .read_cycle = 5,
+ .write_cycle = 5,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+ .tdf_cycles = 2,
+};
+
+static void ek_add_device_nand(void)
+{
+ /* setup bus-width (8 or 16) */
+ if (nand_pdata.bus_width_16)
+ ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+ else
+ ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+ /* configure chip-select 3 (NAND) */
+ sam9_smc_configure(3, &ek_nand_smc_config);
+
+ at91_add_device_nand(&nand_pdata);
+}
+
+/*
+ * DM9000 ethernet device
+ */
+#if defined(CONFIG_DRIVER_NET_DM9000)
+static struct dm9000_platform_data dm9000_data = {
+ .iobase = AT91_CHIPSELECT_2,
+ .iodata = AT91_CHIPSELECT_2 + 4,
+ .buswidth = DM9000_WIDTH_16,
+ .srom = 0,
+};
+
+static struct device_d dm9000_dev = {
+ .name = "dm9000",
+ .map_base = AT91_CHIPSELECT_2,
+ .size = 8,
+ .platform_data = &dm9000_data,
+};
+
+/*
+ * SMC timings for the DM9000.
+ * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
+ */
+static struct sam9_smc_config __initdata dm9000_smc_config = {
+ .ncs_read_setup = 0,
+ .nrd_setup = 2,
+ .ncs_write_setup = 0,
+ .nwe_setup = 2,
+
+ .ncs_read_pulse = 8,
+ .nrd_pulse = 4,
+ .ncs_write_pulse = 8,
+ .nwe_pulse = 4,
+
+ .read_cycle = 16,
+ .write_cycle = 16,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
+ .tdf_cycles = 1,
+};
+
+static void __init ek_add_device_dm9000(void)
+{
+ /* Configure chip-select 2 (DM9000) */
+ sam9_smc_configure(2, &dm9000_smc_config);
+
+ /* Configure Reset signal as output */
+ at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+ /* Configure Interrupt pin as input, no pull-up */
+ at91_set_gpio_input(AT91_PIN_PC11, 0);
+
+ register_device(&dm9000_dev);
+}
+#else
+static void __init ek_add_device_dm9000(void) {}
+#endif /* CONFIG_DRIVER_NET_DM9000 */
+
+static int at91sam9261ek_devices_init(void)
+{
+
+ at91_add_device_sdram(64 * 1024 * 1024);
+ ek_add_device_nand();
+ ek_add_device_dm9000();
+
+ devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw");
+ dev_add_bb_dev("self_raw", "self0");
+ devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw");
+ dev_add_bb_dev("env_raw", "env0");
+
+ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
+ armlinux_set_architecture(MACH_TYPE_AT91SAM9261EK);
+
+ return 0;
+}
+
+device_initcall(at91sam9261ek_devices_init);
+
+static int at91sam9261ek_console_init(void)
+{
+ at91_register_uart(0, 0);
+ return 0;
+}
+
+console_initcall(at91sam9261ek_console_init);
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
new file mode 100644
index 0000000..cb9ea75
--- /dev/null
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -0,0 +1,242 @@
+#
+# Automatically generated make config: don't edit
+# U-Boot version: 2.0.0-rc10
+# Wed Oct 21 16:33:44 2009
+#
+# CONFIG_BOARD_LINKER_SCRIPT is not set
+CONFIG_GENERIC_LINKER_SCRIPT=y
+CONFIG_ARM=y
+
+#
+# System Type
+#
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_S3C24xx is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+
+#
+# processor features
+#
+CONFIG_ARCH_TEXT_BASE=0x23f00000
+CONFIG_BOARDINFO="Atmel at91sam9261-ek"
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91SAM9260 is not set
+CONFIG_ARCH_AT91SAM9261=y
+# CONFIG_ARCH_AT91SAM9263 is not set
+CONFIG_MACH_AT91SAM9261EK=y
+# CONFIG_AEABI is not set
+
+#
+# Arm specific settings
+#
+CONFIG_CMD_ARM_CPUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_GREGORIAN_CALENDER=y
+CONFIG_HAS_KALLSYMS=y
+CONFIG_HAS_MODULES=y
+CONFIG_CMD_MEMORY=y
+CONFIG_ENV_HANDLING=y
+CONFIG_GENERIC_GPIO=y
+
+#
+# General Settings
+#
+CONFIG_LOCALVERSION_AUTO=y
+
+#
+# memory layout
+#
+CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
+CONFIG_TEXT_BASE=0x23f00000
+CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
+CONFIG_MEMORY_LAYOUT_DEFAULT=y
+# CONFIG_MEMORY_LAYOUT_FIXED is not set
+CONFIG_STACK_SIZE=0x8000
+CONFIG_MALLOC_SIZE=0x400000
+# CONFIG_BROKEN is not set
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_MACH_HAS_LOWLEVEL_INIT=y
+CONFIG_MACH_DO_LOWLEVEL_INIT=y
+CONFIG_PROMPT="9261-EK:"
+CONFIG_BAUDRATE=115200
+CONFIG_LONGHELP=y
+CONFIG_CBSIZE=1024
+CONFIG_MAXARGS=16
+CONFIG_SHELL_HUSH=y
+# CONFIG_SHELL_SIMPLE is not set
+CONFIG_GLOB=y
+CONFIG_PROMPT_HUSH_PS2="> "
+# CONFIG_HUSH_FANCY_PROMPT is not set
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_ERRNO_MESSAGES=y
+CONFIG_TIMESTAMP=y
+CONFIG_CONSOLE_FULL=y
+CONFIG_CONSOLE_ACTIVATE_FIRST=y
+# CONFIG_OF_FLAT_TREE is not set
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env"
+
+#
+# Debugging
+#
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_ENABLE_FLASH_NOISE is not set
+# CONFIG_ENABLE_PARTITION_NOISE is not set
+# CONFIG_ENABLE_DEVICE_NOISE is not set
+
+#
+# Commands
+#
+
+#
+# scripting
+#
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TRUE=y
+CONFIG_CMD_FALSE=y
+
+#
+# file commands
+#
+CONFIG_CMD_LS=y
+CONFIG_CMD_RM=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_MKDIR=y
+CONFIG_CMD_RMDIR=y
+CONFIG_CMD_CP=y
+CONFIG_CMD_PWD=y
+CONFIG_CMD_CD=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UMOUNT=y
+
+#
+# console
+#
+CONFIG_CMD_CLEAR=y
+CONFIG_CMD_ECHO=y
+# CONFIG_CMD_ECHO_E is not set
+
+#
+# memory
+#
+# CONFIG_CMD_LOADB is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_MTEST=y
+# CONFIG_CMD_MTEST_ALTERNATIVE is not set
+
+#
+# flash
+#
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_UBI=y
+
+#
+# booting
+#
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTU=y
+# CONFIG_CMD_LINUX16 is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_TEST=y
+CONFIG_CMD_VERSION=y
+CONFIG_CMD_HELP=y
+CONFIG_CMD_DEVINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+# CONFIG_NET_TFTP_PUSH is not set
+# CONFIG_NET_NETCONSOLE is not set
+# CONFIG_NET_RESOLV is not set
+
+#
+# Drivers
+#
+
+#
+# serial drivers
+#
+# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
+# CONFIG_DRIVER_SERIAL_NS16550 is not set
+CONFIG_DRIVER_SERIAL_ATMEL=y
+CONFIG_HAS_DM9000=y
+CONFIG_MIIPHY=y
+
+#
+# Network drivers
+#
+# CONFIG_DRIVER_NET_SMC911X is not set
+# CONFIG_DRIVER_NET_SMC91111 is not set
+CONFIG_DRIVER_NET_DM9000=y
+# CONFIG_DRIVER_NET_MACB is not set
+
+#
+# SPI drivers
+#
+# CONFIG_SPI is not set
+# CONFIG_I2C is not set
+
+#
+# flash drivers
+#
+# CONFIG_DRIVER_CFI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_ATMEL=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_UBI=y
+# CONFIG_ATA is not set
+# CONFIG_USB is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_VIDEO is not set
+
+#
+# Filesystem support
+#
+# CONFIG_FS_CRAMFS is not set
+CONFIG_FS_RAMFS=y
+CONFIG_FS_DEVFS=y
+CONFIG_PARTITION_NEED_MTD=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_CRC32=y
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 923ce0b..debc7dc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -6,6 +6,7 @@ config ARCH_TEXT_BASE
config BOARDINFO
default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260EK
+ default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK
default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
default "Bucyrus MMC-CPU" if MACH_MMCCPU
default "Ronetix PM9263" if MACH_PM9263
@@ -19,6 +20,10 @@ config ARCH_AT91SAM9260
bool "AT91SAM9260"
select CPU_ARM926T
+config ARCH_AT91SAM9261
+ bool "AT91SAM9261"
+ select CPU_ARM926T
+
config ARCH_AT91SAM9263
bool "AT91SAM9263"
select CPU_ARM926T
@@ -45,6 +50,24 @@ endif
# ----------------------------------------------------------
+if ARCH_AT91SAM9261
+
+choice
+ prompt "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+ bool "Atmel AT91SAM9261-EK Evaluation Kit"
+ select HAS_DM9000
+ help
+ Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+ <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+endchoice
+
+endif
+
+# ----------------------------------------------------------
+
if ARCH_AT91SAM9263
choice
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 0f55883..65a2657 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
# CPU-specific support
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o sam9_smc.o
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
new file mode 100644
index 0000000..3d503aa
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -0,0 +1,230 @@
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <asm/hardware.h>
+#include <mach/at91_pmc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+/* --------------------------------------------------------------------
+ * Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+ .name = "pioA_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+ .name = "pioB_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+ .name = "pioC_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+ .name = "usart0_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_US0,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+ .name = "usart1_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_US1,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+ .name = "usart2_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_US2,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+ .name = "mci_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_MCI,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+ .name = "udc_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_UDP,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi_clk = {
+ .name = "twi_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_TWI,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+ .name = "spi0_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+ .name = "spi1_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+ .name = "ssc0_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+ .name = "ssc1_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+ .name = "ssc2_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+ .name = "tc0_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_TC0,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+ .name = "tc1_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_TC1,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+ .name = "tc2_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_TC2,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+ .name = "ohci_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_UHP,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+ .name = "lcdc_clk",
+ .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] = {
+ &pioA_clk,
+ &pioB_clk,
+ &pioC_clk,
+ &usart0_clk,
+ &usart1_clk,
+ &usart2_clk,
+ &mmc_clk,
+ &udc_clk,
+ &twi_clk,
+ &spi0_clk,
+ &spi1_clk,
+ &ssc0_clk,
+ &ssc1_clk,
+ &ssc2_clk,
+ &tc0_clk,
+ &tc1_clk,
+ &tc2_clk,
+ &ohci_clk,
+ &lcdc_clk,
+ // irq0 .. irq2
+};
+
+/*
+ * The four programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+ .name = "pck0",
+ .pmc_mask = AT91_PMC_PCK0,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 0,
+};
+static struct clk pck1 = {
+ .name = "pck1",
+ .pmc_mask = AT91_PMC_PCK1,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 1,
+};
+static struct clk pck2 = {
+ .name = "pck2",
+ .pmc_mask = AT91_PMC_PCK2,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 2,
+};
+static struct clk pck3 = {
+ .name = "pck3",
+ .pmc_mask = AT91_PMC_PCK3,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 3,
+};
+
+/* HClocks */
+static struct clk hck0 = {
+ .name = "hck0",
+ .pmc_mask = AT91_PMC_HCK0,
+ .type = CLK_TYPE_SYSTEM,
+ .id = 0,
+};
+static struct clk hck1 = {
+ .name = "hck1",
+ .pmc_mask = AT91_PMC_HCK1,
+ .type = CLK_TYPE_SYSTEM,
+ .id = 1,
+};
+
+static void at91sam9261_register_clocks(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+ clk_register(periph_clocks[i]);
+
+ clk_register(&pck0);
+ clk_register(&pck1);
+ clk_register(&pck2);
+ clk_register(&pck3);
+
+ clk_register(&hck0);
+ clk_register(&hck1);
+}
+
+
+/* --------------------------------------------------------------------
+ * GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at91sam9261_gpio[] = {
+ {
+ .id = AT91SAM9261_ID_PIOA,
+ .offset = AT91_PIOA,
+ .clock = &pioA_clk,
+ }, {
+ .id = AT91SAM9261_ID_PIOB,
+ .offset = AT91_PIOB,
+ .clock = &pioB_clk,
+ }, {
+ .id = AT91SAM9261_ID_PIOC,
+ .offset = AT91_PIOC,
+ .clock = &pioC_clk,
+ }
+};
+
+
+static int at91sam9261_initialize(void)
+{
+ /* Init clock subsystem */
+ at91_clock_init(AT91_MAIN_CLOCK);
+
+ /* Register the processor-specific clocks */
+ at91sam9261_register_clocks();
+
+ /* Register GPIO subsystem */
+ at91_gpio_init(at91sam9261_gpio, 3);
+ return 0;
+}
+
+core_initcall(at91sam9261_initialize);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
new file mode 100644
index 0000000..6725e97
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -0,0 +1,169 @@
+/*
+ * arch/arm/mach-at91/at91sam9261_devices.c
+ *
+ * Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <common.h>
+#include <asm/armlinux.h>
+#include <asm/hardware.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9261_matrix.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/io.h>
+
+#include "generic.h"
+
+static struct memory_platform_data ram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .name = "mem",
+ .map_base = AT91_CHIPSELECT_1,
+ .platform_data = &ram_pdata,
+};
+
+void at91_add_device_sdram(u32 size)
+{
+ sdram_dev.size = size;
+ register_device(&sdram_dev);
+ armlinux_add_dram(&sdram_dev);
+}
+
+#if defined(CONFIG_NAND_ATMEL)
+static struct device_d nand_dev = {
+ .name = "atmel_nand",
+ .map_base = AT91_CHIPSELECT_3,
+ .size = 0x10,
+};
+
+void at91_add_device_nand(struct atmel_nand_data *data)
+{
+ unsigned long csa;
+
+ if (!data)
+ return;
+
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* enable pin */
+ if (data->enable_pin)
+ at91_set_gpio_output(data->enable_pin, 1);
+
+ /* ready/busy pin */
+ if (data->rdy_pin)
+ at91_set_gpio_input(data->rdy_pin, 1);
+
+ /* card detect pin */
+ if (data->det_pin)
+ at91_set_gpio_input(data->det_pin, 1);
+
+ at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
+ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
+
+ nand_dev.platform_data = data;
+ register_device(&nand_dev);
+}
+#else
+void at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+
+static struct device_d dbgu_serial_device = {
+ .name = "atmel_serial",
+ .map_base = (AT91_BASE_SYS + AT91_DBGU),
+ .size = 4096,
+};
+
+static inline void configure_dbgu_pins(void)
+{
+ at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
+ at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
+}
+
+static struct device_d uart0_serial_device = {
+ .name = "atmel_serial",
+ .map_base = AT91SAM9261_BASE_US0,
+ .size = 4096,
+};
+
+static inline void configure_usart0_pins(unsigned pins)
+{
+ at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
+ at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
+
+ if (pins & ATMEL_UART_RTS)
+ at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
+ if (pins & ATMEL_UART_CTS)
+ at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
+}
+
+static struct device_d uart1_serial_device = {
+ .name = "atmel_serial",
+ .map_base = AT91SAM9261_BASE_US1,
+ .size = 4096,
+};
+
+static inline void configure_usart1_pins(unsigned pins)
+{
+ at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
+ at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
+
+ if (pins & ATMEL_UART_RTS)
+ at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
+ if (pins & ATMEL_UART_CTS)
+ at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
+}
+
+static struct device_d uart2_serial_device = {
+ .name = "atmel_serial",
+ .map_base = AT91SAM9261_BASE_US2,
+ .size = 4096,
+};
+
+static inline void configure_usart2_pins(unsigned pins)
+{
+ at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
+ at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
+
+ if (pins & ATMEL_UART_RTS)
+ at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
+ if (pins & ATMEL_UART_CTS)
+ at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
+}
+
+void at91_register_uart(unsigned id, unsigned pins)
+{
+ switch (id) {
+ case 0: /* DBGU */
+ configure_dbgu_pins();
+ at91_clock_associate("mck", &dbgu_serial_device, "usart");
+ register_device(&dbgu_serial_device);
+ break;
+ case AT91SAM9261_ID_US0:
+ configure_usart0_pins(pins);
+ at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
+ register_device(&uart0_serial_device);
+ break;
+ case AT91SAM9261_ID_US1:
+ configure_usart1_pins(pins);
+ at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
+ register_device(&uart1_serial_device);
+ break;
+ case AT91SAM9261_ID_US2:
+ configure_usart2_pins(pins);
+ at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
+ register_device(&uart2_serial_device);
+ break;
+ default:
+ return;
+ }
+}
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
new file mode 100644
index 0000000..b303e07
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -0,0 +1,109 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
+ *
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
+#define AT91SAM9261_ID_US0 6 /* USART 0 */
+#define AT91SAM9261_ID_US1 7 /* USART 1 */
+#define AT91SAM9261_ID_US2 8 /* USART 2 */
+#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
+#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
+#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
+#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
+#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
+#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
+#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
+#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
+#define AT91SAM9261_ID_UHP 20 /* USB Host port */
+#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
+#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9261_BASE_TCB0 0xfffa0000
+#define AT91SAM9261_BASE_TC0 0xfffa0000
+#define AT91SAM9261_BASE_TC1 0xfffa0040
+#define AT91SAM9261_BASE_TC2 0xfffa0080
+#define AT91SAM9261_BASE_UDP 0xfffa4000
+#define AT91SAM9261_BASE_MCI 0xfffa8000
+#define AT91SAM9261_BASE_TWI 0xfffac000
+#define AT91SAM9261_BASE_US0 0xfffb0000
+#define AT91SAM9261_BASE_US1 0xfffb4000
+#define AT91SAM9261_BASE_US2 0xfffb8000
+#define AT91SAM9261_BASE_SSC0 0xfffbc000
+#define AT91SAM9261_BASE_SSC1 0xfffc0000
+#define AT91SAM9261_BASE_SSC2 0xfffc4000
+#define AT91SAM9261_BASE_SPI0 0xfffc8000
+#define AT91SAM9261_BASE_SPI1 0xfffcc000
+#define AT91_BASE_SYS 0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT91SAM9261_BASE_US0
+#define AT91_USART1 AT91SAM9261_BASE_US1
+#define AT91_USART2 AT91SAM9261_BASE_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
+
+#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
+
+#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
+#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
+
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME "AT91SAM9261"
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
new file mode 100644
index 0000000..7de0157
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -0,0 +1,64 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16 (5 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_ITCM_64 (7 << 0)
+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91_MATRIX_DTCM_64 (7 << 4)
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+
+#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
+#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
+
+#endif
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/6] at91: add Ronetix pm9261 board support
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 2/6] at91: Introduction of at91sam9261 SOC Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 4/6] at91: rename clocksource.c -> at91sam926x_time.c Jean-Christophe PLAGNIOL-VILLARD
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/Makefile | 1 +
arch/arm/boards/pm9261/Makefile | 1 +
arch/arm/boards/pm9261/config.h | 110 +++++++++
arch/arm/boards/pm9261/env/bin/_update | 36 +++
arch/arm/boards/pm9261/env/bin/boot | 47 ++++
arch/arm/boards/pm9261/env/bin/hush_hack | 1 +
arch/arm/boards/pm9261/env/bin/init | 38 +++
.../boards/pm9261/env/bin/update_barebox_xmodem | 26 ++
arch/arm/boards/pm9261/env/bin/update_kernel | 15 ++
arch/arm/boards/pm9261/env/bin/update_root | 16 ++
arch/arm/boards/pm9261/env/config | 28 +++
arch/arm/boards/pm9261/init.c | 169 +++++++++++++
arch/arm/configs/pm9261_defconfig | 250 ++++++++++++++++++++
arch/arm/mach-at91/Kconfig | 8 +
14 files changed, 746 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boards/pm9261/Makefile
create mode 100644 arch/arm/boards/pm9261/config.h
create mode 100644 arch/arm/boards/pm9261/env/bin/_update
create mode 100644 arch/arm/boards/pm9261/env/bin/boot
create mode 100644 arch/arm/boards/pm9261/env/bin/hush_hack
create mode 100644 arch/arm/boards/pm9261/env/bin/init
create mode 100644 arch/arm/boards/pm9261/env/bin/update_barebox_xmodem
create mode 100644 arch/arm/boards/pm9261/env/bin/update_kernel
create mode 100644 arch/arm/boards/pm9261/env/bin/update_root
create mode 100644 arch/arm/boards/pm9261/env/config
create mode 100644 arch/arm/boards/pm9261/init.c
create mode 100644 arch/arm/configs/pm9261_defconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7d2a118..c1e488c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -78,6 +78,7 @@ board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
board-$(CONFIG_MACH_PCM037) := pcm037
board-$(CONFIG_MACH_PCM038) := pcm038
board-$(CONFIG_MACH_PCM043) := pcm043
+board-$(CONFIG_MACH_PM9261) := pm9261
board-$(CONFIG_MACH_PM9263) := pm9263
board-$(CONFIG_MACH_SCB9328) := scb9328
board-$(CONFIG_MACH_NESO) := guf-neso
diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile
new file mode 100644
index 0000000..eb072c0
--- /dev/null
+++ b/arch/arm/boards/pm9261/Makefile
@@ -0,0 +1 @@
+obj-y += init.o
diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h
new file mode 100644
index 0000000..1c57448
--- /dev/null
+++ b/arch/arm/boards/pm9261/config.h
@@ -0,0 +1,110 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000 /* 16.367 MHz crystal */
+
+#define MASTER_PLL_DIV 15
+#define MASTER_PLL_MUL 162
+#define MAIN_PLL_DIV 2
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOSCEN | \
+ (255 << 8)) /* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_OUT | \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
+
+/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+ (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_3 | \
+ AT91_SDRAMC_DBW_32 | \
+ (1 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (3 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (1 << 28)) /* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_16 | \
+ AT91_SMC_TDFMODE | \
+ AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9261/env/bin/_update b/arch/arm/boards/pm9261/env/bin/_update
new file mode 100644
index 0000000..014bce3
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+ echo "define \$part and \$image"
+ exit 1
+fi
+
+if [ ! -e "$part" ]; then
+ echo "Partition $part does not exist"
+ exit 1
+fi
+
+if [ $# = 1 ]; then
+ image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+ dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+ echo "update aborted"
+ exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/arm/boards/pm9261/env/bin/boot b/arch/arm/boards/pm9261/env/bin/boot
new file mode 100644
index 0000000..533dea7
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/boot
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+ root=nand
+ kernel=nand
+fi
+
+if [ x$1 = xnet ]; then
+ root=net
+ kernel=net
+fi
+
+if [ x$1 = xnor ]; then
+ root=nor
+ kernel=nor
+fi
+
+if [ x$ip = xdhcp ]; then
+ bootargs="$bootargs ip=dhcp"
+else
+ bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xnand ]; then
+ bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+elif [ x$root = xnor ]; then
+ bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+else
+ bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts"
+
+if [ $kernel = net ]; then
+ if [ x$ip = xdhcp ]; then
+ dhcp
+ fi
+ tftp $uimage uImage || exit 1
+ bootm uImage
+elif [ $kernel = nor ]; then
+ bootm /dev/nor0.kernel
+else
+ bootm /dev/nand0.kernel.bb
+fi
+
diff --git a/arch/arm/boards/pm9261/env/bin/hush_hack b/arch/arm/boards/pm9261/env/bin/hush_hack
new file mode 100644
index 0000000..5fffa92
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/hush_hack
@@ -0,0 +1 @@
+nand -a /dev/nand0.*
diff --git a/arch/arm/boards/pm9261/env/bin/init b/arch/arm/boards/pm9261/env/bin/init
new file mode 100644
index 0000000..eaa298d
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/init
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+if [ -e /dev/nor0 ]; then
+ addpart /dev/nor0 $nor_parts
+fi
+
+if [ -e /dev/nand0 ]; then
+ addpart /dev/nand0 $nand_parts
+
+ # Uh, oh, hush first expands wildcards and then starts executing
+ # commands. What a bug!
+ source /env/bin/hush_hack
+fi
+
+if [ -z $eth0.ethaddr ]; then
+ while [ -z $eth0.ethaddr ]; do
+ readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+ done
+ echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+ echo
+ echo "type update_kernel nor [<imagename>] to update kernel into flash"
+ echo "type update_root nor [<imagename>] to update rootfs into flash"
+ echo "type update_barebox_xmodem nor to update barebox into flash"
+ echo
+ exit
+fi
+
+boot
diff --git a/arch/arm/boards/pm9261/env/bin/update_barebox_xmodem b/arch/arm/boards/pm9261/env/bin/update_barebox_xmodem
new file mode 100644
index 0000000..39818b5
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/update_barebox_xmodem
@@ -0,0 +1,26 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.barebox
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.barebox
+else
+ echo "usage: $0 nor|nand"
+ exit 1
+fi
+
+loadb -f barebox.bin -c
+
+unprotect $part
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing barebox.bin to $part"
+echo
+cp barebox.bin $part
+crc32 -f barebox.bin
+crc32 -f $part
diff --git a/arch/arm/boards/pm9261/env/bin/update_kernel b/arch/arm/boards/pm9261/env/bin/update_kernel
new file mode 100644
index 0000000..05c822d
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/update_kernel
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.kernel.bb
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.kernel
+else
+ echo "usage: $0 nor|nand [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/arch/arm/boards/pm9261/env/bin/update_root b/arch/arm/boards/pm9261/env/bin/update_root
new file mode 100644
index 0000000..a751372
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$jffs2
+if [ x$1 = xnand ]; then
+ part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+ part=/dev/nor0.root
+else
+ echo "usage: $0 nor|nand [imagename]"
+ exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/arch/arm/boards/pm9261/env/config b/arch/arm/boards/pm9261/env/config
new file mode 100644
index 0000000..4b322ad
--- /dev/null
+++ b/arch/arm/boards/pm9261/env/config
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+# can be either 'net', 'nor' or 'nand''
+kernel=net
+root=net
+
+uimage=uImage
+jffs2=root.jffs2
+
+autoboot_timeout=3
+
+nfsroot=""
+bootargs="console=ttyS0,115200"
+
+nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
+rootpart_nor="/dev/mtdblock3"
+
+#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
+#rootpart_nand="/dev/mtdblock7"
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=192.168.23.1
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
new file mode 100644
index 0000000..4b0813b
--- /dev/null
+++ b/arch/arm/boards/pm9261/init.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <init.h>
+#include <environment.h>
+#include <asm/armlinux.h>
+#include <asm/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <nand.h>
+#include <linux/mtd/nand.h>
+#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/io.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/sam9_smc.h>
+#include <dm9000.h>
+
+static struct atmel_nand_data nand_pdata = {
+ .ale = 22,
+ .cle = 21,
+/* .det_pin = ... not connected */
+ .rdy_pin = AT91_PIN_PA16,
+ .enable_pin = AT91_PIN_PC14,
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
+ .bus_width_16 = 1,
+#else
+ .bus_width_16 = 0,
+#endif
+};
+
+static struct sam9_smc_config pm_nand_smc_config = {
+ .ncs_read_setup = 0,
+ .nrd_setup = 1,
+ .ncs_write_setup = 0,
+ .nwe_setup = 1,
+
+ .ncs_read_pulse = 3,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 3,
+ .nwe_pulse = 3,
+
+ .read_cycle = 5,
+ .write_cycle = 5,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+ .tdf_cycles = 2,
+};
+
+static void pm_add_device_nand(void)
+{
+ /* setup bus-width (8 or 16) */
+ if (nand_pdata.bus_width_16)
+ pm_nand_smc_config.mode |= AT91_SMC_DBW_16;
+ else
+ pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+ /* configure chip-select 3 (NAND) */
+ sam9_smc_configure(3, &pm_nand_smc_config);
+
+ at91_add_device_nand(&nand_pdata);
+}
+
+/*
+ * DM9000 ethernet device
+ */
+#if defined(CONFIG_DRIVER_NET_DM9000)
+static struct dm9000_platform_data dm9000_data = {
+ .iobase = AT91_CHIPSELECT_2,
+ .iodata = AT91_CHIPSELECT_2 + 4,
+ .buswidth = DM9000_WIDTH_16,
+ .srom = 1,
+};
+
+static struct device_d dm9000_dev = {
+ .name = "dm9000",
+ .map_base = AT91_CHIPSELECT_2,
+ .size = 8,
+ .platform_data = &dm9000_data,
+};
+
+/*
+ * SMC timings for the DM9000.
+ * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
+ */
+static struct sam9_smc_config __initdata dm9000_smc_config = {
+ .ncs_read_setup = 0,
+ .nrd_setup = 2,
+ .ncs_write_setup = 0,
+ .nwe_setup = 2,
+
+ .ncs_read_pulse = 8,
+ .nrd_pulse = 4,
+ .ncs_write_pulse = 8,
+ .nwe_pulse = 4,
+
+ .read_cycle = 16,
+ .write_cycle = 16,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
+ .tdf_cycles = 1,
+};
+
+static void __init pm_add_device_dm9000(void)
+{
+ /* Configure chip-select 2 (DM9000) */
+ sam9_smc_configure(2, &dm9000_smc_config);
+
+ register_device(&dm9000_dev);
+}
+#else
+static void __init ek_add_device_dm9000(void) {}
+#endif /* CONFIG_DRIVER_NET_DM9000 */
+
+static struct device_d cfi_dev = {
+ .name = "cfi_flash",
+ .map_base = AT91_CHIPSELECT_0,
+ .size = 4 * 1024 * 1024,
+};
+
+static int pm9261_devices_init(void)
+{
+
+ at91_add_device_sdram(64 * 1024 * 1024);
+ pm_add_device_nand();
+ register_device(&cfi_dev);
+ pm_add_device_dm9000();
+
+ devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
+
+ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
+ armlinux_set_architecture(MACH_TYPE_PM9261);
+
+ return 0;
+}
+
+device_initcall(pm9261_devices_init);
+
+static int pm9261_console_init(void)
+{
+ at91_register_uart(0, 0);
+ return 0;
+}
+
+console_initcall(pm9261_console_init);
diff --git a/arch/arm/configs/pm9261_defconfig b/arch/arm/configs/pm9261_defconfig
new file mode 100644
index 0000000..a135ef7
--- /dev/null
+++ b/arch/arm/configs/pm9261_defconfig
@@ -0,0 +1,250 @@
+#
+# Automatically generated make config: don't edit
+# U-Boot version: 2.0.0-rc10
+# Wed Oct 21 16:44:38 2009
+#
+# CONFIG_BOARD_LINKER_SCRIPT is not set
+CONFIG_GENERIC_LINKER_SCRIPT=y
+CONFIG_ARM=y
+
+#
+# System Type
+#
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_S3C24xx is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+
+#
+# processor features
+#
+CONFIG_ARCH_TEXT_BASE=0x23f00000
+CONFIG_BOARDINFO="Ronetix PM9261"
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91SAM9260 is not set
+CONFIG_ARCH_AT91SAM9261=y
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_MACH_AT91SAM9261EK is not set
+CONFIG_MACH_PM9261=y
+# CONFIG_AEABI is not set
+
+#
+# Arm specific settings
+#
+CONFIG_CMD_ARM_CPUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_GREGORIAN_CALENDER=y
+CONFIG_HAS_KALLSYMS=y
+CONFIG_HAS_MODULES=y
+CONFIG_CMD_MEMORY=y
+CONFIG_ENV_HANDLING=y
+CONFIG_GENERIC_GPIO=y
+
+#
+# General Settings
+#
+CONFIG_LOCALVERSION_AUTO=y
+
+#
+# memory layout
+#
+CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
+CONFIG_TEXT_BASE=0x23f00000
+CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
+CONFIG_MEMORY_LAYOUT_DEFAULT=y
+# CONFIG_MEMORY_LAYOUT_FIXED is not set
+CONFIG_STACK_SIZE=0x8000
+CONFIG_MALLOC_SIZE=0x400000
+# CONFIG_BROKEN is not set
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_MACH_HAS_LOWLEVEL_INIT=y
+CONFIG_MACH_DO_LOWLEVEL_INIT=y
+CONFIG_PROMPT="PM9261:"
+CONFIG_BAUDRATE=115200
+CONFIG_LONGHELP=y
+CONFIG_CBSIZE=1024
+CONFIG_MAXARGS=16
+CONFIG_SHELL_HUSH=y
+# CONFIG_SHELL_SIMPLE is not set
+CONFIG_GLOB=y
+CONFIG_PROMPT_HUSH_PS2="> "
+# CONFIG_HUSH_FANCY_PROMPT is not set
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_ERRNO_MESSAGES=y
+CONFIG_TIMESTAMP=y
+CONFIG_CONSOLE_FULL=y
+CONFIG_CONSOLE_ACTIVATE_FIRST=y
+# CONFIG_OF_FLAT_TREE is not set
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9261/env/"
+
+#
+# Debugging
+#
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_ENABLE_FLASH_NOISE is not set
+# CONFIG_ENABLE_PARTITION_NOISE is not set
+# CONFIG_ENABLE_DEVICE_NOISE is not set
+
+#
+# Commands
+#
+
+#
+# scripting
+#
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TRUE=y
+CONFIG_CMD_FALSE=y
+
+#
+# file commands
+#
+CONFIG_CMD_LS=y
+CONFIG_CMD_RM=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_MKDIR=y
+CONFIG_CMD_RMDIR=y
+CONFIG_CMD_CP=y
+CONFIG_CMD_PWD=y
+CONFIG_CMD_CD=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UMOUNT=y
+
+#
+# console
+#
+CONFIG_CMD_CLEAR=y
+CONFIG_CMD_ECHO=y
+# CONFIG_CMD_ECHO_E is not set
+
+#
+# memory
+#
+# CONFIG_CMD_LOADB is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_MTEST=y
+# CONFIG_CMD_MTEST_ALTERNATIVE is not set
+
+#
+# flash
+#
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_UBI=y
+
+#
+# booting
+#
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTU=y
+# CONFIG_CMD_LINUX16 is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_TEST=y
+CONFIG_CMD_VERSION=y
+CONFIG_CMD_HELP=y
+CONFIG_CMD_DEVINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+# CONFIG_NET_TFTP_PUSH is not set
+# CONFIG_NET_NETCONSOLE is not set
+# CONFIG_NET_RESOLV is not set
+
+#
+# Drivers
+#
+
+#
+# serial drivers
+#
+# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
+# CONFIG_DRIVER_SERIAL_NS16550 is not set
+CONFIG_DRIVER_SERIAL_ATMEL=y
+CONFIG_HAS_DM9000=y
+CONFIG_MIIPHY=y
+
+#
+# Network drivers
+#
+# CONFIG_DRIVER_NET_SMC911X is not set
+# CONFIG_DRIVER_NET_SMC91111 is not set
+CONFIG_DRIVER_NET_DM9000=y
+# CONFIG_DRIVER_NET_MACB is not set
+
+#
+# SPI drivers
+#
+# CONFIG_SPI is not set
+# CONFIG_I2C is not set
+
+#
+# flash drivers
+#
+CONFIG_DRIVER_CFI=y
+CONFIG_DRIVER_CFI_INTEL=y
+CONFIG_DRIVER_CFI_AMD=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_1=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_2=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_4=y
+# CONFIG_DRIVER_CFI_BANK_WIDTH_8 is not set
+CONFIG_CFI_BUFFER_WRITE=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_ATMEL=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_UBI=y
+# CONFIG_ATA is not set
+# CONFIG_USB is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_VIDEO is not set
+
+#
+# Filesystem support
+#
+# CONFIG_FS_CRAMFS is not set
+CONFIG_FS_RAMFS=y
+CONFIG_FS_DEVFS=y
+CONFIG_PARTITION_NEED_MTD=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_CRC32=y
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index debc7dc..bea238b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -9,6 +9,7 @@ config BOARDINFO
default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK
default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
default "Bucyrus MMC-CPU" if MACH_MMCCPU
+ default "Ronetix PM9261" if MACH_PM9261
default "Ronetix PM9263" if MACH_PM9263
comment "Atmel AT91 System-on-Chip"
@@ -23,6 +24,7 @@ config ARCH_AT91SAM9260
config ARCH_AT91SAM9261
bool "AT91SAM9261"
select CPU_ARM926T
+ select MACH_HAS_LOWLEVEL_INIT
config ARCH_AT91SAM9263
bool "AT91SAM9263"
@@ -62,6 +64,12 @@ config MACH_AT91SAM9261EK
Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+config MACH_PM9261
+ bool "Ronetix PM9261"
+ select HAS_DM9000
+ help
+ Say y here if you are using the Ronetix PM9261 Board
+
endchoice
endif
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/6] at91: rename clocksource.c -> at91sam926x_time.c
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
` (2 preceding siblings ...)
2010-08-19 2:48 ` [PATCH 3/6] at91: add Ronetix pm9261 board support Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 5/6] macb: introduce HAS_MACB configuration Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 6/6] at91: remove non used and obsolete at91rm9200 code Jean-Christophe PLAGNIOL-VILLARD
5 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
preparation to move the rm9200 to the same api as other at91
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Makefile | 8 ++--
arch/arm/mach-at91/at91sam926x_time.c | 85 +++++++++++++++++++++++++++++++++
arch/arm/mach-at91/clocksource.c | 85 ---------------------------------
3 files changed, 89 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/mach-at91/at91sam926x_time.c
delete mode 100644 arch/arm/mach-at91/clocksource.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 65a2657..d711f6a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,8 +1,8 @@
-obj-y += clock.o clocksource.o gpio.o
+obj-y += clock.o gpio.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
# CPU-specific support
-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
new file mode 100644
index 0000000..84df1a1
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <asm/hardware.h>
+#include <mach/at91_pit.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/io.h>
+#include <asm/io.h>
+
+uint64_t at91sam9_clocksource_read(void)
+{
+ return at91_sys_read(AT91_PIT_PIIR);
+}
+
+static struct clocksource cs = {
+ .read = at91sam9_clocksource_read,
+ .mask = 0xffffffff,
+ .shift = 10,
+};
+
+static int clocksource_init (void)
+{
+ /*
+ * Enable PITC Clock
+ * The clock is already enabled for system controller in boot
+ */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+
+ /* Enable PITC */
+ at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
+
+ cs.mult = clocksource_hz2mult(1000000 * 6, cs.shift);
+
+ init_clock(&cs);
+
+ return 0;
+}
+
+core_initcall(clocksource_init);
+
+/*
+ * Reset the cpu through the reset controller
+ */
+void __noreturn reset_cpu (unsigned long ignored)
+{
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_PERRST);
+
+ /* Not reached */
+ while (1);
+}
+EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-at91/clocksource.c b/arch/arm/mach-at91/clocksource.c
deleted file mode 100644
index 84df1a1..0000000
--- a/arch/arm/mach-at91/clocksource.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <asm/hardware.h>
-#include <mach/at91_pit.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-#include <mach/io.h>
-#include <asm/io.h>
-
-uint64_t at91sam9_clocksource_read(void)
-{
- return at91_sys_read(AT91_PIT_PIIR);
-}
-
-static struct clocksource cs = {
- .read = at91sam9_clocksource_read,
- .mask = 0xffffffff,
- .shift = 10,
-};
-
-static int clocksource_init (void)
-{
- /*
- * Enable PITC Clock
- * The clock is already enabled for system controller in boot
- */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
-
- /* Enable PITC */
- at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
-
- cs.mult = clocksource_hz2mult(1000000 * 6, cs.shift);
-
- init_clock(&cs);
-
- return 0;
-}
-
-core_initcall(clocksource_init);
-
-/*
- * Reset the cpu through the reset controller
- */
-void __noreturn reset_cpu (unsigned long ignored)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
- AT91_RSTC_PROCRST |
- AT91_RSTC_PERRST);
-
- /* Not reached */
- while (1);
-}
-EXPORT_SYMBOL(reset_cpu);
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/6] macb: introduce HAS_MACB configuration
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
` (3 preceding siblings ...)
2010-08-19 2:48 ` [PATCH 4/6] at91: rename clocksource.c -> at91sam926x_time.c Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 6/6] at91: remove non used and obsolete at91rm9200 code Jean-Christophe PLAGNIOL-VILLARD
5 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 2 ++
drivers/net/Kconfig | 5 ++++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bea238b..ef54a17 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -20,6 +20,7 @@ choice
config ARCH_AT91SAM9260
bool "AT91SAM9260"
select CPU_ARM926T
+ select HAS_MACB
config ARCH_AT91SAM9261
bool "AT91SAM9261"
@@ -30,6 +31,7 @@ config ARCH_AT91SAM9263
bool "AT91SAM9263"
select CPU_ARM926T
select MACH_HAS_LOWLEVEL_INIT
+ select HAS_MACB
endchoice
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0955562..a106a7b 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -4,6 +4,9 @@ config HAS_CS8900
config HAS_DM9000
bool
+config HAS_MACB
+ bool
+
config HAS_AT91_ETHER
bool
@@ -71,7 +74,7 @@ config DRIVER_NET_EP93XX
config DRIVER_NET_MACB
bool "macb Ethernet driver"
- depends on ARCH_AT91
+ depends on HAS_MACB
select MIIPHY
config DRIVER_NET_TAP
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 6/6] at91: remove non used and obsolete at91rm9200 code
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
` (4 preceding siblings ...)
2010-08-19 2:48 ` [PATCH 5/6] macb: introduce HAS_MACB configuration Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 2:48 ` Jean-Christophe PLAGNIOL-VILLARD
5 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 2:48 UTC (permalink / raw)
To: barebox
this will be re-add as mach-at91
for now on keep the net driver which will be updated to new API
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/Kconfig | 5 -
arch/arm/Makefile | 1 -
arch/arm/mach-at91rm9200/Kconfig | 16 -
arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h | 762 --------------------
arch/arm/mach-at91rm9200/include/mach/hardware.h | 78 --
5 files changed, 0 insertions(+), 862 deletions(-)
delete mode 100644 arch/arm/mach-at91rm9200/Kconfig
delete mode 100644 arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h
delete mode 100644 arch/arm/mach-at91rm9200/include/mach/hardware.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 82dbfda..945528c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -30,10 +30,6 @@ config ARCH_AT91
bool "Atmel AT91"
select GENERIC_GPIO
-config ARCH_AT91RM9200
- bool "Atmel AT91RM9200"
- select CPU_ARM920T
-
config ARCH_EP93XX
bool "Cirrus Logic EP93xx"
select CPU_ARM920T
@@ -65,7 +61,6 @@ endchoice
source arch/arm/common/Kconfig
source arch/arm/cpu/Kconfig
source arch/arm/mach-at91/Kconfig
-source arch/arm/mach-at91rm9200/Kconfig
source arch/arm/mach-ep93xx/Kconfig
source arch/arm/mach-imx/Kconfig
source arch/arm/mach-netx/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c1e488c..2d03ac9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -39,7 +39,6 @@ CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91
-machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
deleted file mode 100644
index c062097..0000000
--- a/arch/arm/mach-at91rm9200/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if ARCH_AT91RM9200
-
-config ARCH_TEXT_BASE
- hex
-
-config BOARDINFO
-
-comment "Atmel AT91RM9200 System-on-Chip"
-
-choice
-
- prompt "AT91RM9200 Board Type"
-
-endchoice
-
-endif
diff --git a/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h b/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h
deleted file mode 100644
index 97d4704..0000000
--- a/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
- * (C) Copyright 2003
- * AT91RM9200 definitions
- * Author : ATMEL AT91 application group
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-typedef volatile unsigned int AT91_REG; /* Hardware register definition */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/******************************************************************************/
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register */
- AT91_REG Reserved0[2]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
-} AT91S_TC, *AT91PS_TC;
-
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Usart */
-/******************************************************************************/
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[5]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG US_XXR; /* XON_XOFF Register */
- AT91_REG US_IF; /* IRDA_FILTER Register */
- AT91_REG Reserved1[44]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
-} AT91S_USART, *AT91PS_USART;
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/******************************************************************************/
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG CKGR_PLLAR; /* PLL A Register */
- AT91_REG CKGR_PLLBR; /* PLL B Register */
-} AT91S_CKGR, *AT91PS_CKGR;
-
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
-
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
-
-/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
-#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */
-#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
-#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
-#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
-
-/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */
-#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
-#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */
-#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
-#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/******************************************************************************/
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[1]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[1]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[1]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[1]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
- AT91_REG Reserved4[1]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[9]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/******************************************************************************/
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[7]; /* */
- AT91_REG DBGU_C1R; /* Chip ID1 Register */
- AT91_REG DBGU_C2R; /* Chip ID2 Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[45]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
-} AT91S_DBGU, *AT91PS_DBGU;
-
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
-
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
-/******************************************************************************/
-typedef struct _AT91S_SMC2
-{
- AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
-} AT91S_SMC2, *AT91PS_SMC2;
-
-/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
-#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
-#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
-#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
-#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
-#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
-#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
-#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
-#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/******************************************************************************/
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[1]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[5]; /* */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved2[3]; /* */
- AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
-} AT91S_PMC, *AT91PS_PMC;
-
-/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
-#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
-/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
-/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
-/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
-#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
-#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
-#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
-#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
-#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
-#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
-/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
-/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
-/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
-/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
-/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Ethernet MAC */
-/******************************************************************************/
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_CTL; /* Network Control Register */
- AT91_REG EMAC_CFG; /* Network Configuration Register */
- AT91_REG EMAC_SR; /* Network Status Register */
- AT91_REG EMAC_TAR; /* Transmit Address Register */
- AT91_REG EMAC_TCR; /* Transmit Control Register */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG Reserved0[1]; /* */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG Reserved1[2]; /* */
- AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
- AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
- AT91_REG EMAC_OK; /* Frames Received OK Register */
- AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CDE; /* Code Error Register */
- AT91_REG EMAC_ELR; /* Excessive Length Error Register */
- AT91_REG EMAC_RJB; /* Receive Jabber Register */
- AT91_REG EMAC_USF; /* Undersize Frame Register */
- AT91_REG EMAC_SQEE; /* SQE Test Error Register */
- AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
- AT91_REG Reserved2[3]; /* */
- AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
- AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
-} AT91S_EMAC, *AT91PS_EMAC;
-
-/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
-#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
-
-/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */
-#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
-
-/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
-#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
-
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
-#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
-#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
-
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
-#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */
-#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
-
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
-
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
-#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
-#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
-#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
-#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
-#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
-#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
-#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
-#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
-#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
-#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
-#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
-
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
-#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
-#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
-#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
-#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
-#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
-#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
-#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
-#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
-#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/******************************************************************************/
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[4]; /* */
- AT91_REG SPI_CSR[4]; /* Chip Select Register */
- AT91_REG Reserved1[48]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
-} AT91S_SPI, *AT91PS_SPI;
-
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
-
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
-
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
-
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/******************************************************************************/
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
-} AT91S_PDC, *AT91PS_PDC;
-
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
-
-/* ========== Register definition ==================================== */
-#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */
-#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */
-#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */
-#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
-#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
-#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
-#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
-#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
-#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
-#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
-#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
-#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
-#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
-#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
-#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
-#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
-#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
-#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
-#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
-#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
-#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
-#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
-#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
-#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
-#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
-#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
-#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
-#define AT91C_PA25_TWD ((unsigned int) 1 << 25)
-#define AT91C_PA26_TWCK ((unsigned int) 1 << 26)
-#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */
-#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */
-#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */
-#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */
-#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */
-
-#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
-#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */
-#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */
-#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */
-#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */
-#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */
-#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */
-#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
-#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */
-#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
-#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
-
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
-#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
-
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */
-#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */
-#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */
-#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */
-#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */
-#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */
-#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
-#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
-
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
-
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
-#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
-#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */
-#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
-#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-
-#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
-
-#endif
diff --git a/arch/arm/mach-at91rm9200/include/mach/hardware.h b/arch/arm/mach-at91rm9200/include/mach/hardware.h
deleted file mode 100644
index a84c60a..0000000
--- a/arch/arm/mach-at91rm9200/include/mach/hardware.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * linux/include/asm-arm/arch-at91/hardware.h
- *
- * Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <sizes.h>
-
-#ifndef __ASSEMBLY__
-#include "AT91RM9200.h"
-#else
-#include "AT91RM9200_inc.h"
-#endif
-
-/* Virtual and Physical base address for system peripherals */
-#define AT91_SYS_BASE 0xFFFFF000 /*4K */
-
-/* Virtual and Physical base addresses of user peripherals */
-#define AT91_SPI_BASE 0xFFFE0000 /*16K */
-#define AT91_SSC2_BASE 0xFFFD8000 /*16K */
-#define AT91_SSC1_BASE 0xFFFD4000 /*16K */
-#define AT91_SSC0_BASE 0xFFFD0000 /*16K */
-#define AT91_USART3_BASE 0xFFFCC000 /*16K */
-#define AT91_USART2_BASE 0xFFFC8000 /*16K */
-#define AT91_USART1_BASE 0xFFFC4000 /*16K */
-#define AT91_USART0_BASE 0xFFFC0000 /*16K */
-#define AT91_EMAC_BASE 0xFFFBC000 /*16K */
-#define AT91_TWI_BASE 0xFFFB8000 /*16K */
-#define AT91_MCI_BASE 0xFFFB4000 /*16K */
-#define AT91_UDP_BASE 0xFFFB0000 /*16K */
-#define AT91_TCB1_BASE 0xFFFA4000 /*16K */
-#define AT91_TCB0_BASE 0xFFFA0000 /*16K */
-
-#define AT91_USB_HOST_BASE 0x00300000
-#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */
-
-/* FLASH */
-#define AT91_FLASH_BASE 0x10000000 /* NCS0 */
-
-/* SDRAM */
-#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */
-
-/* Definition of interrupt priority levels */
-#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
-#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
-#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
-#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
-#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
-#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
-#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
-#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
-
-#endif
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] dm9000: allow to specify that no srom is present
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 6:32 ` Sascha Hauer
2010-08-19 6:40 ` [PATCH 1/6 v2] " Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 0 replies; 12+ messages in thread
From: Sascha Hauer @ 2010-08-19 6:32 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
Hi Jean-Christophe,
On Thu, Aug 19, 2010 at 04:48:25AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/boards/scb9328/scb9328.c | 1 +
> drivers/net/dm9000.c | 6 ++++--
> include/dm9000.h | 1 +
> 3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
> index e781393..3c04996 100644
> --- a/arch/arm/boards/scb9328/scb9328.c
> +++ b/arch/arm/boards/scb9328/scb9328.c
> @@ -55,6 +55,7 @@ static struct dm9000_platform_data dm9000_data = {
> .iobase = 0x16000000,
> .iodata = 0x16000004,
> .buswidth = DM9000_WIDTH_16,
> + .srom = 1;
> };
>
> static struct device_d dm9000_dev = {
> diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
> index 2062c66..5f61ddc 100644
> --- a/drivers/net/dm9000.c
> +++ b/drivers/net/dm9000.c
> @@ -498,8 +498,10 @@ static int dm9000_probe(struct device_d *dev)
> edev->send = dm9000_eth_send;
> edev->recv = dm9000_eth_rx;
> edev->halt = dm9000_eth_halt;
> - edev->get_ethaddr = dm9000_get_ethaddr;
> - edev->set_ethaddr = dm9000_set_ethaddr;
> + if (pdata->srom) {
> + edev->get_ethaddr = dm9000_get_ethaddr;
> + edev->set_ethaddr = dm9000_set_ethaddr;
> + }
edev->set_ethaddr is not an optional call. Without it the driver won't
work.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/6 v2] dm9000: allow to specify that no srom is present
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:32 ` Sascha Hauer
@ 2010-08-19 6:40 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:42 ` Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 6:40 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
v2:
keep set_ethaddr
Best Regards,
J.
arch/arm/boards/scb9328/scb9328.c | 1 +
drivers/net/dm9000.c | 3 ++-
include/dm9000.h | 1 +
3 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index e781393..3c04996 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -55,6 +55,7 @@ static struct dm9000_platform_data dm9000_data = {
.iobase = 0x16000000,
.iodata = 0x16000004,
.buswidth = DM9000_WIDTH_16,
+ .srom = 1;
};
static struct device_d dm9000_dev = {
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2062c66..ab06735 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -498,8 +498,9 @@ static int dm9000_probe(struct device_d *dev)
edev->send = dm9000_eth_send;
edev->recv = dm9000_eth_rx;
edev->halt = dm9000_eth_halt;
- edev->get_ethaddr = dm9000_get_ethaddr;
edev->set_ethaddr = dm9000_set_ethaddr;
+ if (pdata->srom)
+ edev->get_ethaddr = dm9000_get_ethaddr;
/* RESET device */
dm9000_reset(priv);
diff --git a/include/dm9000.h b/include/dm9000.h
index 3cc5235..b4a04b1 100644
--- a/include/dm9000.h
+++ b/include/dm9000.h
@@ -10,6 +10,7 @@ struct dm9000_platform_data {
unsigned long iobase;
unsigned long iodata;
int buswidth;
+ int srom;
};
#endif /* __DM9000_H__ */
--
1.7.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6 v2] dm9000: allow to specify that no srom is present
2010-08-19 6:40 ` [PATCH 1/6 v2] " Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 6:42 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 6:42 UTC (permalink / raw)
To: barebox
On 08:40 Thu 19 Aug , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> v2:
>
> keep set_ethaddr
git://git.jcrosoft.org branch at91 updated
Best Regards,
J.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/6] at91: Introduction of at91sam9261 SOC.
2010-08-19 2:48 ` [PATCH 2/6] at91: Introduction of at91sam9261 SOC Jean-Christophe PLAGNIOL-VILLARD
@ 2010-08-19 6:52 ` Sascha Hauer
2010-08-19 15:42 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 12+ messages in thread
From: Sascha Hauer @ 2010-08-19 6:52 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Thu, Aug 19, 2010 at 04:48:26AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> AT91sam9261 series is an ARM 926ej-s SOC family clocked at 190/100MHz.
>
> The first board that embeds at91sam9261 chip is the AT91SAM9261-EK.
> http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/Makefile | 1 +
> arch/arm/boards/at91sam9261ek/Makefile | 1 +
> arch/arm/boards/at91sam9261ek/config.h | 110 +++++++++
> arch/arm/boards/at91sam9261ek/env/bin/_update | 36 +++
> arch/arm/boards/at91sam9261ek/env/bin/boot | 47 ++++
> arch/arm/boards/at91sam9261ek/env/bin/hush_hack | 1 +
> arch/arm/boards/at91sam9261ek/env/bin/init | 38 +++
> .../at91sam9261ek/env/bin/update_barebox_xmodem | 26 ++
> .../arm/boards/at91sam9261ek/env/bin/update_kernel | 15 ++
> arch/arm/boards/at91sam9261ek/env/bin/update_root | 16 ++
> arch/arm/boards/at91sam9261ek/env/config | 28 +++
Care to use the generic environment? What's missing in it for you to use
it?
> arch/arm/boards/at91sam9261ek/init.c | 170 ++++++++++++++
> arch/arm/configs/at91sam9261ek_defconfig | 242 ++++++++++++++++++++
> arch/arm/mach-at91/Kconfig | 23 ++
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/at91sam9261.c | 230 +++++++++++++++++++
> arch/arm/mach-at91/at91sam9261_devices.c | 169 ++++++++++++++
> arch/arm/mach-at91/include/mach/at91sam9261.h | 109 +++++++++
Can you please make two patches out of this? One for the architecture
support and another one for the board support.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/6] at91: Introduction of at91sam9261 SOC.
2010-08-19 6:52 ` Sascha Hauer
@ 2010-08-19 15:42 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 12+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-08-19 15:42 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 08:52 Thu 19 Aug , Sascha Hauer wrote:
> On Thu, Aug 19, 2010 at 04:48:26AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > AT91sam9261 series is an ARM 926ej-s SOC family clocked at 190/100MHz.
> >
> > The first board that embeds at91sam9261 chip is the AT91SAM9261-EK.
> > http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820
> >
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> > ---
> > arch/arm/Makefile | 1 +
> > arch/arm/boards/at91sam9261ek/Makefile | 1 +
> > arch/arm/boards/at91sam9261ek/config.h | 110 +++++++++
> > arch/arm/boards/at91sam9261ek/env/bin/_update | 36 +++
> > arch/arm/boards/at91sam9261ek/env/bin/boot | 47 ++++
> > arch/arm/boards/at91sam9261ek/env/bin/hush_hack | 1 +
> > arch/arm/boards/at91sam9261ek/env/bin/init | 38 +++
> > .../at91sam9261ek/env/bin/update_barebox_xmodem | 26 ++
> > .../arm/boards/at91sam9261ek/env/bin/update_kernel | 15 ++
> > arch/arm/boards/at91sam9261ek/env/bin/update_root | 16 ++
> > arch/arm/boards/at91sam9261ek/env/config | 28 +++
>
> Care to use the generic environment? What's missing in it for you to use
> it?
miss it in the code
>
> > arch/arm/boards/at91sam9261ek/init.c | 170 ++++++++++++++
> > arch/arm/configs/at91sam9261ek_defconfig | 242 ++++++++++++++++++++
> > arch/arm/mach-at91/Kconfig | 23 ++
> > arch/arm/mach-at91/Makefile | 1 +
> > arch/arm/mach-at91/at91sam9261.c | 230 +++++++++++++++++++
> > arch/arm/mach-at91/at91sam9261_devices.c | 169 ++++++++++++++
> > arch/arm/mach-at91/include/mach/at91sam9261.h | 109 +++++++++
>
> Can you please make two patches out of this? One for the architecture
> support and another one for the board support.
Personnaly I prefer to add the first board at the same as e do for the kernel
otherwise ok
Best Regards,
J.
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2010-08-19 15:47 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-08-19 2:48 [PATCH 0/6] AT91 fies and new soc & board Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 1/6] dm9000: allow to specify that no srom is present Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:32 ` Sascha Hauer
2010-08-19 6:40 ` [PATCH 1/6 v2] " Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:42 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 2/6] at91: Introduction of at91sam9261 SOC Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 6:52 ` Sascha Hauer
2010-08-19 15:42 ` Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 3/6] at91: add Ronetix pm9261 board support Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 4/6] at91: rename clocksource.c -> at91sam926x_time.c Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 5/6] macb: introduce HAS_MACB configuration Jean-Christophe PLAGNIOL-VILLARD
2010-08-19 2:48 ` [PATCH 6/6] at91: remove non used and obsolete at91rm9200 code Jean-Christophe PLAGNIOL-VILLARD
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