* [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text"
@ 2010-09-05 16:41 Jean-Christophe PLAGNIOL-VILLARD
2010-09-05 17:12 ` Sam Ravnborg
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-09-05 16:41 UTC (permalink / raw)
To: barebox
and make init.h availlable for assembly too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/cpu/cache-armv4.S | 3 ++-
arch/arm/cpu/cache-armv5.S | 3 ++-
arch/arm/cpu/cache-armv6.S | 3 ++-
arch/arm/cpu/cache-armv7.S | 3 ++-
include/init.h | 6 ++++++
5 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 3cec4dd..fc53653 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define CACHE_DLINESIZE 32
@@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index 9fb320f..d870e6b 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define CACHE_DLINESIZE 32
@@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index 25476d5..9de76da 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define HARVARD_CACHE
#define CACHE_LINE_SIZE 32
@@ -43,7 +44,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index a303dc1..79bc243 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
ENTRY(__mmu_cache_on)
mov r12, lr
@@ -49,7 +50,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_on)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
diff --git a/include/init.h b/include/init.h
index 8692b68..5a7a5b6 100644
--- a/include/init.h
+++ b/include/init.h
@@ -7,6 +7,10 @@
#define __init
#define __initdata
+/* For assembly routines */
+#define __BARE_INIT .section ".text_bare_init.text"
+
+#ifndef __ASSEMBLY__
typedef int (*initcall_t)(void);
#define __define_initcall(level,fn,id) \
@@ -40,5 +44,7 @@ typedef int (*initcall_t)(void);
*/
#define __bare_init __section(.text_bare_init.text)
+#endif
+
#endif /* _INIT_H */
--
1.7.1
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text"
2010-09-05 16:41 [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text" Jean-Christophe PLAGNIOL-VILLARD
@ 2010-09-05 17:12 ` Sam Ravnborg
2010-09-12 11:30 ` [PATCH v2] " Jean-Christophe PLAGNIOL-VILLARD
2010-09-16 10:56 ` [PATCH] " Sascha Hauer
2 siblings, 0 replies; 5+ messages in thread
From: Sam Ravnborg @ 2010-09-05 17:12 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
> diff --git a/include/init.h b/include/init.h
> index 8692b68..5a7a5b6 100644
> --- a/include/init.h
> +++ b/include/init.h
> @@ -7,6 +7,10 @@
> #define __init
> #define __initdata
>
> +/* For assembly routines */
> +#define __BARE_INIT .section ".text_bare_init.text"
You should consider using:
#define __BARE_INIT .section ".text_bare_init.text","ax"
Then you do not rely on the as/ld to add these flags.
In the kernel we had a few cases where it mattered.
Sam
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] init: introduce __BARE_INIT for .section ".text_bare_init.text"
2010-09-05 16:41 [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text" Jean-Christophe PLAGNIOL-VILLARD
2010-09-05 17:12 ` Sam Ravnborg
@ 2010-09-12 11:30 ` Jean-Christophe PLAGNIOL-VILLARD
2010-09-16 10:56 ` [PATCH] " Sascha Hauer
2 siblings, 0 replies; 5+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-09-12 11:30 UTC (permalink / raw)
To: barebox
and make init.h availlable for assembly too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/cpu/cache-armv4.S | 3 ++-
arch/arm/cpu/cache-armv5.S | 3 ++-
arch/arm/cpu/cache-armv6.S | 3 ++-
arch/arm/cpu/cache-armv7.S | 3 ++-
include/init.h | 6 ++++++
5 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 3cec4dd..fc53653 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define CACHE_DLINESIZE 32
@@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index 9fb320f..d870e6b 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define CACHE_DLINESIZE 32
@@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index 25476d5..9de76da 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define HARVARD_CACHE
#define CACHE_LINE_SIZE 32
@@ -43,7 +44,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index a303dc1..79bc243 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
ENTRY(__mmu_cache_on)
mov r12, lr
@@ -49,7 +50,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_on)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
diff --git a/include/init.h b/include/init.h
index 8692b68..2f4fac1 100644
--- a/include/init.h
+++ b/include/init.h
@@ -7,6 +7,10 @@
#define __init
#define __initdata
+/* For assembly routines */
+#define __BARE_INIT .section ".text_bare_init.text","ax"
+
+#ifndef __ASSEMBLY__
typedef int (*initcall_t)(void);
#define __define_initcall(level,fn,id) \
@@ -40,5 +44,7 @@ typedef int (*initcall_t)(void);
*/
#define __bare_init __section(.text_bare_init.text)
+#endif
+
#endif /* _INIT_H */
--
1.7.1
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text"
2010-09-05 16:41 [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text" Jean-Christophe PLAGNIOL-VILLARD
2010-09-05 17:12 ` Sam Ravnborg
2010-09-12 11:30 ` [PATCH v2] " Jean-Christophe PLAGNIOL-VILLARD
@ 2010-09-16 10:56 ` Sascha Hauer
2010-09-16 11:12 ` Jean-Christophe PLAGNIOL-VILLARD
2 siblings, 1 reply; 5+ messages in thread
From: Sascha Hauer @ 2010-09-16 10:56 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sun, Sep 05, 2010 at 06:41:59PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> and make init.h availlable for assembly too
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/cpu/cache-armv4.S | 3 ++-
> arch/arm/cpu/cache-armv5.S | 3 ++-
> arch/arm/cpu/cache-armv6.S | 3 ++-
> arch/arm/cpu/cache-armv7.S | 3 ++-
> include/init.h | 6 ++++++
> 5 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
> index 3cec4dd..fc53653 100644
> --- a/arch/arm/cpu/cache-armv4.S
> +++ b/arch/arm/cpu/cache-armv4.S
> @@ -1,4 +1,5 @@
> #include <linux/linkage.h>
> +#include <init.h>
>
> #define CACHE_DLINESIZE 32
>
> @@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
> mov pc, lr
> ENDPROC(__mmu_cache_off)
>
> -.section ".text_bare_init.text"
> +__BARE_INIT
> ENTRY(__mmu_cache_flush)
> mrc p15, 0, r6, c0, c0 @ get processor ID
> mov r2, #64*1024 @ default: 32K dcache size (*2)
> diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
> index 9fb320f..d870e6b 100644
> --- a/arch/arm/cpu/cache-armv5.S
> +++ b/arch/arm/cpu/cache-armv5.S
> @@ -1,4 +1,5 @@
> #include <linux/linkage.h>
> +#include <init.h>
>
> #define CACHE_DLINESIZE 32
>
> @@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
> mov pc, lr
> ENDPROC(__mmu_cache_off)
>
> -.section ".text_bare_init.text"
> +__BARE_INIT
> ENTRY(__mmu_cache_flush)
> 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
> bne 1b
> diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
> index 25476d5..9de76da 100644
> --- a/arch/arm/cpu/cache-armv6.S
> +++ b/arch/arm/cpu/cache-armv6.S
> @@ -1,4 +1,5 @@
> #include <linux/linkage.h>
> +#include <init.h>
>
> #define HARVARD_CACHE
> #define CACHE_LINE_SIZE 32
> @@ -43,7 +44,7 @@ ENTRY(__mmu_cache_off)
> #endif
> mov pc, lr
>
> -.section ".text_bare_init.text"
> +__BARE_INIT
> ENTRY(__mmu_cache_flush)
> mov r1, #0
> mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
> diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
> index a303dc1..79bc243 100644
> --- a/arch/arm/cpu/cache-armv7.S
> +++ b/arch/arm/cpu/cache-armv7.S
> @@ -1,4 +1,5 @@
> #include <linux/linkage.h>
> +#include <init.h>
>
> ENTRY(__mmu_cache_on)
> mov r12, lr
> @@ -49,7 +50,7 @@ ENTRY(__mmu_cache_off)
> mov pc, r12
> ENDPROC(__mmu_cache_on)
>
> -.section ".text_bare_init.text"
> +__BARE_INIT
> ENTRY(__mmu_cache_flush)
> mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
> tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
> diff --git a/include/init.h b/include/init.h
> index 8692b68..5a7a5b6 100644
> --- a/include/init.h
> +++ b/include/init.h
> @@ -7,6 +7,10 @@
> #define __init
> #define __initdata
>
> +/* For assembly routines */
> +#define __BARE_INIT .section ".text_bare_init.text"
Is there a reason you used capital letters for __BARE_INIT in assembly?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text"
2010-09-16 10:56 ` [PATCH] " Sascha Hauer
@ 2010-09-16 11:12 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 5+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-09-16 11:12 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
> > --- a/include/init.h
> > +++ b/include/init.h
> > @@ -7,6 +7,10 @@
> > #define __init
> > #define __initdata
> >
> > +/* For assembly routines */
> > +#define __BARE_INIT .section ".text_bare_init.text"
>
> Is there a reason you used capital letters for __BARE_INIT in assembly?
same way as the kernel for assembly we use upercase
cf __INIT __INITDATA
Best Regards,
J.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2010-09-16 11:13 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-09-05 16:41 [PATCH] init: introduce __BARE_INIT for .section ".text_bare_init.text" Jean-Christophe PLAGNIOL-VILLARD
2010-09-05 17:12 ` Sam Ravnborg
2010-09-12 11:30 ` [PATCH v2] " Jean-Christophe PLAGNIOL-VILLARD
2010-09-16 10:56 ` [PATCH] " Sascha Hauer
2010-09-16 11:12 ` Jean-Christophe PLAGNIOL-VILLARD
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox