* [PATCH 4/6] omap3: Add DPLL tables for silicon rev 1 and 2
2010-12-30 13:49 [PATCH 1/6] omap3: Add macros to extract hawkeye and version Sanjeev Premi
2010-12-30 13:49 ` [PATCH 2/6] omap3: Detect cpu based on hawkeye Sanjeev Premi
2010-12-30 13:49 ` [PATCH 3/6] omap3: Update method to detect si revision Sanjeev Premi
@ 2010-12-30 13:49 ` Sanjeev Premi
2010-12-30 13:49 ` [PATCH 5/6] omap3: Define separate functions for DPLL configuration Sanjeev Premi
2010-12-30 13:49 ` [PATCH 6/6] omap3: Select DPLL tables based on cpu revision Sanjeev Premi
4 siblings, 0 replies; 6+ messages in thread
From: Sanjeev Premi @ 2010-12-30 13:49 UTC (permalink / raw)
To: barebox
This patch adds DPLL tables for OMAP34xx ES1.0 and ES2.0.
When more than one table is added, the get_xxx_dpll_param()
was updated to use the tables corresponding to ES2.0 to
ensure that current functionality doesn't break.
In addition, the tables have been reformatted for better
readability.
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
arch/arm/mach-omap/omap3_clock_core.S | 144 ++++++++++++++-------------------
1 files changed, 62 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index 872ae5a..207d43a 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -205,106 +205,86 @@ pll_div_val5:
/* the literal pools origin */
.ltorg
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param
- * struct(omap3_clock.c). MAX index is as per omap3_clock.h
+/* MPU DPLL Parameter table
+ *
+ * This table defines the DPLL parameter table for the MPU as defined by
+ * "struct dpll_param defined" in "omap3-clock.h"
+ *
+ * The tables are defined for separately each silicon revision.
*/
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES2 */
-.word 0x0FA,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES2 */
-.word 0x1F4,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES2 */
-.word 0x271,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES2 */
-.word 0x0FA,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES2 */
-.word 0x271,0x2F,0x03,0x01
+.globl mpu_dpll_param_es1
+mpu_dpll_param_es1:
+/* M N FREQSEL M2 */
+.word 0x0FE, 0x07, 0x05, 0x01 /* 12 MHz */
+.word 0x17D, 0x0C, 0x03, 0x01 /* 13 MHz */
+.word 0x179, 0x12, 0x04, 0x01 /* 19.2 MHz */
+.word 0x17D, 0x19, 0x03, 0x01 /* 26 MHz */
+.word 0x1FA, 0x32, 0x03, 0x01 /* 38.4 MHz */
+
+.globl mpu_dpll_param_es2
+mpu_dpll_param_es2:
+/* M N FREQSEL M2 */
+.word 0x0FA, 0x05, 0x07, 0x01 /* 12 MHz */
+.word 0x1F4, 0x0C, 0x03, 0x01 /* 13 MHz */
+.word 0x271, 0x17, 0x03, 0x01 /* 19.2 MHz */
+.word 0x0FA, 0x0C, 0x07, 0x01 /* 26 MHz */
+.word 0x271, 0x2F, 0x03, 0x01 /* 38.4 MHz */
.globl get_mpu_dpll_param
get_mpu_dpll_param:
- adr r0, mpu_dpll_param
+ adr r0, mpu_dpll_param_es2
mov pc, lr
-iva_dpll_param:
-/* 12MHz */
-/* ES2 */
-.word 0x0B4,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES2 */
-.word 0x168,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES2 */
-.word 0x0E1,0x0B,0x06,0x01
-
-/* 26MHz */
-/* ES2 */
-.word 0x0B4,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES2 */
-.word 0x0E1,0x17,0x06,0x01
+iva_dpll_param_es1:
+/* M N FREQSEL M2 */
+.word 0x07D, 0x05, 0x07, 0x01 /* 12 MHz */
+.word 0x0FA, 0x0C, 0x03, 0x01 /* 13 MHz */
+.word 0x082, 0x09, 0x07, 0x01 /* 19.2 MHz */
+.word 0x07D, 0x0C, 0x07, 0x01 /* 26 MHz */
+.word 0x13F, 0x30, 0x03, 0x01 /* 38.4 MHz */
+
+iva_dpll_param_es2:
+/* M N FREQSEL M2 */
+.word 0x0B4, 0x05, 0x07, 0x01 /* 12 MHz */
+.word 0x168, 0x0C, 0x03, 0x01 /* 13 MHz */
+.word 0x0E1, 0x0B, 0x06, 0x01 /* 19.2 MHz */
+.word 0x0B4, 0x0C, 0x07, 0x01 /* 26 MHz */
+.word 0x0E1, 0x17, 0x06, 0x01 /* 38.4 MHz */
.globl get_iva_dpll_param
get_iva_dpll_param:
- adr r0, iva_dpll_param
+ adr r0, iva_dpll_param_es2
mov pc, lr
-core_dpll_param:
-/* 12MHz */
-/* ES2 */
-.word 0x0A6,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES2 */
-.word 0x14C,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES2 */
-.word 0x19F,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES2 */
-.word 0x0A6,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES2 */
-.word 0x19F,0x2F,0x03,0x01
+core_dpll_param_es1:
+/* M N FREQSEL M2 */
+.word 0x19F, 0x0E, 0x03, 0x01 /* 12 MHz */
+.word 0x1B2, 0x10, 0x03, 0x01 /* 13 MHz */
+.word 0x19F, 0x17, 0x03, 0x01 /* 19.2 MHz */
+.word 0x1B2, 0x21, 0x03, 0x01 /* 26 MHz */
+.word 0x19F, 0x2F, 0x03, 0x01 /* 38.4 MHz */
+
+core_dpll_param_es2:
+/* M N FREQSEL M2 */
+.word 0x0A6, 0x05, 0x07, 0x01 /* 12 MHz */
+.word 0x14C, 0x0C, 0x03, 0x01 /* 13 MHz */
+.word 0x19F, 0x17, 0x03, 0x01 /* 19.2 MHz */
+.word 0x0A6, 0x0C, 0x07, 0x01 /* 26 MHz */
+.word 0x19F, 0x2F, 0x03, 0x01 /* 38.4 MHz */
.globl get_core_dpll_param
get_core_dpll_param:
- adr r0, core_dpll_param
+ adr r0, core_dpll_param_es2
mov pc, lr
/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
-/* 12MHz */
-.word 0xD8,0x05,0x07,0x09
-
-/* 13MHz */
-.word 0x1B0,0x0C,0x03,0x09
-
-/* 19.2MHz */
-.word 0xE1,0x09,0x07,0x09
-
-/* 26MHz */
-.word 0xD8,0x0C,0x07,0x09
-
-/* 38.4MHz */
-.word 0xE1,0x13,0x07,0x09
+/* M N FREQSEL M2 */
+.word 0x0D8, 0x05, 0x07, 0x09 /* 12 MHz */
+.word 0x1B0, 0x0C, 0x03, 0x09 /* 13 MHz */
+.word 0x0E1, 0x09, 0x07, 0x09 /* 19.2 MHz */
+.word 0x0D8, 0x0C, 0x07, 0x09 /* 26 MHz */
+.word 0x0E1, 0x13, 0x07, 0x09 /* 38.4 MHz */
.globl get_per_dpll_param
get_per_dpll_param:
--
1.7.2.2
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5/6] omap3: Define separate functions for DPLL configuration
2010-12-30 13:49 [PATCH 1/6] omap3: Add macros to extract hawkeye and version Sanjeev Premi
` (2 preceding siblings ...)
2010-12-30 13:49 ` [PATCH 4/6] omap3: Add DPLL tables for silicon rev 1 and 2 Sanjeev Premi
@ 2010-12-30 13:49 ` Sanjeev Premi
2010-12-30 13:49 ` [PATCH 6/6] omap3: Select DPLL tables based on cpu revision Sanjeev Premi
4 siblings, 0 replies; 6+ messages in thread
From: Sanjeev Premi @ 2010-12-30 13:49 UTC (permalink / raw)
To: barebox
Content from monolith implementation in prcm_init() has been
moved into separate functions - per clock domain. This makes
code easy to adapt for silicon revisions and families.
Few cosmetic changes may have been done during this movement.
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
arch/arm/mach-omap/omap3_clock.c | 319 +++++++++++++++++++++++++-------------
1 files changed, 210 insertions(+), 109 deletions(-)
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 13e8729..ff99b2c 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -137,89 +137,87 @@ static void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
}
/**
- * @brief Inits clocks for PRCM
+ * @brief Initialize CORE DPLL for OMAP34x
*
- * This is called from SRAM, or Flash (using temp SRAM stack).
- * if CONFIG_OMAP3_COPY_CLOCK_SRAM is defined, @ref go_to_speed
- *
- * @return void
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
*/
-void prcm_init(void)
+static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
{
- int xip_safe;
- u32 osc_clk = 0, sys_clkin_sel = 0;
- u32 clk_index, sil_index = 0;
- struct dpll_param *dpll_param_p;
+ struct dpll_param *dp = get_core_dpll_param();
#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
int p0, p1, p2, p3;
- f_lock_pll = (void *)(OMAP_SRAM_INTVECT + OMAP_SRAM_INTVECT_COPYSIZE);
#endif
- xip_safe = running_in_sram();
+ dp += clk_sel;
- /* Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
- /* set input crystal speed */
- sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
- /* input clock divider */
- sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
- clk_index = sys_clkin_sel / 2;
- } else {
- /* input clock divider */
- sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 1);
- clk_index = sys_clkin_sel;
- }
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
-
- /* Getting the base address of Core DPLL param table */
- dpll_param_p = (struct dpll_param *)get_core_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX * clk_index + sil_index;
- if (xip_safe) {
- /* CORE DPLL */
- /* sr32(CM_REG(CLKSEL2_EMU)) set override to work when asleep */
+ if (running_in_sram()) {
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_CKGEN), LDELAY);
- /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
- work. write another value and then default value. */
+
+ /*
+ * OMAP3430 ES1.0 Errata 1.50
+ * Writing default value doesn't work. First write a different
+ * value and then write the default value.
+ */
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2 + 1);
sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
- sr32(CM_REG(CLKSEL1_PLL), 27, 2, dpll_param_p->m2);
- sr32(CM_REG(CLKSEL1_PLL), 16, 11, dpll_param_p->m);
- sr32(CM_REG(CLKSEL1_PLL), 8, 7, dpll_param_p->n);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_REG(CLKSEL1_PLL), 27, 2, dp->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
+
+ /* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(CM_REG(CLKSEL1_PLL), 6, 1, 0);
+
sr32(CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV);
sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
- sr32(CM_REG(CLKEN_PLL), 4, 4, dpll_param_p->fsel);
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
+
+ /* Lock Mode */
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_CKGEN), LDELAY);
} else if (running_in_flash()) {
#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
- /* if running from flash,
- * jump to small relocated code area in SRAM.
+ f_lock_pll = (void *)(OMAP_SRAM_INTVECT +
+ OMAP_SRAM_INTVECT_COPYSIZE);
+
+ /*
+ * Jump to small relocated code area in SRAM.
*/
p0 = readl(CM_REG(CLKEN_PLL));
sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
- sr32((u32) &p0, 4, 4, dpll_param_p->fsel);
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32((u32) &p0, 4, 4, dp->fsel);
p1 = readl(CM_REG(CLKSEL1_PLL));
- sr32((u32) &p1, 27, 2, dpll_param_p->m2);
- sr32((u32) &p1, 16, 11, dpll_param_p->m);
- sr32((u32) &p1, 8, 7, dpll_param_p->n);
- sr32((u32) &p1, 6, 1, 0); /* set source for 96M */
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32((u32) &p1, 27, 2, dp->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32((u32) &p1, 16, 11, dp->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32((u32) &p1, 8, 7, dp->n);
+
+ /* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32((u32) &p1, 6, 1, 0);
+
p2 = readl(CM_REG(CLKSEL_CORE));
sr32((u32) &p2, 8, 4, CORE_SSI_DIV);
sr32((u32) &p2, 4, 2, CORE_FUSB_DIV);
@@ -234,70 +232,173 @@ void prcm_init(void)
hang();
#endif
}
+}
+
+/**
+ * @brief Initialize PER DPLL for OMAP34x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_per_dpll_34x(u32 cpu_rev, u32 clk_sel)
+{
+ struct dpll_param *dp = get_per_dpll_param();
+
+ dp += clk_sel;
+
+ /*
+ * OMAP3430 ES1.0 Errata 1.50
+ * Writing default value doesn't work. First write a different
+ * value and then write the default value.
+ */
- /* PER DPLL */
sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
wait_on_value((0x1 << 1), 0, CM_REG(IDLEST_CKGEN), LDELAY);
- /* Getting the base address to PER DPLL param table */
- /* Set N */
- dpll_param_p = (struct dpll_param *)get_per_dpll_param();
- /* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
- /* Errata 1.50 Workaround for 3430 ES1.0 only */
- /* If using default divisors, write default divisor + 1
- and then the actual divisor value */
- /* Need to change it to silicon and revisino check */
- if (1) {
- sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2 + 1); /* set M6 */
- sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2 + 1); /* set M5 */
- sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2 + 1); /* set M4 */
- sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2 + 1); /* set M3 */
- sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2); /* set M3 */
- /* set M2 */
- sr32(CM_REG(CLKSEL3_PLL), 0, 5, dpll_param_p->m2 + 1);
- sr32(CM_REG(CLKSEL3_PLL), 0, 5, dpll_param_p->m2);
- } else {
- sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2); /* set M3 */
- sr32(CM_REG(CLKSEL3_PLL), 0, 5, dpll_param_p->m2);
- }
- sr32(CM_REG(CLKSEL2_PLL), 8, 11, dpll_param_p->m); /* set m */
- sr32(CM_REG(CLKSEL2_PLL), 0, 7, dpll_param_p->n); /* set n */
- sr32(CM_REG(CLKEN_PLL), 20, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK); /* lock mode */
+ /* Set M6 */
+ sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2 + 1);
+ sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2);
+
+ /* Set M5 */
+ sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2 + 1);
+ sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2);
+
+ /* Set M4 */
+ sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2 + 1);
+ sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2);
+
+ /* Set M3 */
+ sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2 + 1);
+ sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2);
+
+ /* Set M2 */
+ sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2 + 1);
+ sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+ sr32(CM_REG(CLKSEL2_PLL), 8, 11, dp->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
+
+ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+ sr32(CM_REG(CLKEN_PLL), 20, 4, dp->fsel);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
wait_on_value((0x1 << 1), 2, CM_REG(IDLEST_CKGEN), LDELAY);
+}
- /* Getting the base address to MPU DPLL param table */
- dpll_param_p = (struct dpll_param *)get_mpu_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX * clk_index + sil_index;
- /* MPU DPLL (unlocked already) */
- sr32(CM_REG(CLKSEL2_PLL_MPU), 0, 5, dpll_param_p->m2); /* Set M2 */
- sr32(CM_REG(CLKSEL1_PLL_MPU), 8, 11, dpll_param_p->m); /* Set M */
- sr32(CM_REG(CLKSEL1_PLL_MPU), 0, 7, dpll_param_p->n); /* Set N */
- sr32(CM_REG(CLKEN_PLL_MPU), 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_MPU), LDELAY);
+/**
+ * @brief Initialize MPU DPLL for OMAP34x
+ *
+ * The MPU DPLL is already unlocked when control reaches here. This
+ * function doesn't lock the DPLL either - defers to the caller.
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_mpu_dpll_34x(u32 cpu_rev, u32 clk_sel)
+{
+ struct dpll_param *dp = get_mpu_dpll_param();
+
+ dp += clk_sel;
+
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
+
+ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+ sr32(CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
+}
+
+/**
+ * @brief Initialize IVA DPLL for OMAP34x
+ *
+ * @param[in] cpu_rev - Silicon revision
+ * @param[in] clk_sel - Clock selection used as index into the dpll table
+ */
+static void init_iva_dpll_34x(u32 cpu_rev, u32 clk_sel)
+{
+ struct dpll_param *dp = get_iva_dpll_param();
- /* Getting the base address to IVA DPLL param table */
- dpll_param_p = (struct dpll_param *)get_iva_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX * clk_index + sil_index;
- /* IVA DPLL (set to 12*20=240MHz) */
+ dp += clk_sel;
+
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_IVA2), LDELAY);
- sr32(CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dpll_param_p->m); /* set M */
- sr32(CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dpll_param_p->n); /* set N */
- sr32(CM_REG(CLKEN_PLL_IVA2), 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK); /* lock mode */
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ sr32(CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
+
+ /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_IVA2), LDELAY);
+}
+
+/**
+ * @brief Inits clocks for PRCM
+ *
+ * This is called from SRAM, or Flash (using temp SRAM stack).
+ * if CONFIG_OMAP3_COPY_CLOCK_SRAM is defined, @ref go_to_speed
+ *
+ * @return void
+ */
+void prcm_init(void)
+{
+ u32 osc_clk = 0, sys_clkin_sel = 0;
+ u32 cpu_rev = get_cpu_rev();
+ u32 clk_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+ /* set input crystal speed */
+ sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if (sys_clkin_sel > 2) {
+ /* input clock divider */
+ sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
+ clk_index = sys_clkin_sel / 2;
+ } else {
+ /* input clock divider */
+ sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 1);
+ clk_index = sys_clkin_sel;
+ }
+
+ /*
+ * Unlock the MPU PLL. Run slow while clocks are being configured.
+ */
+ sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
+
+ init_core_dpll_34x(cpu_rev, clk_index);
+ init_per_dpll_34x(cpu_rev, clk_index);
+ init_mpu_dpll_34x(cpu_rev, clk_index);
+ init_iva_dpll_34x(cpu_rev, clk_index);
+
+ /*
+ * Clock configuration complete. Lock MPU PLL.
+ */
+ sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOCK);
+ wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_MPU), LDELAY);
/* Set up GPTimers to sys_clk source only */
sr32(CM_REG(CLKSEL_PER), 0, 8, 0xff);
--
1.7.2.2
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 6/6] omap3: Select DPLL tables based on cpu revision
2010-12-30 13:49 [PATCH 1/6] omap3: Add macros to extract hawkeye and version Sanjeev Premi
` (3 preceding siblings ...)
2010-12-30 13:49 ` [PATCH 5/6] omap3: Define separate functions for DPLL configuration Sanjeev Premi
@ 2010-12-30 13:49 ` Sanjeev Premi
4 siblings, 0 replies; 6+ messages in thread
From: Sanjeev Premi @ 2010-12-30 13:49 UTC (permalink / raw)
To: barebox
This patch updates the DPLL functions to return correct
DPLL table based on the cpu revision.
The DPLL table for PER domain is same across all revisions,
but the function signature has been updated to maintain
consistency in the API definition.
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
arch/arm/mach-omap/include/mach/omap3-clock.h | 8 ++--
arch/arm/mach-omap/omap3_clock.c | 8 ++--
arch/arm/mach-omap/omap3_clock_core.S | 58 ++++++++++++++++++++++---
3 files changed, 60 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index b655fe3..1b42500 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -125,10 +125,10 @@ struct dpll_param {
unsigned int m2;
};
/* External functions see omap3_clock_core.S */
-extern struct dpll_param *get_mpu_dpll_param(void);
-extern struct dpll_param *get_iva_dpll_param(void);
-extern struct dpll_param *get_core_dpll_param(void);
-extern struct dpll_param *get_per_dpll_param(void);
+extern struct dpll_param *get_mpu_dpll_param(u32);
+extern struct dpll_param *get_iva_dpll_param(u32);
+extern struct dpll_param *get_core_dpll_param(u32);
+extern struct dpll_param *get_per_dpll_param(u32);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index ff99b2c..dad4ed1 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -144,7 +144,7 @@ static void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
*/
static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
{
- struct dpll_param *dp = get_core_dpll_param();
+ struct dpll_param *dp = get_core_dpll_param(cpu_rev);
#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
int p0, p1, p2, p3;
#endif
@@ -242,7 +242,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
*/
static void init_per_dpll_34x(u32 cpu_rev, u32 clk_sel)
{
- struct dpll_param *dp = get_per_dpll_param();
+ struct dpll_param *dp = get_per_dpll_param(cpu_rev);
dp += clk_sel;
@@ -300,7 +300,7 @@ static void init_per_dpll_34x(u32 cpu_rev, u32 clk_sel)
*/
static void init_mpu_dpll_34x(u32 cpu_rev, u32 clk_sel)
{
- struct dpll_param *dp = get_mpu_dpll_param();
+ struct dpll_param *dp = get_mpu_dpll_param(cpu_rev);
dp += clk_sel;
@@ -325,7 +325,7 @@ static void init_mpu_dpll_34x(u32 cpu_rev, u32 clk_sel)
*/
static void init_iva_dpll_34x(u32 cpu_rev, u32 clk_sel)
{
- struct dpll_param *dp = get_iva_dpll_param();
+ struct dpll_param *dp = get_iva_dpll_param(cpu_rev);
dp += clk_sel;
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index 207d43a..f28069a 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -230,10 +230,23 @@ mpu_dpll_param_es2:
.word 0x0FA, 0x0C, 0x07, 0x01 /* 26 MHz */
.word 0x271, 0x2F, 0x03, 0x01 /* 38.4 MHz */
+/**
+ * @brief Get address of MPU DPLL param table.
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
.globl get_mpu_dpll_param
get_mpu_dpll_param:
- adr r0, mpu_dpll_param_es2
- mov pc, lr
+ mov r3, r0
+ lsl r3, r3, #16 /* Isolate silicon revision */
+ lsr r3, r3, #16
+ cmp r3, #0 /* Revision 1 ? */
+ adr r0, mpu_dpll_param_es1
+ bxeq lr
+ adr r0, mpu_dpll_param_es2
+ mov pc, lr
iva_dpll_param_es1:
/* M N FREQSEL M2 */
@@ -251,10 +264,23 @@ iva_dpll_param_es2:
.word 0x0B4, 0x0C, 0x07, 0x01 /* 26 MHz */
.word 0x0E1, 0x17, 0x06, 0x01 /* 38.4 MHz */
+/**
+ * @brief Get address of IVA DPLL param table.
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
.globl get_iva_dpll_param
get_iva_dpll_param:
- adr r0, iva_dpll_param_es2
- mov pc, lr
+ mov r3, r0
+ lsl r3, r3, #16 /* Isolate silicon revision */
+ lsr r3, r3, #16
+ cmp r3, #0 /* Revision 1 ? */
+ adr r0, iva_dpll_param_es1
+ bxeq lr
+ adr r0, iva_dpll_param_es2
+ mov pc, lr
core_dpll_param_es1:
/* M N FREQSEL M2 */
@@ -272,10 +298,23 @@ core_dpll_param_es2:
.word 0x0A6, 0x0C, 0x07, 0x01 /* 26 MHz */
.word 0x19F, 0x2F, 0x03, 0x01 /* 38.4 MHz */
+/**
+ * @brief Get address of CORE DPLL param table.
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
.globl get_core_dpll_param
get_core_dpll_param:
- adr r0, core_dpll_param_es2
- mov pc, lr
+ mov r3, r0
+ lsl r3, r3, #16 /* Isolate silicon revision */
+ lsr r3, r3, #16
+ cmp r3, #0 /* Revision 1 ? */
+ adr r0, core_dpll_param_es1
+ bxeq lr
+ adr r0, core_dpll_param_es2
+ mov pc, lr
/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
@@ -286,6 +325,13 @@ per_dpll_param:
.word 0x0D8, 0x0C, 0x07, 0x09 /* 26 MHz */
.word 0x0E1, 0x13, 0x07, 0x09 /* 38.4 MHz */
+/**
+ * @brief Get address of PER DPLL param table.
+ *
+ * @param rev Silicon revision (not used).
+ *
+ * @return Address of the param table
+ */
.globl get_per_dpll_param
get_per_dpll_param:
adr r0, per_dpll_param
--
1.7.2.2
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^ permalink raw reply [flat|nested] 6+ messages in thread