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From: Sanjeev Premi <premi@ti.com>
To: barebox@lists.infradead.org
Subject: [PATCH 4/8] omap36x: Add DPLL tables and functions to access them
Date: Mon,  3 Jan 2011 19:54:51 +0530	[thread overview]
Message-ID: <1294064695-10865-5-git-send-email-premi@ti.com> (raw)
In-Reply-To: <1294064695-10865-1-git-send-email-premi@ti.com>

This patch adds the DPLL tables for OMAP36XX and the
necessary functions to access these tables.

Both definitions follow the conventions used for
OMAP34XX.

All tables, currently, correspond to SYSCLK at 26MHz.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    4 +
 arch/arm/mach-omap/omap3_clock_core.S         |   88 +++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index aa420f8..b9e2714 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -142,6 +142,10 @@ extern struct dpll_param *get_iva_dpll_param_34x(u32);
 extern struct dpll_param *get_core_dpll_param_34x(u32);
 extern struct dpll_param *get_per_dpll_param_34x(u32);
 
+extern struct dpll_param *get_mpu_dpll_param_36x(u32);
+extern struct dpll_param *get_iva_dpll_param_36x(u32);
+extern struct dpll_param *get_core_dpll_param_36x(u32);
+extern struct dpll_param_per_36x *get_per_dpll_param_36x(u32);
 #endif /* __ASSEMBLY__ */
 
 #endif  /* endif _OMAP343X_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index 5a1f068..eb13c2f 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -336,3 +336,91 @@ per_dpll_param_34x:
 get_per_dpll_param_34x:
 	adr r0, per_dpll_param_34x
 	mov pc, lr
+
+.globl mpu_dpll_param_36x
+mpu_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 12   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 13   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 26   MHz	*/
+.word	0x12C,	0x0C,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of MPU DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_mpu_dpll_param_36x
+get_mpu_dpll_param_36x:
+	adr r0, mpu_dpll_param_36x
+	mov pc, lr
+
+.globl iva_dpll_param_36x
+iva_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 12   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 13   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 26   MHz	*/
+.word	0x00A,	0x00,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of IVA DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_iva_dpll_param_36x
+get_iva_dpll_param_36x:
+	adr r0, iva_dpll_param_36x
+	mov pc, lr
+
+.globl core_dpll_param_36x
+core_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*    	M	N	FREQSEL	M2	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 12   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 13   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 19.2 MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 26   MHz	*/
+.word	0x0C8,	0x0C,	0x00,	0x01		/* 38.4 MHz	*/
+
+/**
+ * @brief Get address of IVA DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_core_dpll_param_36x
+get_core_dpll_param_36x:
+	adr r0, core_dpll_param_36x
+	mov pc, lr
+
+.globl per_dpll_param_36x
+per_dpll_param_36x:
+/* FIXME: All values correspond to 26MHz only */
+/*	M	N	M2	M3	M4	M5	M6	m2DIV */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 12   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 13   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 19.2 MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 26   MHz */
+.word	0x1B0,	0x0C,	9,	0x10,	9,	4,	3,	1 /* 38.4 MHz */
+
+/**
+ * @brief Get address of PER DPLL param table (OMAP36XX).
+ *
+ * @param rev Silicon revision.
+ *
+ * @return Address of the param table
+ */
+.globl get_per_dpll_param_36x
+get_per_dpll_param_36x:
+	adr r0, per_dpll_param_36x
+	mov pc, lr
-- 
1.7.2.2


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  parent reply	other threads:[~2011-01-03 14:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-03 14:24 [PATCH 0/8] omap36x: Add basic support Sanjeev Premi
2011-01-03 14:24 ` [PATCH 1/8] omap36x: Add support for dynamic detection Sanjeev Premi
2011-01-03 14:24 ` [PATCH 2/8] omap36x: Detect silicon revisions Sanjeev Premi
2011-01-03 14:24 ` [PATCH 3/8] omap36x: Define structure for PER DPLL Sanjeev Premi
2011-01-03 14:24 ` Sanjeev Premi [this message]
2011-01-03 14:24 ` [PATCH 5/8] omap36x: Define per domain functions for DPLL configuration Sanjeev Premi
2011-01-03 14:24 ` [PATCH 6/8] omap36x: Perform basic clock initialization Sanjeev Premi
2011-01-03 14:24 ` [PATCH 7/8] omap3: Avoid sudden change to SYS_CLK divider Sanjeev Premi
2011-01-03 14:24 ` [PATCH 8/8] omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx Sanjeev Premi

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