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From: Sanjeev Premi <premi@ti.com>
To: barebox@lists.infradead.org
Subject: [PATCH 6/8] omap36x: Perform basic clock initialization
Date: Mon,  3 Jan 2011 19:54:53 +0530	[thread overview]
Message-ID: <1294064695-10865-7-git-send-email-premi@ti.com> (raw)
In-Reply-To: <1294064695-10865-1-git-send-email-premi@ti.com>

This patch adds the basic clock initizlization for OMAP36XX.

Portion of this patch is based on commit:
    29587220909e639cda4fb5a35cb5bf33aba242b9
    at http://arago-project.org/git/projects/?p=x-load-omap3.git

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/omap3_clock.c |   32 ++++++++++++++++++++++++++------
 1 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 492e309..1668369 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -554,6 +554,7 @@ static void init_iva_dpll_36x(u32 cpu_rev, u32 clk_sel)
 void prcm_init(void)
 {
 	u32 osc_clk = 0, sys_clkin_sel = 0;
+	u32 cpu_type = get_cpu_type();
 	u32 cpu_rev = get_cpu_rev();
 	u32 clk_index;
 
@@ -565,8 +566,15 @@ void prcm_init(void)
 	/* set input crystal speed */
 	sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
 
-	/* If the input clock is greater than 19.2M always divide/2 */
-	if (sys_clkin_sel > 2) {
+	/*
+	 * OMAP3430:
+	 *	If the input clock is greater than 19.2M always divide/2
+	 * OMAP3630:
+	 *	DDR corruption was observed on exit from OFF mode, when
+	 *	sys clock is lower than 26M. As workaround, it is maintained
+	 *	at 26M.
+	 */
+	if ((cpu_type != CPU_3630) && (sys_clkin_sel > 2)) {
 		/* input clock divider */
 		sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
 		clk_index = sys_clkin_sel / 2;
@@ -582,10 +590,22 @@ void prcm_init(void)
 	sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
 	wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
 
-	init_core_dpll_34x(cpu_rev, clk_index);
-	init_per_dpll_34x(cpu_rev, clk_index);
-	init_mpu_dpll_34x(cpu_rev, clk_index);
-	init_iva_dpll_34x(cpu_rev, clk_index);
+	if (cpu_type == CPU_3430) {
+		init_core_dpll_34x(cpu_rev, clk_index);
+		init_per_dpll_34x(cpu_rev, clk_index);
+		init_mpu_dpll_34x(cpu_rev, clk_index);
+		init_iva_dpll_34x(cpu_rev, clk_index);
+	}
+	else if (cpu_type == CPU_3630) {
+		init_core_dpll_36x(cpu_rev, clk_index);
+		init_per_dpll_36x(cpu_rev, clk_index);
+		init_mpu_dpll_36x(cpu_rev, clk_index);
+		init_iva_dpll_36x(cpu_rev, clk_index);
+	}
+	else {
+		/* Unknown CPU */
+		hang();
+	}
 
 	/*
 	 * Clock configuration complete. Lock MPU PLL.
-- 
1.7.2.2


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  parent reply	other threads:[~2011-01-03 14:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-03 14:24 [PATCH 0/8] omap36x: Add basic support Sanjeev Premi
2011-01-03 14:24 ` [PATCH 1/8] omap36x: Add support for dynamic detection Sanjeev Premi
2011-01-03 14:24 ` [PATCH 2/8] omap36x: Detect silicon revisions Sanjeev Premi
2011-01-03 14:24 ` [PATCH 3/8] omap36x: Define structure for PER DPLL Sanjeev Premi
2011-01-03 14:24 ` [PATCH 4/8] omap36x: Add DPLL tables and functions to access them Sanjeev Premi
2011-01-03 14:24 ` [PATCH 5/8] omap36x: Define per domain functions for DPLL configuration Sanjeev Premi
2011-01-03 14:24 ` Sanjeev Premi [this message]
2011-01-03 14:24 ` [PATCH 7/8] omap3: Avoid sudden change to SYS_CLK divider Sanjeev Premi
2011-01-03 14:24 ` [PATCH 8/8] omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx Sanjeev Premi

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