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From: Sanjeev Premi <premi@ti.com>
To: barebox@lists.infradead.org
Subject: [PATCH 7/8] omap3: Avoid sudden change to SYS_CLK divider
Date: Mon,  3 Jan 2011 19:54:54 +0530	[thread overview]
Message-ID: <1294064695-10865-8-git-send-email-premi@ti.com> (raw)
In-Reply-To: <1294064695-10865-1-git-send-email-premi@ti.com>

In function get_osc_clk_speed(), the SYS_CLK divider
was being changed 'suddenly'.

This change has cascading effect on the derived clocks,
leading to inconsistent behavior - often a crash.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    6 ++++++
 arch/arm/mach-omap/omap3_clock.c              |   19 +++++++++++++++----
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index b9e2714..cccb0da 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -92,6 +92,12 @@
 #define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
 #define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
 
+/*
+ * Bit positions indicating current SYSCLK divider
+ */
+#define SYSCLK_DIV_1		(1 << 6)
+#define SYSCLK_DIV_2		(1 << 7)
+
 /* The following configurations are OPP and SysClk value independant
  * and hence are defined here.
  */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 1668369..16cbae9 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -65,12 +65,20 @@ static void per_clocks_enable(void);
  */
 static u32 get_osc_clk_speed(void)
 {
-	u32 start, cstart, cend, cdiff, val;
+	u32 start, cstart, cend, cdiff, cdiv, val;
 
 	val = readl(PRM_REG(CLKSRC_CTRL));
-	/* If SYS_CLK is being divided by 2, remove for now */
-	val = (val & (~(0x1 << 7))) | (0x1 << 6);
-	writel(val, PRM_REG(CLKSRC_CTRL));
+
+	if (val & SYSCLK_DIV_2)
+		cdiv = 2;
+	else if (val & SYSCLK_DIV_1)
+		cdiv = 1;
+	else
+		/*
+		 * Should never reach here!
+		 * To proceed, assume divider as 1.
+		 */
+		cdiv = 1;
 
 	/* enable timer2 */
 	val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
@@ -97,6 +105,9 @@ static u32 get_osc_clk_speed(void)
 	cend = readl(OMAP_GPTIMER1_BASE + TCRR);
 	cdiff = cend - cstart;	/* get elapsed ticks */
 
+	if (cdiv == 2)
+		cdiff *= 2;
+
 	/* based on number of ticks assign speed */
 	if (cdiff > 19000)
 		return S38_4M;
-- 
1.7.2.2


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  parent reply	other threads:[~2011-01-03 14:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-03 14:24 [PATCH 0/8] omap36x: Add basic support Sanjeev Premi
2011-01-03 14:24 ` [PATCH 1/8] omap36x: Add support for dynamic detection Sanjeev Premi
2011-01-03 14:24 ` [PATCH 2/8] omap36x: Detect silicon revisions Sanjeev Premi
2011-01-03 14:24 ` [PATCH 3/8] omap36x: Define structure for PER DPLL Sanjeev Premi
2011-01-03 14:24 ` [PATCH 4/8] omap36x: Add DPLL tables and functions to access them Sanjeev Premi
2011-01-03 14:24 ` [PATCH 5/8] omap36x: Define per domain functions for DPLL configuration Sanjeev Premi
2011-01-03 14:24 ` [PATCH 6/8] omap36x: Perform basic clock initialization Sanjeev Premi
2011-01-03 14:24 ` Sanjeev Premi [this message]
2011-01-03 14:24 ` [PATCH 8/8] omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx Sanjeev Premi

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