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From: Sanjeev Premi <premi@ti.com>
To: barebox@lists.infradead.org
Subject: [PATCH 8/8] omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx
Date: Mon,  3 Jan 2011 19:54:55 +0530	[thread overview]
Message-ID: <1294064695-10865-9-git-send-email-premi@ti.com> (raw)
In-Reply-To: <1294064695-10865-1-git-send-email-premi@ti.com>

This patch updates the clock dividers for the graphics
processor.

It is based on commit:
    c4e1d9b718b65436e30422506f43fa4eb21069d3
    at http://arago-project.org/git/projects/?p=u-boot-omap3.git

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/mach-omap/include/mach/omap3-clock.h |    3 ++-
 arch/arm/mach-omap/omap3_clock.c              |    2 +-
 arch/arm/mach-omap/omap3_clock_core.S         |    2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index cccb0da..10566e1 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -108,7 +108,8 @@
 #define CORE_FUSB_DIV		2        /* 41.5MHz: */
 #define CORE_L4_DIV		2        /*  83MHz : L4 */
 #define CORE_L3_DIV		2        /* 166MHz : L3 {DDR} */
-#define GFX_DIV			2        /*  83MHz : CM_CLKSEL_GFX */
+#define GFX_DIV_34X		3        /*  96MHz : CM_CLKSEL_GFX (OMAP34XX) */
+#define GFX_DIV_36X		5        /* 200MHz : CM_CLKSEL_GFX (OMAP36XX) */
 #define WKUP_RSM		2        /* 41.5MHz: CM_CLKSEL_WKUP */
 
 /* PER DPLL */
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 16cbae9..3a0ab24 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -192,7 +192,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
 		sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
 		sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
 		sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
-		sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV);
+		sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_34X);
 		sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
 
 		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S
index eb13c2f..c8d04bb 100644
--- a/arch/arm/mach-omap/omap3_clock_core.S
+++ b/arch/arm/mach-omap/omap3_clock_core.S
@@ -194,7 +194,7 @@ pll_div_val3:
 pll_div_add4:
     .word CM_CLKSEL_GFX
 pll_div_val4:
-    .word (GFX_DIV << 0)
+    .word GFX_DIV_34X
 pll_div_add5:
     .word CM_CLKSEL1_EMU
 pll_div_val5:
-- 
1.7.2.2


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      parent reply	other threads:[~2011-01-03 14:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-03 14:24 [PATCH 0/8] omap36x: Add basic support Sanjeev Premi
2011-01-03 14:24 ` [PATCH 1/8] omap36x: Add support for dynamic detection Sanjeev Premi
2011-01-03 14:24 ` [PATCH 2/8] omap36x: Detect silicon revisions Sanjeev Premi
2011-01-03 14:24 ` [PATCH 3/8] omap36x: Define structure for PER DPLL Sanjeev Premi
2011-01-03 14:24 ` [PATCH 4/8] omap36x: Add DPLL tables and functions to access them Sanjeev Premi
2011-01-03 14:24 ` [PATCH 5/8] omap36x: Define per domain functions for DPLL configuration Sanjeev Premi
2011-01-03 14:24 ` [PATCH 6/8] omap36x: Perform basic clock initialization Sanjeev Premi
2011-01-03 14:24 ` [PATCH 7/8] omap3: Avoid sudden change to SYS_CLK divider Sanjeev Premi
2011-01-03 14:24 ` Sanjeev Premi [this message]

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