* [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally Juergen Beisert
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
The S3Cxxxx family consists of ARMv4, ARMv5 and ARMv6 types of CPU cores. The
S3C24xx sub family is only one of it. To be able to handle all CPUs in one mach
directory, use a more generic name for it.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/Kconfig | 3 +-
arch/arm/Makefile | 2 +-
arch/arm/mach-s3c24xx/Kconfig | 108 -----
arch/arm/mach-s3c24xx/Makefile | 2 -
arch/arm/mach-s3c24xx/generic.c | 297 --------------
arch/arm/mach-s3c24xx/gpio-s3c24x0.c | 169 --------
arch/arm/mach-s3c24xx/include/mach/fb.h | 59 ---
arch/arm/mach-s3c24xx/include/mach/gpio.h | 31 --
arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h | 426 --------------------
arch/arm/mach-s3c24xx/include/mach/mci.h | 46 ---
arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h | 177 --------
arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h | 54 ---
.../mach-s3c24xx/include/mach/s3c24xx-generic.h | 33 --
arch/arm/mach-s3c24xx/lowlevel-init.S | 317 ---------------
arch/arm/mach-samsung/Kconfig | 117 ++++++
arch/arm/mach-samsung/Makefile | 2 +
arch/arm/mach-samsung/generic.c | 297 ++++++++++++++
arch/arm/mach-samsung/gpio-s3c24x0.c | 169 ++++++++
arch/arm/mach-samsung/include/mach/fb.h | 59 +++
arch/arm/mach-samsung/include/mach/gpio.h | 31 ++
arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h | 426 ++++++++++++++++++++
arch/arm/mach-samsung/include/mach/mci.h | 46 +++
arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h | 177 ++++++++
arch/arm/mach-samsung/include/mach/s3c24x0-nand.h | 54 +++
.../mach-samsung/include/mach/s3c24xx-generic.h | 33 ++
arch/arm/mach-samsung/lowlevel-init.S | 317 +++++++++++++++
26 files changed, 1731 insertions(+), 1721 deletions(-)
delete mode 100644 arch/arm/mach-s3c24xx/Kconfig
delete mode 100644 arch/arm/mach-s3c24xx/Makefile
delete mode 100644 arch/arm/mach-s3c24xx/generic.c
delete mode 100644 arch/arm/mach-s3c24xx/gpio-s3c24x0.c
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/fb.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/mci.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
delete mode 100644 arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h
delete mode 100644 arch/arm/mach-s3c24xx/lowlevel-init.S
create mode 100644 arch/arm/mach-samsung/Kconfig
create mode 100644 arch/arm/mach-samsung/Makefile
create mode 100644 arch/arm/mach-samsung/generic.c
create mode 100644 arch/arm/mach-samsung/gpio-s3c24x0.c
create mode 100644 arch/arm/mach-samsung/include/mach/fb.h
create mode 100644 arch/arm/mach-samsung/include/mach/gpio.h
create mode 100644 arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
create mode 100644 arch/arm/mach-samsung/include/mach/mci.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
create mode 100644 arch/arm/mach-samsung/lowlevel-init.S
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40677a3..b600179 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -68,6 +68,7 @@ config ARCH_PXA
config ARCH_S3C24xx
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+ select ARCH_SAMSUNG
select CPU_ARM920T
select GENERIC_GPIO
@@ -86,7 +87,7 @@ source arch/arm/mach-netx/Kconfig
source arch/arm/mach-nomadik/Kconfig
source arch/arm/mach-omap/Kconfig
source arch/arm/mach-pxa/Kconfig
-source arch/arm/mach-s3c24xx/Kconfig
+source arch/arm/mach-samsung/Kconfig
source arch/arm/mach-versatile/Kconfig
config ARM_ASM_UNIFIED
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a3e12e6..0f9bb64 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -52,7 +52,7 @@ machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_PXA) := pxa
-machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
+machine-$(CONFIG_ARCH_SAMSUNG) := samsung
machine-$(CONFIG_ARCH_VERSATILE) := versatile
# Board directory name. This list is sorted alphanumerically
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
deleted file mode 100644
index 80b65fb..0000000
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-if ARCH_S3C24xx
-
-config ARCH_TEXT_BASE
- hex
- default 0x31fc0000
-
-config BOARDINFO
- default "Mini 2440" if MACH_MINI2440
- default "Digi A9M2440" if MACH_A9M2440
- default "Digi A9M2410" if MACH_A9M2410
-
-config CPU_S3C2410
- bool
-
-config CPU_S3C2440
- bool
-
-choice
-
- prompt "S3C24xx Board Type"
-
-config MACH_A9M2410
- bool "Digi A9M2410"
- select CPU_S3C2410
- select MACH_HAS_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
- select S3C24XX_SDRAM_INIT
- help
- Say Y here if you are using Digi's Connect Core 9M equipped
- with a Samsung S3C2410 Processor
-
-config MACH_A9M2440
- bool "Digi A9M2440"
- select CPU_S3C2440
- select MACH_HAS_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
- help
- Say Y here if you are using Digi's Connect Core 9M equipped
- with a Samsung S3C2440 Processor
-
-config MACH_MINI2440
- bool "Mini 2440"
- select CPU_S3C2440
- select MACH_HAS_LOWLEVEL_INIT
- select MACH_DO_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
- select S3C24XX_SDRAM_INIT
- select HAS_DM9000
- help
- Say Y here if you are using Mini 2440 dev board equipped
- with a Samsung S3C2440 Processor
-
-endchoice
-
-menu "Board specific settings "
-
-choice
- prompt "A9M2440 baseboard"
- depends on MACH_A9M2440
-
-config MACH_A9M2410DEV
- bool
- prompt "A9M2410dev"
- select HAS_CS8900
- help
- Digi's evaluation board.
-
-endchoice
-
-source arch/arm/boards/mini2440/Kconfig
-
-endmenu
-
-menu "S3C24X0 Features "
-
-config S3C24XX_LOW_LEVEL_INIT
- bool
-
-config S3C24XX_PLL_INIT
- bool
- prompt "Reconfigure PLL"
- select S3C24XX_LOW_LEVEL_INIT
- help
- This adds generic code to reconfigure the internal PLL very early
- after reset.
-
-config S3C24XX_SDRAM_INIT
- bool
- prompt "Initialize SDRAM"
- select S3C24XX_LOW_LEVEL_INIT
- help
- This adds generic code to configure the SDRAM controller after reset.
- The initialisation will be skipped if the code is already running
- from SDRAM.
-
-config S3C24XX_NAND_BOOT
- bool
- prompt "Booting from NAND"
- select MTD
- select NAND
- select NAND_S3C24X0
- help
- Add generic support to boot from NAND flash. Image loading will be
- skipped if the code is running from NOR or already from SDRAM.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
deleted file mode 100644
index 88d45fe..0000000
--- a/arch/arm/mach-s3c24xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y += generic.o gpio-s3c24x0.o
-obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c
deleted file mode 100644
index d2f2ac7..0000000
--- a/arch/arm/mach-s3c24xx/generic.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/**
- * @file
- * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c24x0-iomap.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_mpllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(MPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_upllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(UPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_fclk(void)
-{
- return s3c24xx_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_hclk(void)
-{
- uint32_t f_clk;
-
- f_clk = s3c24xx_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
- if (readl(CLKDIVN) & 0x02)
- return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
- switch(readl(CLKDIVN) & 0x06) {
- case 2:
- return f_clk >> 1;
- case 4:
- return f_clk >> 2; /* TODO consider CAMDIVN */
- case 6:
- return f_clk / 3; /* TODO consider CAMDIVN */
- }
-#endif
- return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_pclk(void)
-{
- uint32_t p_clk;
-
- p_clk = s3c24xx_get_hclk();
- if (readl(CLKDIVN) & 0x01)
- return p_clk >> 1;
- return p_clk;
-}
-
-/**
- * Calculate the UCLK frequency used by the USB host device
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_uclk(void)
-{
- return s3c24xx_get_upllclk();
-}
-
-/**
- * Calculate the amount of connected and available memory
- * @return Memory size in bytes
- */
-uint32_t s3c24x0_get_memory_size(void)
-{
- uint32_t reg, size;
-
- /*
- * detect the current memory size
- */
- reg = readl(BANKSIZE);
-
- switch (reg & 0x7) {
- case 0:
- size = 32 * 1024 * 1024;
- break;
- case 1:
- size = 64 * 1024 * 1024;
- break;
- case 2:
- size = 128 * 1024 * 1024;
- break;
- case 4:
- size = 2 * 1024 * 1024;
- break;
- case 5:
- size = 4 * 1024 * 1024;
- break;
- case 6:
- size = 8 * 1024 * 1024;
- break;
- default:
- size = 16 * 1024 * 1024;
- break;
- }
-
- /*
- * Is bank7 also configured for SDRAM usage?
- */
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- size <<= 1; /* also count this bank */
-
- return size;
-}
-
-/**
- * Show the user the current clock settings
- */
-int s3c24xx_dump_clocks(void)
-{
- printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
- printf("mpll: %7d kHz\n", s3c24xx_get_mpllclk() / 1000);
- printf("upll: %7d kHz\n", s3c24xx_get_upllclk() / 1000);
- printf("fclk: %7d kHz\n", s3c24xx_get_fclk() / 1000);
- printf("hclk: %7d kHz\n", s3c24xx_get_hclk() / 1000);
- printf("pclk: %7d kHz\n", s3c24xx_get_pclk() / 1000);
- printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
- s3c24xx_get_hclk() / 1000000);
- return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
-
-static uint64_t s3c24xx_clocksource_read(void)
-{
- /* note: its a down counter */
- return 0xFFFF - readw(TCNTO4);
-}
-
-static struct clocksource cs = {
- .read = s3c24xx_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 10,
-};
-
-static int clocksource_init (void)
-{
- uint32_t p_clk = s3c24xx_get_pclk();
-
- writel(0x00000000, TCON); /* stop all timers */
- writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, TCFG1); /* /16 */
-
- writew(0xffff, TCNTB4); /* reload value is TOP */
-
- writel(0x00600000, TCON); /* force a first reload */
- writel(0x00400000, TCON);
- writel(0x00500000, TCON); /* enable timer 4 with auto reload */
-
- cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
- init_clock(&cs);
-
- return 0;
-}
-core_initcall(clocksource_init);
-
-void __noreturn reset_cpu(unsigned long addr)
-{
- /* Disable watchdog */
- writew(0x0000, WTCON);
-
- /* Initialize watchdog timer count register */
- writew(0x0001, WTCNT);
-
- /* Enable watchdog timer; assert reset at timer timeout */
- writew(0x0021, WTCON);
-
- /* loop forever and wait for reset to happen */
- while(1)
- ;
-}
-EXPORT_SYMBOL(reset_cpu);
-
-/**
-
-@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
-
-@section s3c24xx_boards Boards using S3C24xx Processors
-
-@li @subpage arch/arm/boards/a9m2410/a9m2410.c
-@li @subpage arch/arm/boards/a9m2440/a9m2440.c
-
-@section s3c24xx_arch Documentation for S3C24xx Architectures Files
-
-@li @subpage arch/arm/mach-s3c24xx/generic.c
-
-@section s3c24xx_mem_map SDRAM Memory Map
-
-SDRAM starts at address 0x3000.0000 up to the available amount of connected
-SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
-up to 128MiB each).
-
-@subsection s3c24xx_mem_generic_map Generic Map
-- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
-- 0x0800.0000 Start of I/O space.
-- 0x3000.0000 Start of SDRAM area.
- - 0x3000.0100 Start of the TAG list area.
- - 0x3000.8000 Start of the linux kernel (physical address).
-- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
-- 0x4800.0000 Start of the internal I/O area
-
-@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
-All S3C24xx common headers are located here.
-
-@note Do not add board specific header files/information here.
-*/
-
-/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
-
-@par barebox Map
-
-The location of the @a barebox itself depends on the available amount of
-installed SDRAM memory:
-
-- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
-- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
-- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
-
-Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
-the available memory.
-
-@note The RAM based filesystem and the stack resides always below the
-@a barebox start address.
-
-@li @subpage dev_s3c24xx_wd_handling
-@li @subpage dev_s3c24xx_pll_handling
-@li @subpage dev_s3c24xx_sdram_handling
-@li @subpage dev_s3c24xx_nandboot_handling
-*/
diff --git a/arch/arm/mach-s3c24xx/gpio-s3c24x0.c b/arch/arm/mach-s3c24xx/gpio-s3c24x0.c
deleted file mode 100644
index 946ec33..0000000
--- a/arch/arm/mach-s3c24xx/gpio-s3c24x0.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/s3c24x0-iomap.h>
-#include <mach/gpio.h>
-
-static const unsigned char group_offset[] =
-{
- 0x00, /* GPA */
- 0x10, /* GPB */
- 0x20, /* GPC */
- 0x30, /* GPD */
- 0x40, /* GPE */
- 0x50, /* GPF */
- 0x60, /* GPG */
- 0x70, /* GPH */
-#ifdef CONFIG_CPU_S3C2440
- 0xd0, /* GPJ */
-#endif
-};
-
-void gpio_set_value(unsigned gpio, int value)
-{
- unsigned group = gpio >> 5;
- unsigned bit = gpio % 32;
- unsigned offset;
- uint32_t reg;
-
- offset = group_offset[group];
-
- reg = readl(GPADAT + offset);
- reg &= ~(1 << bit);
- reg |= (!!value) << bit;
- writel(reg, GPADAT + offset);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- unsigned group = gpio >> 5;
- unsigned bit = gpio % 32;
- unsigned offset;
- uint32_t reg;
-
- offset = group_offset[group];
-
- reg = readl(GPACON + offset);
- reg &= ~(0x3 << (bit << 1));
- writel(reg, GPACON + offset);
-
- return 0;
-}
-
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- unsigned group = gpio >> 5;
- unsigned bit = gpio % 32;
- unsigned offset;
- uint32_t reg;
-
- offset = group_offset[group];
-
- /* value */
- gpio_set_value(gpio,value);
- /* direction */
- if (group == 0) { /* GPA is special */
- reg = readl(GPACON);
- reg &= ~(1 << bit);
- writel(reg, GPACON);
- } else {
- reg = readl(GPACON + offset);
- reg &= ~(0x3 << (bit << 1));
- reg |= 0x1 << (bit << 1);
- writel(reg, GPACON + offset);
- }
-
- return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- unsigned group = gpio >> 5;
- unsigned bit = gpio % 32;
- unsigned offset;
- uint32_t reg;
-
- if (group == 0) /* GPA is special: no input mode available */
- return -ENODEV;
-
- offset = group_offset[group];
-
- /* value */
- reg = readl(GPADAT + offset);
-
- return !!(reg & (1 << bit));
-}
-
-void s3c_gpio_mode(unsigned gpio_mode)
-{
- unsigned group, func, bit, offset, gpio;
- uint32_t reg;
-
- group = GET_GROUP(gpio_mode);
- func = GET_FUNC(gpio_mode);
- bit = GET_BIT(gpio_mode);
- gpio = GET_GPIO_NO(gpio_mode);
-
- if (group == 0) {
- /* GPA is special */
- switch (func) {
- case 0: /* GPIO input */
- pr_debug("Cannot set GPA pin to GPIO input\n");
- break;
- case 1: /* GPIO output */
- gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
- break;
- default:
- reg = readl(GPACON);
- reg |= 1 << bit;
- writel(reg, GPACON);
- break;
- }
- return;
- }
-
- offset = group_offset[group];
-
- if (PU_PRESENT(gpio_mode)) {
- reg = readl(GPACON + offset + 8);
- if (GET_PU(gpio_mode))
- reg |= (1 << bit); /* set means _disabled_ */
- else
- reg &= ~(1 << bit);
- writel(reg, GPACON + offset + 8);
- }
-
- switch (func) {
- case 0: /* input */
- gpio_direction_input(gpio);
- break;
- case 1: /* output */
- gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode));
- break;
- case 2: /* function one */
- case 3: /* function two */
- reg = readl(GPACON + offset);
- reg &= ~(0x3 << (bit << 1));
- reg |= func << (bit << 1);
- writel(reg, GPACON + offset);
- break;
- }
-}
diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h
deleted file mode 100644
index 05e013a..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/fb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __MACH_FB_H_
-# define __MACH_FB_H_
-
-#include <fb.h>
-
-/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
-
-/** ! INVVDEN - DE active high */
-#define FB_SYNC_DE_HIGH_ACT (1 << 23)
-/** INVVCLK - invert CLK signal */
-#define FB_SYNC_CLK_INVERT (1 << 24)
-/** INVVD - invert data */
-#define FB_SYNC_DATA_INVERT (1 << 25)
-/** INVPWREN - use PWREN signal */
-#define FB_SYNC_INVERT_PWREN (1 << 26)
-/** INVLEND - use LEND signal */
-#define FB_SYNC_INVERT_LEND (1 << 27)
-/** PWREN - use PWREN signal */
-#define FB_SYNC_USE_PWREN (1 << 28)
-/** ENLEND - use LEND signal */
-#define FB_SYNC_USE_LEND (1 << 29)
-/** BSWP - swap bytes */
-#define FB_SYNC_SWAP_BYTES (1 << 30)
-/** HWSWP - swap half words */
-#define FB_SYNC_SWAP_HW (1 << 31)
-
-struct s3c_fb_platform_data {
- struct fb_videomode *mode_list;
- unsigned mode_cnt;
-
- unsigned bits_per_pixel;
- int passive_display; /**< enable support for STN or CSTN displays */
-
- /** hook to enable backlight and stuff */
- void (*enable)(int enable);
-};
-
-#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
deleted file mode 100644
index 37db4f5..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/gpio.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_MACH_GPIO_H
-#define __ASM_MACH_GPIO_H
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410)
-# include <mach/iomux-s3c24x0.h>
-#endif
-
-void gpio_set_value(unsigned, int);
-int gpio_direction_input(unsigned);
-int gpio_direction_output(unsigned, int);
-int gpio_get_value(unsigned);
-void s3c_gpio_mode(unsigned);
-
-#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h b/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
deleted file mode 100644
index 2c64a97..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_IOMUX_S3C24x0_H
-#define __MACH_IOMUX_S3C24x0_H
-
-/* 3322222222221111111111
- * 10987654321098765432109876543210
- * ^^^^^_ Bit offset
- * ^^^^______ Group Number
- * ^^____________ Function
- * ^______________ initial GPIO out value
- * ^_______________ Pull up feature present
- * ^________________ initial pull up setting
- */
-
-
-#define PIN(group,bit) (group * 32 + bit)
-#define FUNC(x) (((x) & 0x3) << 11)
-#define GET_FUNC(x) (((x) >> 11) & 0x3)
-#define GET_GROUP(x) (((x) >> 5) & 0xf)
-#define GET_BIT(x) (((x) & 0x1ff) % 32)
-#define GET_GPIOVAL(x) (((x) >> 13) & 0x1)
-#define GET_GPIO_NO(x) ((x & 0x1ff))
-#define GPIO_OUT FUNC(1)
-#define GPIO_IN FUNC(0)
-#define GPIO_VAL(x) ((!!(x)) << 13)
-#define PU (1 << 14)
-#define PU_PRESENT(x) (!!((x) & (1 << 14)))
-#define ENABLE_PU (0 << 15)
-#define DISABLE_PU (1 << 15)
-#define GET_PU(x) (!!((x) & DISABLE_PU))
-
-/*
- * Group 0: GPIO 0...31
- * Used GPIO: 0...22
- * These pins can also act as GPIO outputs
- */
-#define GPA0_ADDR0 (PIN(0,0) | FUNC(2))
-#define GPA0_ADDR0_GPIO (PIN(0,0) | FUNC(0))
-#define GPA1_ADDR16 (PIN(0,1) | FUNC(2))
-#define GPA1_ADDR16_GPIO (PIN(0,1) | FUNC(0))
-#define GPA2_ADDR17 (PIN(0,2) | FUNC(2))
-#define GPA2_ADDR17_GPIO (PIN(0,2) | FUNC(0))
-#define GPA3_ADDR18 (PIN(0,3) | FUNC(2))
-#define GPA3_ADDR18_GPIO (PIN(0,3) | FUNC(0))
-#define GPA4_ADDR19 (PIN(0,4) | FUNC(2))
-#define GPA4_ADDR19_GPIO (PIN(0,4) | FUNC(0))
-#define GPA5_ADDR20 (PIN(0,5) | FUNC(2))
-#define GPA5_ADDR20_GPIO (PIN(0,5) | FUNC(0))
-#define GPA6_ADDR21 (PIN(0,6) | FUNC(2))
-#define GPA6_ADDR21_GPIO (PIN(0,6) | FUNC(0))
-#define GPA7_ADDR22 (PIN(0,7) | FUNC(2))
-#define GPA7_ADDR22_GPIO (PIN(0,7) | FUNC(0))
-#define GPA8_ADDR23 (PIN(0,8) | FUNC(2))
-#define GPA8_ADDR23_GPIO (PIN(0,8) | FUNC(0))
-#define GPA9_ADDR24 (PIN(0,9) | FUNC(2))
-#define GPA9_ADDR24_GPIO (PIN(0,9) | FUNC(0))
-#define GPA10_ADDR25 (PIN(0,10) | FUNC(2))
-#define GPA10_ADDR25_GPIO (PIN(0,10) | FUNC(0))
-#define GPA11_ADDR26 (PIN(0,11) | FUNC(2))
-#define GPA11_ADDR26_GPIO (PIN(0,11) | FUNC(0))
-#define GPA12_NGCS1 (PIN(0,12) | FUNC(2))
-#define GPA12_NGCS1_GPIO (PIN(0,12) | FUNC(0))
-#define GPA13_NGCS2 (PIN(0,13) | FUNC(2))
-#define GPA13_NGCS2_GPIO (PIN(0,13) | FUNC(0))
-#define GPA14_NGCS3 (PIN(0,14) | FUNC(2))
-#define GPA14_NGCS3_GPIO (PIN(0,14) | FUNC(0))
-#define GPA15_NGCS4 (PIN(0,15) | FUNC(2))
-#define GPA15_NGCS4_GPIO (PIN(0,15) | FUNC(0))
-#define GPA16_NGCS5 (PIN(0,16) | FUNC(2))
-#define GPA16_NGCS5_GPIO (PIN(0,16) | FUNC(0))
-#define GPA17_CLE (PIN(0,17) | FUNC(2))
-#define GPA17_CLE_GPIO (PIN(0,17) | FUNC(0))
-#define GPA18_ALE (PIN(0,18) | FUNC(2))
-#define GPA18_ALE_GPIO (PIN(0,18) | FUNC(0))
-#define GPA19_NFWE (PIN(0,19) | FUNC(2))
-#define GPA19_NFWE_GPIO (PIN(0,19) | FUNC(0))
-#define GPA20_NFRE (PIN(0,20) | FUNC(2))
-#define GPA20_NFRE_GPIO (PIN(0,20) | FUNC(0))
-#define GPA21_NRSTOUT (PIN(0,21) | FUNC(2))
-#define GPA21_NRSTOUT_GPIO (PIN(0,21) | FUNC(0))
-#define GPA22_NFCE (PIN(0,22) | FUNC(2))
-#define GPA22_NFCE_GPIO (PIN(0,22) | FUNC(0))
-
-/*
- * Group 1: GPIO 32...63
- * Used GPIO: 0...10
- * these pins can also act as GPIO inputs/outputs
- */
-#define GPB0_TOUT0 (PIN(1,0) | FUNC(2) | PU)
-#define GPB0_GPIO (PIN(1,0) | FUNC(0) | PU)
-#define GPB1_TOUT1 (PIN(1,1) | FUNC(2) | PU)
-#define GPB1_GPIO (PIN(1,1) | FUNC(0) | PU)
-#define GPB2_TOUT2 (PIN(1,2) | FUNC(2) | PU)
-#define GPB2_GPIO (PIN(1,2) | FUNC(0) | PU)
-#define GPB3_TOUT3 (PIN(1,3) | FUNC(2) | PU)
-#define GPB3_GPIO (PIN(1,3) | FUNC(0) | PU)
-#define GPB4_TCLK0 (PIN(1,4) | FUNC(2) | PU)
-#define GPB4_GPIO (PIN(1,4) | FUNC(0) | PU)
-#define GPB5_NXBACK (PIN(1,5) | FUNC(2) | PU)
-#define GPB5_GPIO (PIN(1,5) | FUNC(0) | PU)
-#define GPB6_NXBREQ (PIN(1,6) | FUNC(2) | PU)
-#define GPB6_GPIO (PIN(1,6) | FUNC(0) | PU)
-#define GPB7_NXDACK1 (PIN(1,7) | FUNC(2) | PU)
-#define GPB7_GPIO (PIN(1,7) | FUNC(0) | PU)
-#define GPB8_NXDREQ1 (PIN(1,8) | FUNC(2) | PU)
-#define GPB8_GPIO (PIN(1,8) | FUNC(0) | PU)
-#define GPB9_NXDACK0 (PIN(1,9) | FUNC(2) | PU)
-#define GPB9_GPIO (PIN(1,9) | FUNC(0) | PU)
-#define GPB10_NXDREQ0 (PIN(1,10) | FUNC(2) | PU)
-#define GPB10_GPIO (PIN(1,10) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 64...95
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPC0_LEND (PIN(2,0) | FUNC(2) | PU)
-#define GPC0_GPIO (PIN(2,0) | FUNC(0) | PU)
-#define GPC1_VCLK (PIN(2,1) | FUNC(2) | PU)
-#define GPC1_GPIO (PIN(2,1) | FUNC(0) | PU)
-#define GPC2_VLINE (PIN(2,2) | FUNC(2) | PU)
-#define GPC2_GPIO (PIN(2,2) | FUNC(0) | PU)
-#define GPC3_VFRAME (PIN(2,3) | FUNC(2) | PU)
-#define GPC3_GPIO (PIN(2,3) | FUNC(0) | PU)
-#define GPC4_VM (PIN(2,4) | FUNC(2) | PU)
-#define GPC4_GPIO (PIN(2,4) | FUNC(0) | PU)
-#define GPC5_LPCOE (PIN(2,5) | FUNC(2) | PU)
-#define GPC5_GPIO (PIN(2,5) | FUNC(0) | PU)
-#define GPC6_LPCREV (PIN(2,6) | FUNC(2) | PU)
-#define GPC6_GPIO (PIN(2,6) | FUNC(0) | PU)
-#define GPC7_LPCREVB (PIN(2,7) | FUNC(2) | PU)
-#define GPC7_GPIO (PIN(2,7) | FUNC(0) | PU)
-#define GPC8_VD0 (PIN(2,8) | FUNC(2) | PU)
-#define GPC8_GPIO (PIN(2,8) | FUNC(0) | PU)
-#define GPC9_VD1 (PIN(2,9) | FUNC(2) | PU)
-#define GPC9_GPIO (PIN(2,9) | FUNC(0) | PU)
-#define GPC10_VD2 (PIN(2,10) | FUNC(2) | PU)
-#define GPC10_GPIO (PIN(2,10) | FUNC(0) | PU)
-#define GPC11_VD3 (PIN(2,11) | FUNC(2) | PU)
-#define GPC11_GPIO (PIN(2,11) | FUNC(0) | PU)
-#define GPC12_VD4 (PIN(2,12) | FUNC(2) | PU)
-#define GPC12_GPIO (PIN(2,12) | FUNC(0) | PU)
-#define GPC13_VD5 (PIN(2,13) | FUNC(2) | PU)
-#define GPC13_GPIO (PIN(2,13) | FUNC(0) | PU)
-#define GPC14_VD6 (PIN(2,14) | FUNC(2) | PU)
-#define GPC14_GPIO (PIN(2,14) | FUNC(0) | PU)
-#define GPC15_VD7 (PIN(2,15) | FUNC(2) | PU)
-#define GPC15_GPIO (PIN(2,15) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 96...127
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPD0_VD8 (PIN(3,0) | FUNC(2) | PU)
-#define GPD0_GPIO (PIN(3,0) | FUNC(0) | PU)
-#define GPD1_VD9 (PIN(3,1) | FUNC(2) | PU)
-#define GPD1_GPIO (PIN(3,1) | FUNC(0) | PU)
-#define GPD2_VD10 (PIN(3,2) | FUNC(2) | PU)
-#define GPD2_GPIO (PIN(3,2) | FUNC(0) | PU)
-#define GPD3_VD11 (PIN(3,3) | FUNC(2) | PU)
-#define GPD3_GPIO (PIN(3,3) | FUNC(0) | PU)
-#define GPD4_VD12 (PIN(3,4) | FUNC(2) | PU)
-#define GPD4_GPIO (PIN(3,4) | FUNC(0) | PU)
-#define GPD5_VD13 (PIN(3,5) | FUNC(2) | PU)
-#define GPD5_GPIO (PIN(3,5) | FUNC(0) | PU)
-#define GPD6_VD14 (PIN(3,6) | FUNC(2) | PU)
-#define GPD6_GPIO (PIN(3,6) | FUNC(0) | PU)
-#define GPD7_VD15 (PIN(3,7) | FUNC(2) | PU)
-#define GPD7_GPIO (PIN(3,7) | FUNC(0) | PU)
-#define GPD8_VD16 (PIN(3,8) | FUNC(2) | PU)
-#define GPD8_GPIO (PIN(3,8) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD8_SPIMISO1 (PIN(3,8) | FUNC(3) | PU)
-#endif
-#define GPD9_VD17 (PIN(3,9) | FUNC(2) | PU)
-#define GPD9_GPIO (PIN(3,9) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD9_SPIMOSI1 (PIN(3,9) | FUNC(3) | PU)
-#endif
-#define GPD10_VD18 (PIN(3,10) | FUNC(2) | PU)
-#define GPD10_GPIO (PIN(3,10) | FUNC(0) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPD10_SPICLK (PIN(3,10) | FUNC(3) | PU)
-#endif
-#define GPD11_VD19 (PIN(3,11) | FUNC(2) | PU)
-#define GPD11_GPIO (PIN(3,11) | FUNC(0) | PU)
-#define GPD12_VD20 (PIN(3,12) | FUNC(2) | PU)
-#define GPD12_GPIO (PIN(3,12) | FUNC(0) | PU)
-#define GPD13_VD21 (PIN(3,13) | FUNC(2) | PU)
-#define GPD13_GPIO (PIN(3,13) | FUNC(0) | PU)
-#define GPD14_VD22 (PIN(3,14) | FUNC(2) | PU)
-#define GPD14_GPIO (PIN(3,14) | FUNC(0) | PU)
-#define GPD14_NSS1 (PIN(3,14) | FUNC(3) | PU)
-#define GPD15_VD23 (PIN(3,15) | FUNC(2) | PU)
-#define GPD15_GPIO (PIN(3,15) | FUNC(0) | PU)
-#define GPD15_NSS0 (PIN(3,15) | FUNC(3) | PU)
-
-/*
- * Group 1: GPIO 128...159
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPE0_I2SLRCK (PIN(4,0) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE0_AC_SYNC (PIN(4,0) | FUNC(3) | PU)
-#endif
-#define GPE0_GPIO (PIN(4,0) | FUNC(0) | PU)
-#define GPE1_I2SSCLK (PIN(4,1) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU)
-#endif
-#define GPE1_GPIO (PIN(4,1) | FUNC(0) | PU)
-#define GPE2_CDCLK (PIN(4,2) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE2_AC_NRESET (PIN(4,2) | FUNC(3) | PU)
-#endif
-#define GPE2_GPIO (PIN(4,2) | FUNC(0) | PU)
-#define GPE3_I2SDI (PIN(4,3) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2410
-# define GPE_NSS0 (PIN(4,3) | FUNC(3) | PU)
-#endif
-#define GPE3_GPIO (PIN(4,3) | FUNC(0) | PU)
-#define GPE4_I2SDO (PIN(4,4) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU)
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define GPE4_I2SSDI (PIN(4,4) | FUNC(3) | PU)
-#endif
-#define GPE4_GPIO (PIN(4,4) | FUNC(0) | PU)
-#define GPE5_SDCLK (PIN(4,5) | FUNC(2) | PU)
-#define GPE5_GPIO (PIN(4,5) | FUNC(0) | PU)
-#define GPE6_SDCMD (PIN(4,6) | FUNC(2) | PU)
-#define GPE6_GPIO (PIN(4,6) | FUNC(0) | PU)
-#define GPE7_SDDAT0 (PIN(4,7) | FUNC(2) | PU)
-#define GPE7_GPIO (PIN(4,7) | FUNC(0) | PU)
-#define GPE8_SDDAT1 (PIN(4,8) | FUNC(2) | PU)
-#define GPE8_GPIO (PIN(4,8) | FUNC(0) | PU)
-#define GPE9_SDDAT2 (PIN(4,9) | FUNC(2) | PU)
-#define GPE9_GPIO (PIN(4,9) | FUNC(0) | PU)
-#define GPE10_SDDAT3 (PIN(4,10) | FUNC(2) | PU)
-#define GPE10_GPIO (PIN(4,10) | FUNC(0) | PU)
-#define GPE11_SPIMISO0 (PIN(4,11) | FUNC(2) | PU)
-#define GPE11_GPIO (PIN(4,11) | FUNC(0) | PU)
-#define GPE12_SPIMOSI0 (PIN(4,12) | FUNC(2) | PU)
-#define GPE12_GPIO (PIN(4,12) | FUNC(0) | PU)
-#define GPE13_SPICLK0 (PIN(4,13) | FUNC(2) | PU)
-#define GPE13_GPIO (PIN(4,13) | FUNC(0) | PU)
-#define GPE14_IICSCL (PIN(4,14) | FUNC(2)) /* no pullup option */
-#define GPE14_GPIO (PIN(4,14) | FUNC(0)) /* no pullup option */
-#define GPE15_IICSDA (PIN(4,15) | FUNC(2)) /* no pullup option */
-#define GPE15_GPIO (PIN(4,15) | FUNC(0)) /* no pullup option */
-
-/*
- * Group 1: GPIO 160...191
- * Used GPIO: 0...7
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPF0_EINT0 (PIN(5,0) | FUNC(2) | PU)
-#define GPF0_GPIO (PIN(5,0) | FUNC(0) | PU)
-#define GPF1_EINT1 (PIN(5,1) | FUNC(2) | PU)
-#define GPF1_GPIO (PIN(5,1) | FUNC(0) | PU)
-#define GPF2_EINT2 (PIN(5,2) | FUNC(2) | PU)
-#define GPF2_GPIO (PIN(5,2) | FUNC(0) | PU)
-#define GPF3_EINT3 (PIN(5,3) | FUNC(2) | PU)
-#define GPF3_GPIO (PIN(5,3) | FUNC(0) | PU)
-#define GPF4_EINT4 (PIN(5,4) | FUNC(2) | PU)
-#define GPF4_GPIO (PIN(5,4) | FUNC(0) | PU)
-#define GPF5_EINT5 (PIN(5,5) | FUNC(2) | PU)
-#define GPF5_GPIO (PIN(5,5) | FUNC(0) | PU)
-#define GPF6_EINT6 (PIN(5,6) | FUNC(2) | PU)
-#define GPF6_GPIO (PIN(5,6) | FUNC(0) | PU)
-#define GPF7_EINT7 (PIN(5,7) | FUNC(2) | PU)
-#define GPF7_GPIO (PIN(5,7) | FUNC(0) | PU)
-
-/*
- * Group 1: GPIO 192..223
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPG0_EINT8 (PIN(6,0) | FUNC(2) | PU)
-#define GPG0_GPIO (PIN(6,0) | FUNC(0) | PU)
-#define GPG1_EINT9 (PIN(6,1) | FUNC(2) | PU)
-#define GPG1_GPIO (PIN(6,1) | FUNC(0) | PU)
-#define GPG2_EINT10 (PIN(6,2) | FUNC(2) | PU)
-#define GPG2_NSS0 (PIN(6,2) | FUNC(3) | PU)
-#define GPG2_GPIO (PIN(6,2) | FUNC(0) | PU)
-#define GPG3_EINT11 (PIN(6,3) | FUNC(2) | PU)
-#define GPG3_NSS1 (PIN(6,3) | FUNC(3) | PU)
-#define GPG3_GPIO (PIN(6,3) | FUNC(0) | PU)
-#define GPG4_EINT12 (PIN(6,4) | FUNC(2) | PU)
-#define GPG4_LCD_PWREN (PIN(6,4) | FUNC(3) | PU)
-#define GPG4_GPIO (PIN(6,4) | FUNC(0) | PU)
-#define GPG5_EINT13 (PIN(6,5) | FUNC(2) | PU)
-#define GPG5_SPIMISO1 (PIN(6,5) | FUNC(3) | PU)
-#define GPG5_GPIO (PIN(6,5) | FUNC(0) | PU)
-#define GPG6_EINT14 (PIN(6,6) | FUNC(2) | PU)
-#define GPG6_SPIMOSI1 (PIN(6,6) | FUNC(3) | PU)
-#define GPG6_GPIO (PIN(6,6) | FUNC(0) | PU)
-#define GPG7_EINT15 (PIN(6,7) | FUNC(2) | PU)
-#define GPG7_SPICLK1 (PIN(6,7) | FUNC(3) | PU)
-#define GPG7_GPIO (PIN(6,7) | FUNC(0) | PU)
-#define GPG8_EINT16 (PIN(6,8) | FUNC(2) | PU)
-#define GPG8_GPIO (PIN(6,8) | FUNC(0) | PU)
-#define GPG9_EINT17 (PIN(6,9) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG9_NRTS1 (PIN(6,9) | FUNC(3) | PU)
-#endif
-#define GPG9_GPIO (PIN(6,9) | FUNC(0) | PU)
-#define GPG10_EINT18 (PIN(6,10) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2440
-# define GPG10_NCTS1 (PIN(6,10) | FUNC(3) | PU)
-#endif
-#define GPG10_GPIO (PIN(6,10) | FUNC(0) | PU)
-#define GPG11_EINT19 (PIN(6,11) | FUNC(2) | PU)
-#define GPG11_TCLK (PIN(6,11) | FUNC(3) | PU)
-#define GPG11_GPIO (PIN(6,11) | FUNC(0) | PU)
-#define GPG12_EINT20 (PIN(6,12) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG12_XMON (PIN(6,12) | FUNC(3) | PU)
-#endif
-#define GPG12_GPIO (PIN(6,12) | FUNC(0) | PU)
-#define GPG13_EINT21 (PIN(6,13) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG13_NXPON (PIN(6,13) | FUNC(3) | PU)
-#endif
-#define GPG13_GPIO (PIN(6,13) | FUNC(0) | PU) /* must be input in NAND boot mode */
-#define GPG14_EINT22 (PIN(6,14) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG14_YMON (PIN(6,14) | FUNC(3) | PU)
-#endif
-#define GPG14_GPIO (PIN(6,14) | FUNC(0) | PU) /* must be input in NAND boot mode */
-#define GPG15_EINT23 (PIN(6,15) | FUNC(2) | PU)
-#ifdef CONFIG_CPU_S3C2410
-# define GPG15_YPON (PIN(6,15) | FUNC(3) | PU)
-#endif
-#define GPG15_GPIO (PIN(6,15) | FUNC(0) | PU) /* must be input in NAND boot mode */
-
-/*
- * Group 1: GPIO 224..255
- * Used GPIO: 0...15
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPH0_NCTS0 (PIN(7,0) | FUNC(2) | PU)
-#define GPH0_GPIO (PIN(7,0) | FUNC(0) | PU)
-#define GPH1_NRTS0 (PIN(7,1) | FUNC(2) | PU)
-#define GPH1_GPIO (PIN(7,1) | FUNC(0) | PU)
-#define GPH2_TXD0 (PIN(7,2) | FUNC(2) | PU)
-#define GPH2_GPIO (PIN(7,2) | FUNC(0) | PU)
-#define GPH3_RXD0 (PIN(7,3) | FUNC(2) | PU)
-#define GPH3_GPIO (PIN(7,3) | FUNC(0) | PU)
-#define GPH4_TXD1 (PIN(7,4) | FUNC(2) | PU)
-#define GPH4_GPIO (PIN(7,4) | FUNC(0) | PU)
-#define GPH5_RXD1 (PIN(7,5) | FUNC(2) | PU)
-#define GPH5_GPIO (PIN(7,5) | FUNC(0) | PU)
-#define GPH6_TXD2 (PIN(7,6) | FUNC(2) | PU)
-#define GPH6_NRTS1 (PIN(7,6) | FUNC(3) | PU)
-#define GPH6_GPIO (PIN(7,6) | FUNC(0) | PU)
-#define GPH7_RXD2 (PIN(7,7) | FUNC(2) | PU)
-#define GPH7_NCTS1 (PIN(7,7) | FUNC(3) | PU)
-#define GPH7_GPIO (PIN(7,7) | FUNC(0) | PU)
-#define GPH8_UEXTCLK (PIN(7,8) | FUNC(2) | PU)
-#define GPH8_GPIO (PIN(7,8) | FUNC(0) | PU)
-#define GPH9_CLOCKOUT0 (PIN(7,9) | FUNC(2) | PU)
-#define GPH9_GPIO (PIN(7,9) | FUNC(0) | PU)
-#define GPH10_CLKOUT1 (PIN(7,10) | FUNC(2) | PU)
-#define GPH10_GPIO (PIN(7,10) | FUNC(0) | PU)
-
-#ifdef CONFIG_CPU_S3C2440
-/*
- * Group 1: GPIO 256..287
- * Used GPIO: 0...12
- * These pins can also act as GPIO inputs/outputs
- */
-#define GPJ0_CAMDATA0 (PIN(8,0) | FUNC(2) | PU)
-#define GPJ0_GPIO (PIN(8,0) | FUNC(0) | PU)
-#define GPJ1_CAMDATA1 (PIN(8,1) | FUNC(2) | PU)
-#define GPJ1_GPIO (PIN(8,1) | FUNC(0) | PU)
-#define GPJ2_CAMDATA2 (PIN(8,2) | FUNC(2) | PU)
-#define GPJ2_GPIO (PIN(8,2) | FUNC(0) | PU)
-#define GPJ3_CAMDATA3 (PIN(8,3) | FUNC(2) | PU)
-#define GPJ3_GPIO (PIN(8,3) | FUNC(0) | PU)
-#define GPJ4_CAMDATA4 (PIN(8,4) | FUNC(2) | PU)
-#define GPJ4_GPIO (PIN(8,4) | FUNC(0) | PU)
-#define GPJ5_CAMDATA5 (PIN(8,5) | FUNC(2) | PU)
-#define GPJ5_GPIO (PIN(8,5) | FUNC(0) | PU)
-#define GPJ6_CAMDATA6 (PIN(8,6) | FUNC(2) | PU)
-#define GPJ6_GPIO (PIN(8,6) | FUNC(0) | PU)
-#define GPJ7_CAMDATA7 (PIN(8,7) | FUNC(2) | PU)
-#define GPJ7_GPIO (PIN(8,7) | FUNC(0) | PU)
-#define GPJ8_CAMPCLK (PIN(8,8) | FUNC(2) | PU)
-#define GPJ8_GPIO (PIN(8,8) | FUNC(0) | PU)
-#define GPJ9_CAMVSYNC (PIN(8,9) | FUNC(2) | PU)
-#define GPJ9_GPIO (PIN(8,9) | FUNC(0) | PU)
-#define GPJ10_CAMHREF (PIN(8,10) | FUNC(2) | PU)
-#define GPJ10_GPIO (PIN(8,10) | FUNC(0) | PU)
-#define GPJ11_CAMCLKOUT (PIN(8,11) | FUNC(2) | PU)
-#define GPJ11_GPIO (PIN(8,11) | FUNC(0) | PU)
-#define GPJ12_CAMRESET (PIN(8,12) | FUNC(0) | PU)
-#define GPJ12_GPIO (PIN(8,12) | FUNC(0) | PU)
-
-#endif
-
-#endif /* __MACH_IOMUX_S3C24x0_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/mci.h b/arch/arm/mach-s3c24xx/include/mach/mci.h
deleted file mode 100644
index 6ba8961..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/mci.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert, Pengutronix
- *
- * This code is partially based on u-boot code:
- *
- * Copyright 2008, Freescale Semiconductor, Inc
- * Andy Fleming
- *
- * Based (loosely) on the Linux code
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MMC_H_
-#define __MACH_MMC_H_
-
-struct s3c_mci_platform_data {
- unsigned caps; /**< supported operating modes (MMC_MODE_*) */
- unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
- unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
- unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
- /* TODO */
- /* function to modify the voltage */
- /* function to switch the voltage */
- /* function to detect the presence of a SD card in the socket */
- unsigned gpio_detect;
- unsigned detect_invert;
-};
-
-#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h
deleted file mode 100644
index a990d80..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/* S3C2410 device base addresses */
-#define S3C24X0_SDRAM_BASE 0x30000000
-#define S3C24X0_SDRAM_END 0x40000000
-#define S3C24X0_MEMCTL_BASE 0x48000000
-#define S3C2410_USB_HOST_BASE 0x49000000
-#define S3C2410_INTERRUPT_BASE 0x4A000000
-#define S3C2410_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
-#define S3C2410_LCD_BASE 0x4D000000
-#define S3C24X0_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
-#define S3C2410_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
-#define S3C2410_I2C_BASE 0x54000000
-#define S3C2410_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
-#define S3C2410_RTC_BASE 0x57000000
-#define S3C2410_ADC_BASE 0x58000000
-#define S3C2410_SPI_BASE 0x59000000
-#define S3C2410_SDI_BASE 0x5A000000
-
-/* Clock control (direct access) */
-
-#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
-#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
-#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
-#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
-#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
-#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
-
-/* Timer (direct access) */
-#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
-#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
-#define TCON (S3C24X0_TIMER_BASE + 0x08)
-#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
-#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
-#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
-#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
-#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
-#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
-#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
-#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
-#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
-#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
-#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
-#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
-#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
-#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
-
-/* Watchdog (direct access) */
-#define WTCON (S3C24X0_WATCHDOG_BASE)
-#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
-#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
-
-/*
- * if we are booting from NAND, its internal SRAM occures at
- * a different address than without this feature
- */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-# define NFC_RAM_AREA 0x00000000
-#else
-# define NFC_RAM_AREA 0x40000000
-#endif
-#define NFC_RAM_SIZE 4096
-
-/* internal UARTs (driver based) */
-#define UART1_BASE (S3C24X0_UART_BASE)
-#define UART1_SIZE 0x4000
-#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
-#define UART2_SIZE 0x4000
-#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
-#define UART3_SIZE 0x4000
-
-/* CS configuration (direct access) */
-#define BWSCON (S3C24X0_MEMCTL_BASE)
-#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
-#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
-#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
-#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
-#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
-#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
-#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
-#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
-#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
-#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
-#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
-#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
-
-/* GPIO registers (direct access) */
-#define GPACON (S3C24X0_GPIO_BASE)
-#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
-
-#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
-#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
-#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
-
-#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
-#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
-#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
-
-#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
-#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
-#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
-
-#define GPECON (S3C24X0_GPIO_BASE + 0x40)
-#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
-#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
-
-#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
-#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
-#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
-
-#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
-#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
-#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
-
-#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
-#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
-#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
-# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
-# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
-#endif
-
-#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
-#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
-#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
-#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
-#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
-#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
-#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
-#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
-#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
-#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
-#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
-#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
-#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
-#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
-#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
-#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
-# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
-#endif
-
-/* external IO space */
-#define CS0_BASE 0x00000000
-#define CS1_BASE 0x08000000
-#define CS2_BASE 0x10000000
-#define CS3_BASE 0x18000000
-#define CS4_BASE 0x20000000
-#define CS5_BASE 0x28000000
-#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
deleted file mode 100644
index 7610b4e..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int);
-#endif
-
-/**
- * Locate the timing bits for the NFCONF register
- * @param setup is the TACLS clock count
- * @param access is the TWRPH0 clock count
- * @param hold is the TWRPH1 clock count
- *
- * @note A clock count of 0 means always 1 HCLK clock.
- * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
- */
-#ifdef CONFIG_CPU_S3C2410
-# define CALC_NFCONF_TIMING(setup, access, hold) \
- ((setup << 8) + (access << 4) + (hold << 0))
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define CALC_NFCONF_TIMING(setup, access, hold) \
- ((setup << 12) + (access << 8) + (hold << 4))
-#endif
-
-/**
- * Define platform specific data for the NAND controller and its device
- */
-struct s3c24x0_nand_platform_data {
- uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */
- char flash_bbt; /**< force a flash based BBT */
-};
-
-/**
- * @file
- * @brief Basic declaration to use the s3c24x0 NAND driver
- */
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h b/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h
deleted file mode 100644
index b8abcf1..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert, Pengutronix
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-uint32_t s3c24xx_get_mpllclk(void);
-uint32_t s3c24xx_get_upllclk(void);
-uint32_t s3c24xx_get_fclk(void);
-uint32_t s3c24xx_get_hclk(void);
-uint32_t s3c24xx_get_pclk(void);
-uint32_t s3c24xx_get_uclk(void);
-uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-s3c24xx/lowlevel-init.S b/arch/arm/mach-s3c24xx/lowlevel-init.S
deleted file mode 100644
index e8004e5..0000000
--- a/arch/arm/mach-s3c24xx/lowlevel-init.S
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <mach/s3c24x0-iomap.h>
-
- .section ".text_bare_init.s3c24x0_disable_wd","ax"
-
-/*
- * Disable the watchdog, else it continues to bark
- */
-.globl s3c24x0_disable_wd
-s3c24x0_disable_wd:
-
- ldr r0, =S3C24X0_WATCHDOG_BASE
- mov r1, #0x0
- str r1, [r0]
- mov pc, lr
-
-/**
-@page dev_s3c24xx_wd_handling Watchdog handling
-
-The watchdog must be disabled very early, because if it resets the system
-it is still active and will continue to reset the system. So, call this
-routine very early in your board_init_lowlevel routine.
-*/
-
-/*
- * S3C2410 PLL configuration
- * -------------------------
- *
- * Basic frequency calculation
- *
- * m * REFclk s = SDIV
- * PLLclk = ------------ p = PDIV + 2
- * p * 2^s m = MDIV + 8
- *
- * After reset the PLL of the s3c2410 processor uses:
- *
- * MPLL UPLL
- * MDIV 0x5c 0x28
- * PDIV 0x08 0x08
- * SDIV 0x0 0x0
- *
- * 100 * 12MHz 1200MHz
- * MPLLclk = ------------- = -------- = 120MHz
- * 10 * 2^0 10
- *
- * 48 * 12MHz 576MHz
- * UPLLclk = ------------- = -------- = 57,6MHz
- * 10 * 2^0 10
- *
- * Note: Do not use "r10" here in this code
- */
-
-#ifdef CONFIG_S3C24XX_PLL_INIT
-
- .section ".text_bare_init.s3c24x0_pll_init","ax"
-
-.globl s3c24x0_pll_init
-s3c24x0_pll_init:
-
- mov r0, #S3C24X0_CLOCK_POWER_BASE
-
- /* configure internal clock ratio */
- mov r1, #BOARD_SPECIFIC_CLKDIVN
- str r1, [r0, #20]
-
- /* enable all devices on this chip */
- mov r1, #0xFFFFFFF0
- str r1, [r0, #12]
-
- /* ??????? */
-#ifdef CONFIG_CPU_S3C2440
- mov r1, #0xFFFFFFFF
-#endif
-#ifdef CONFIG_CPU_S3C2410
- mov r1, #0x00FFFFFF
-#endif
- str r1, [r0, #0]
-
-#ifdef CONFIG_CPU_S3C2440
- /*
- * Most of the time HDIVN is not 0, so we must use the
- * asynchronous bus mode (refer datasheet "Clock and Power Management")
- */
- mrc p15, 0, r1, c1, c0, 0
- orr r1, r1, #0xc0000000
- mcr p15, 0, r1, c1, c0, 0
-#endif
-
- /* configure UPLL */
- ldr r1, =BOARD_SPECIFIC_UPLL
- str r1, [r0, #8]
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* configure MPLL */
- ldr r1, =BOARD_SPECIFIC_MPLL
- str r1, [r0, #4]
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- mov pc, lr
-
-#endif
-
-/**
-@page dev_s3c24xx_pll_handling PLL clock handling
-
-To control the speed of your machine the PLLs must be reconfigured after reset.
-
-For example the S3C2410 CPU wakes up after reset at 120MHz main PLL speed,
-shared with all other system on chip components. Most of the time this
-configuration is to slow for the CPU and to fast for the other components.
-
-PLL reprogramming can be done in the machine specific manner very early when
-the CONFIG_S3C24XX_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
-defined. The board must provide a board_init_lowlevel() assembler function in
-this case and calling the s3c24x0_pll_init() assembler function.
-
-If the s3c24x0_pll_init() is called a few further symbols must be defined to
-setup the correct values for the machine.
-
-Define in the machine specific config.h the following symbols:
-
-- S3C24XX_CLOCK_REFERENCE with the frequency in Hz of your reference crystal.
-- BOARD_SPECIFIC_CLKDIVN with the value for the main clock ratio register (CLKDIVN)
-- BOARD_SPECIFIC_MPLL with the value for the main PLL setup register
-- BOARD_SPECIFIC_UPLL with the value for the USB PLL setup register
-
-@note Valid values for the PLL settings can be found in the CPU manual.
-
-@par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs) and S3C2440 (UPLL only)
-
-@f[
- f_{PLL} = \frac{m * f_{Ref}}{p * 2^s}
-@f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
-@par Background: PLL frequency calculation for the S3C2440 CPU (MPLL only)
-
-@f[
- f_{PLL} = \frac{2 * m * f_{Ref}}{p * 2^s}
-@f]
-
-With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
-
-@note This routine can be used for the S3C2410 and the S3C2440 CPU.
-
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C24XX_SDRAM_INIT
-
- .section ".text_bare_init.s3c24x0_sdram_init","ax"
-
- .globl s3c24x0_sdram_init
-s3c24x0_sdram_init:
-
- adr r0, SDRAMDATA /* get the current relative address of the table */
- mov r1, #S3C24X0_MEMCTL_BASE
- mov r2, #6 /* we *know* it contains 6 entries */
-
- ldr r3, [r0], #4 /* write BSWCON first */
- str r3, [r1], #0x1c /* post add register offset for bank6 */
-/*
- * Initializing the SDRAM controller is very simple:
- * Just write some useful values into the SDRAM controller.
- */
-0: ldr r3, [r0], #4
- str r3, [r1], #4
- subs r2, r2, #1
- bne 0b
-
- mov pc, lr
-
-SDRAMDATA:
- .word BOARD_SPECIFIC_BWSCON
- .word BOARD_SPECIFIC_BANKCON6
- .word BOARD_SPECIFIC_BANKCON7
- .word BOARD_SPECIFIC_REFRESH
- .word BOARD_SPECIFIC_BANKSIZE
- .word BOARD_SPECIFIC_MRSRB6
- .word BOARD_SPECIFIC_MRSRB7
-
-#endif
-
-/**
-@page dev_s3c24xx_sdram_handling SDRAM controller initialisation
-
-The SDRAM controller is very simple and its initialisation requires only a
-few steps. barebox provides a generic routine to do this step.
-
-Enable CONFIG_S3C24XX_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
-to call the generic s3c24x0_sdram_init() assembler function from within the
-machine specific board_init_lowlevel() assembler function.
-
-To use the s3c24x0_sdram_init() assembler function a few symbols must be
-defined to setup correct values for the machine.
-
-Define in the machine specific config.h the following list of symbols:
-
-- BOARD_SPECIFIC_BWSCON with the values for SDRAM banks 6 and 7
-- BOARD_SPECIFIC_BANKCON6 with the value for the BANKCON6 register
-- BOARD_SPECIFIC_BANKCON7 with the value for the BANKCON7 register
-- BOARD_SPECIFIC_REFRESH with the value for the REFRESH register
-- BOARD_SPECIFIC_BANKSIZE with the value for the BANKSIZE register
-- BOARD_SPECIFIC_MRSRB6 with the value for the MRSRB6 register
-- BOARD_SPECIFIC_MRSRB7 with the value for the MRSRB7 register
-*/
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-
- .section ".text_bare_init.s3c24x0_nand_boot","ax"
-
- .globl s3c24x0_nand_boot
-s3c24x0_nand_boot:
-/*
- * In the case of NOR boot we are running from the same address space.
- * Detect this case to handle it correctly.
- */
- mov r1, #S3C24X0_MEMCTL_BASE
- ldr r3, [r1]
- and r3, r3, #0x6
- cmp r3, #0x0 /* check for NAND case */
- beq 2f
- mov pc, lr /* NOR case: nothing to do here */
-
-2: ldr sp, =TEXT_BASE /* Setup a temporary stack in SDRAM */
-/*
- * We still run at a location we are not linked to. But lets still running
- * from the internal SRAM, this may speed up the boot
- */
- push {lr}
- bl nand_boot
- pop {lr}
-/*
- * Adjust the return address to the correct address in SDRAM
- */
- ldr r1, =TEXT_BASE
- add lr, lr, r1
-
- mov pc, lr
-
-#endif
-
-/**
-@page dev_s3c24xx_nandboot_handling Booting from NAND
-
-To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
-enable CONFIG_S3C24XX_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
-able to call the s3c24x0_nand_boot() assembler routine from within the
-machine specific board_init_lowlevel() assembler function.
-
-@note This routine assumes an already working SDRAM controller and
-an initialized stack pointer.
-
-@note Basicly this routine runs from inside the internal SRAM. After load of
-the whole barebox image from the NAND flash memory into the SDRAM it adjusts
-the link register to the final SDRAM adress and returns.
-
-@note In the NAND boot mode, ECC is not checked. So, the first x KBytes used
-by barebox should have no bit error.
-
-Due to the fact the code to load the whole barebox from NAND must fit into
-the first 4kiB of the barebox image, the shrinked NAND driver is very
-minimalistic. Setup the NAND access timing is done in a safe manner, what
-means: Slowest possible values are used. If you want to increase the speed you
-should define the BOARD_DEFAULT_NAND_TIMING to a valid setting into the
-NFCONF register and add it to your board specific config.h. Refer S3C24x0's
-datasheet for further details. The macro #CALC_NFCONF_TIMING could help to
-calculate the register setting in a hardware independent manner.
-
-@note The regular NAND driver uses a platform data structure to define the
-NAND access timings.
-
-@note Its still possible to boot this image from NOR memory. If this routine
-detects it is running from NOR instead of the internal SRAM it skips any
-loading and returns immediately.
-
-*/
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
new file mode 100644
index 0000000..a800cb8
--- /dev/null
+++ b/arch/arm/mach-samsung/Kconfig
@@ -0,0 +1,117 @@
+config ARCH_SAMSUNG
+ bool
+
+if ARCH_SAMSUNG
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x31fc0000 if MACH_MINI2440
+ default 0x31fc0000 if MACH_A9M2440
+ default 0x31fc0000 if MACH_A9M2410
+
+config BOARDINFO
+ default "Mini 2440" if MACH_MINI2440
+ default "Digi A9M2440" if MACH_A9M2440
+ default "Digi A9M2410" if MACH_A9M2410
+
+if ARCH_S3C24xx
+
+config CPU_S3C2410
+ bool
+
+config CPU_S3C2440
+ bool
+
+choice
+
+ prompt "S3C24xx Board Type"
+
+config MACH_A9M2410
+ bool "Digi A9M2410"
+ select CPU_S3C2410
+ select MACH_HAS_LOWLEVEL_INIT
+ select S3C24XX_PLL_INIT
+ select S3C24XX_SDRAM_INIT
+ help
+ Say Y here if you are using Digi's Connect Core 9M equipped
+ with a Samsung S3C2410 Processor
+
+config MACH_A9M2440
+ bool "Digi A9M2440"
+ select CPU_S3C2440
+ select MACH_HAS_LOWLEVEL_INIT
+ select S3C24XX_PLL_INIT
+ help
+ Say Y here if you are using Digi's Connect Core 9M equipped
+ with a Samsung S3C2440 Processor
+
+config MACH_MINI2440
+ bool "Mini 2440"
+ select CPU_S3C2440
+ select MACH_HAS_LOWLEVEL_INIT
+ select MACH_DO_LOWLEVEL_INIT
+ select S3C24XX_PLL_INIT
+ select S3C24XX_SDRAM_INIT
+ select HAS_DM9000
+ help
+ Say Y here if you are using Mini 2440 dev board equipped
+ with a Samsung S3C2440 Processor
+
+endchoice
+
+menu "Board specific settings "
+
+choice
+ prompt "A9M2440 baseboard"
+ depends on MACH_A9M2440
+
+config MACH_A9M2410DEV
+ bool
+ prompt "A9M2410dev"
+ select HAS_CS8900
+ help
+ Digi's evaluation board.
+
+endchoice
+
+source arch/arm/boards/mini2440/Kconfig
+
+endmenu
+
+menu "S3C24X0 Features "
+
+config S3C24XX_LOW_LEVEL_INIT
+ bool
+
+config S3C24XX_PLL_INIT
+ bool
+ prompt "Reconfigure PLL"
+ select S3C24XX_LOW_LEVEL_INIT
+ help
+ This adds generic code to reconfigure the internal PLL very early
+ after reset.
+
+config S3C24XX_SDRAM_INIT
+ bool
+ prompt "Initialize SDRAM"
+ select S3C24XX_LOW_LEVEL_INIT
+ help
+ This adds generic code to configure the SDRAM controller after reset.
+ The initialisation will be skipped if the code is already running
+ from SDRAM.
+
+config S3C24XX_NAND_BOOT
+ bool
+ prompt "Booting from NAND"
+ select MTD
+ select NAND
+ select NAND_S3C24X0
+ help
+ Add generic support to boot from NAND flash. Image loading will be
+ skipped if the code is running from NOR or already from SDRAM.
+
+endmenu
+
+endif
+
+endif
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
new file mode 100644
index 0000000..88d45fe
--- /dev/null
+++ b/arch/arm/mach-samsung/Makefile
@@ -0,0 +1,2 @@
+obj-y += generic.o gpio-s3c24x0.o
+obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
new file mode 100644
index 0000000..d2f2ac7
--- /dev/null
+++ b/arch/arm/mach-samsung/generic.c
@@ -0,0 +1,297 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/**
+ * @file
+ * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c24x0-iomap.h>
+
+/**
+ * Calculate the current M-PLL clock.
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_mpllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(MPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+#ifdef CONFIG_CPU_S3C2410
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
+#endif
+}
+
+/**
+ * Calculate the current U-PLL clock
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_upllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(UPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+/**
+ * Calculate the FCLK frequency used for the ARM CPU core
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_fclk(void)
+{
+ return s3c24xx_get_mpllclk();
+}
+
+/**
+ * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_hclk(void)
+{
+ uint32_t f_clk;
+
+ f_clk = s3c24xx_get_fclk();
+#ifdef CONFIG_CPU_S3C2410
+ if (readl(CLKDIVN) & 0x02)
+ return f_clk >> 1;
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ switch(readl(CLKDIVN) & 0x06) {
+ case 2:
+ return f_clk >> 1;
+ case 4:
+ return f_clk >> 2; /* TODO consider CAMDIVN */
+ case 6:
+ return f_clk / 3; /* TODO consider CAMDIVN */
+ }
+#endif
+ return f_clk;
+}
+
+/**
+ * Calculate the PCLK frequency used for the slower peripherals
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_pclk(void)
+{
+ uint32_t p_clk;
+
+ p_clk = s3c24xx_get_hclk();
+ if (readl(CLKDIVN) & 0x01)
+ return p_clk >> 1;
+ return p_clk;
+}
+
+/**
+ * Calculate the UCLK frequency used by the USB host device
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24xx_get_uclk(void)
+{
+ return s3c24xx_get_upllclk();
+}
+
+/**
+ * Calculate the amount of connected and available memory
+ * @return Memory size in bytes
+ */
+uint32_t s3c24x0_get_memory_size(void)
+{
+ uint32_t reg, size;
+
+ /*
+ * detect the current memory size
+ */
+ reg = readl(BANKSIZE);
+
+ switch (reg & 0x7) {
+ case 0:
+ size = 32 * 1024 * 1024;
+ break;
+ case 1:
+ size = 64 * 1024 * 1024;
+ break;
+ case 2:
+ size = 128 * 1024 * 1024;
+ break;
+ case 4:
+ size = 2 * 1024 * 1024;
+ break;
+ case 5:
+ size = 4 * 1024 * 1024;
+ break;
+ case 6:
+ size = 8 * 1024 * 1024;
+ break;
+ default:
+ size = 16 * 1024 * 1024;
+ break;
+ }
+
+ /*
+ * Is bank7 also configured for SDRAM usage?
+ */
+ if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ size <<= 1; /* also count this bank */
+
+ return size;
+}
+
+/**
+ * Show the user the current clock settings
+ */
+int s3c24xx_dump_clocks(void)
+{
+ printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
+ printf("mpll: %7d kHz\n", s3c24xx_get_mpllclk() / 1000);
+ printf("upll: %7d kHz\n", s3c24xx_get_upllclk() / 1000);
+ printf("fclk: %7d kHz\n", s3c24xx_get_fclk() / 1000);
+ printf("hclk: %7d kHz\n", s3c24xx_get_hclk() / 1000);
+ printf("pclk: %7d kHz\n", s3c24xx_get_pclk() / 1000);
+ printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
+ if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ s3c24xx_get_hclk() / 1000000);
+ return 0;
+}
+
+late_initcall(s3c24xx_dump_clocks);
+
+static uint64_t s3c24xx_clocksource_read(void)
+{
+ /* note: its a down counter */
+ return 0xFFFF - readw(TCNTO4);
+}
+
+static struct clocksource cs = {
+ .read = s3c24xx_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(16),
+ .shift = 10,
+};
+
+static int clocksource_init (void)
+{
+ uint32_t p_clk = s3c24xx_get_pclk();
+
+ writel(0x00000000, TCON); /* stop all timers */
+ writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
+ writel(0x00030000, TCFG1); /* /16 */
+
+ writew(0xffff, TCNTB4); /* reload value is TOP */
+
+ writel(0x00600000, TCON); /* force a first reload */
+ writel(0x00400000, TCON);
+ writel(0x00500000, TCON); /* enable timer 4 with auto reload */
+
+ cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
+ init_clock(&cs);
+
+ return 0;
+}
+core_initcall(clocksource_init);
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ /* Disable watchdog */
+ writew(0x0000, WTCON);
+
+ /* Initialize watchdog timer count register */
+ writew(0x0001, WTCNT);
+
+ /* Enable watchdog timer; assert reset at timer timeout */
+ writew(0x0021, WTCON);
+
+ /* loop forever and wait for reset to happen */
+ while(1)
+ ;
+}
+EXPORT_SYMBOL(reset_cpu);
+
+/**
+
+@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
+
+@section s3c24xx_boards Boards using S3C24xx Processors
+
+@li @subpage arch/arm/boards/a9m2410/a9m2410.c
+@li @subpage arch/arm/boards/a9m2440/a9m2440.c
+
+@section s3c24xx_arch Documentation for S3C24xx Architectures Files
+
+@li @subpage arch/arm/mach-s3c24xx/generic.c
+
+@section s3c24xx_mem_map SDRAM Memory Map
+
+SDRAM starts at address 0x3000.0000 up to the available amount of connected
+SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
+up to 128MiB each).
+
+@subsection s3c24xx_mem_generic_map Generic Map
+- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
+- 0x0800.0000 Start of I/O space.
+- 0x3000.0000 Start of SDRAM area.
+ - 0x3000.0100 Start of the TAG list area.
+ - 0x3000.8000 Start of the linux kernel (physical address).
+- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
+- 0x4800.0000 Start of the internal I/O area
+
+@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
+All S3C24xx common headers are located here.
+
+@note Do not add board specific header files/information here.
+*/
+
+/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
+
+@par barebox Map
+
+The location of the @a barebox itself depends on the available amount of
+installed SDRAM memory:
+
+- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
+- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
+- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
+
+Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
+the available memory.
+
+@note The RAM based filesystem and the stack resides always below the
+@a barebox start address.
+
+@li @subpage dev_s3c24xx_wd_handling
+@li @subpage dev_s3c24xx_pll_handling
+@li @subpage dev_s3c24xx_sdram_handling
+@li @subpage dev_s3c24xx_nandboot_handling
+*/
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
new file mode 100644
index 0000000..946ec33
--- /dev/null
+++ b/arch/arm/mach-samsung/gpio-s3c24x0.c
@@ -0,0 +1,169 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <io.h>
+#include <mach/s3c24x0-iomap.h>
+#include <mach/gpio.h>
+
+static const unsigned char group_offset[] =
+{
+ 0x00, /* GPA */
+ 0x10, /* GPB */
+ 0x20, /* GPC */
+ 0x30, /* GPD */
+ 0x40, /* GPE */
+ 0x50, /* GPF */
+ 0x60, /* GPG */
+ 0x70, /* GPH */
+#ifdef CONFIG_CPU_S3C2440
+ 0xd0, /* GPJ */
+#endif
+};
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ reg = readl(GPADAT + offset);
+ reg &= ~(1 << bit);
+ reg |= (!!value) << bit;
+ writel(reg, GPADAT + offset);
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ writel(reg, GPACON + offset);
+
+ return 0;
+}
+
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ /* value */
+ gpio_set_value(gpio,value);
+ /* direction */
+ if (group == 0) { /* GPA is special */
+ reg = readl(GPACON);
+ reg &= ~(1 << bit);
+ writel(reg, GPACON);
+ } else {
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ reg |= 0x1 << (bit << 1);
+ writel(reg, GPACON + offset);
+ }
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ if (group == 0) /* GPA is special: no input mode available */
+ return -ENODEV;
+
+ offset = group_offset[group];
+
+ /* value */
+ reg = readl(GPADAT + offset);
+
+ return !!(reg & (1 << bit));
+}
+
+void s3c_gpio_mode(unsigned gpio_mode)
+{
+ unsigned group, func, bit, offset, gpio;
+ uint32_t reg;
+
+ group = GET_GROUP(gpio_mode);
+ func = GET_FUNC(gpio_mode);
+ bit = GET_BIT(gpio_mode);
+ gpio = GET_GPIO_NO(gpio_mode);
+
+ if (group == 0) {
+ /* GPA is special */
+ switch (func) {
+ case 0: /* GPIO input */
+ pr_debug("Cannot set GPA pin to GPIO input\n");
+ break;
+ case 1: /* GPIO output */
+ gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
+ break;
+ default:
+ reg = readl(GPACON);
+ reg |= 1 << bit;
+ writel(reg, GPACON);
+ break;
+ }
+ return;
+ }
+
+ offset = group_offset[group];
+
+ if (PU_PRESENT(gpio_mode)) {
+ reg = readl(GPACON + offset + 8);
+ if (GET_PU(gpio_mode))
+ reg |= (1 << bit); /* set means _disabled_ */
+ else
+ reg &= ~(1 << bit);
+ writel(reg, GPACON + offset + 8);
+ }
+
+ switch (func) {
+ case 0: /* input */
+ gpio_direction_input(gpio);
+ break;
+ case 1: /* output */
+ gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode));
+ break;
+ case 2: /* function one */
+ case 3: /* function two */
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ reg |= func << (bit << 1);
+ writel(reg, GPACON + offset);
+ break;
+ }
+}
diff --git a/arch/arm/mach-samsung/include/mach/fb.h b/arch/arm/mach-samsung/include/mach/fb.h
new file mode 100644
index 0000000..05e013a
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/fb.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ * Copyright (C) 2011 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MACH_FB_H_
+# define __MACH_FB_H_
+
+#include <fb.h>
+
+/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
+
+/** ! INVVDEN - DE active high */
+#define FB_SYNC_DE_HIGH_ACT (1 << 23)
+/** INVVCLK - invert CLK signal */
+#define FB_SYNC_CLK_INVERT (1 << 24)
+/** INVVD - invert data */
+#define FB_SYNC_DATA_INVERT (1 << 25)
+/** INVPWREN - use PWREN signal */
+#define FB_SYNC_INVERT_PWREN (1 << 26)
+/** INVLEND - use LEND signal */
+#define FB_SYNC_INVERT_LEND (1 << 27)
+/** PWREN - use PWREN signal */
+#define FB_SYNC_USE_PWREN (1 << 28)
+/** ENLEND - use LEND signal */
+#define FB_SYNC_USE_LEND (1 << 29)
+/** BSWP - swap bytes */
+#define FB_SYNC_SWAP_BYTES (1 << 30)
+/** HWSWP - swap half words */
+#define FB_SYNC_SWAP_HW (1 << 31)
+
+struct s3c_fb_platform_data {
+ struct fb_videomode *mode_list;
+ unsigned mode_cnt;
+
+ unsigned bits_per_pixel;
+ int passive_display; /**< enable support for STN or CSTN displays */
+
+ /** hook to enable backlight and stuff */
+ void (*enable)(int enable);
+};
+
+#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
new file mode 100644
index 0000000..37db4f5
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -0,0 +1,31 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_MACH_GPIO_H
+#define __ASM_MACH_GPIO_H
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410)
+# include <mach/iomux-s3c24x0.h>
+#endif
+
+void gpio_set_value(unsigned, int);
+int gpio_direction_input(unsigned);
+int gpio_direction_output(unsigned, int);
+int gpio_get_value(unsigned);
+void s3c_gpio_mode(unsigned);
+
+#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h b/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
new file mode 100644
index 0000000..2c64a97
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/iomux-s3c24x0.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_IOMUX_S3C24x0_H
+#define __MACH_IOMUX_S3C24x0_H
+
+/* 3322222222221111111111
+ * 10987654321098765432109876543210
+ * ^^^^^_ Bit offset
+ * ^^^^______ Group Number
+ * ^^____________ Function
+ * ^______________ initial GPIO out value
+ * ^_______________ Pull up feature present
+ * ^________________ initial pull up setting
+ */
+
+
+#define PIN(group,bit) (group * 32 + bit)
+#define FUNC(x) (((x) & 0x3) << 11)
+#define GET_FUNC(x) (((x) >> 11) & 0x3)
+#define GET_GROUP(x) (((x) >> 5) & 0xf)
+#define GET_BIT(x) (((x) & 0x1ff) % 32)
+#define GET_GPIOVAL(x) (((x) >> 13) & 0x1)
+#define GET_GPIO_NO(x) ((x & 0x1ff))
+#define GPIO_OUT FUNC(1)
+#define GPIO_IN FUNC(0)
+#define GPIO_VAL(x) ((!!(x)) << 13)
+#define PU (1 << 14)
+#define PU_PRESENT(x) (!!((x) & (1 << 14)))
+#define ENABLE_PU (0 << 15)
+#define DISABLE_PU (1 << 15)
+#define GET_PU(x) (!!((x) & DISABLE_PU))
+
+/*
+ * Group 0: GPIO 0...31
+ * Used GPIO: 0...22
+ * These pins can also act as GPIO outputs
+ */
+#define GPA0_ADDR0 (PIN(0,0) | FUNC(2))
+#define GPA0_ADDR0_GPIO (PIN(0,0) | FUNC(0))
+#define GPA1_ADDR16 (PIN(0,1) | FUNC(2))
+#define GPA1_ADDR16_GPIO (PIN(0,1) | FUNC(0))
+#define GPA2_ADDR17 (PIN(0,2) | FUNC(2))
+#define GPA2_ADDR17_GPIO (PIN(0,2) | FUNC(0))
+#define GPA3_ADDR18 (PIN(0,3) | FUNC(2))
+#define GPA3_ADDR18_GPIO (PIN(0,3) | FUNC(0))
+#define GPA4_ADDR19 (PIN(0,4) | FUNC(2))
+#define GPA4_ADDR19_GPIO (PIN(0,4) | FUNC(0))
+#define GPA5_ADDR20 (PIN(0,5) | FUNC(2))
+#define GPA5_ADDR20_GPIO (PIN(0,5) | FUNC(0))
+#define GPA6_ADDR21 (PIN(0,6) | FUNC(2))
+#define GPA6_ADDR21_GPIO (PIN(0,6) | FUNC(0))
+#define GPA7_ADDR22 (PIN(0,7) | FUNC(2))
+#define GPA7_ADDR22_GPIO (PIN(0,7) | FUNC(0))
+#define GPA8_ADDR23 (PIN(0,8) | FUNC(2))
+#define GPA8_ADDR23_GPIO (PIN(0,8) | FUNC(0))
+#define GPA9_ADDR24 (PIN(0,9) | FUNC(2))
+#define GPA9_ADDR24_GPIO (PIN(0,9) | FUNC(0))
+#define GPA10_ADDR25 (PIN(0,10) | FUNC(2))
+#define GPA10_ADDR25_GPIO (PIN(0,10) | FUNC(0))
+#define GPA11_ADDR26 (PIN(0,11) | FUNC(2))
+#define GPA11_ADDR26_GPIO (PIN(0,11) | FUNC(0))
+#define GPA12_NGCS1 (PIN(0,12) | FUNC(2))
+#define GPA12_NGCS1_GPIO (PIN(0,12) | FUNC(0))
+#define GPA13_NGCS2 (PIN(0,13) | FUNC(2))
+#define GPA13_NGCS2_GPIO (PIN(0,13) | FUNC(0))
+#define GPA14_NGCS3 (PIN(0,14) | FUNC(2))
+#define GPA14_NGCS3_GPIO (PIN(0,14) | FUNC(0))
+#define GPA15_NGCS4 (PIN(0,15) | FUNC(2))
+#define GPA15_NGCS4_GPIO (PIN(0,15) | FUNC(0))
+#define GPA16_NGCS5 (PIN(0,16) | FUNC(2))
+#define GPA16_NGCS5_GPIO (PIN(0,16) | FUNC(0))
+#define GPA17_CLE (PIN(0,17) | FUNC(2))
+#define GPA17_CLE_GPIO (PIN(0,17) | FUNC(0))
+#define GPA18_ALE (PIN(0,18) | FUNC(2))
+#define GPA18_ALE_GPIO (PIN(0,18) | FUNC(0))
+#define GPA19_NFWE (PIN(0,19) | FUNC(2))
+#define GPA19_NFWE_GPIO (PIN(0,19) | FUNC(0))
+#define GPA20_NFRE (PIN(0,20) | FUNC(2))
+#define GPA20_NFRE_GPIO (PIN(0,20) | FUNC(0))
+#define GPA21_NRSTOUT (PIN(0,21) | FUNC(2))
+#define GPA21_NRSTOUT_GPIO (PIN(0,21) | FUNC(0))
+#define GPA22_NFCE (PIN(0,22) | FUNC(2))
+#define GPA22_NFCE_GPIO (PIN(0,22) | FUNC(0))
+
+/*
+ * Group 1: GPIO 32...63
+ * Used GPIO: 0...10
+ * these pins can also act as GPIO inputs/outputs
+ */
+#define GPB0_TOUT0 (PIN(1,0) | FUNC(2) | PU)
+#define GPB0_GPIO (PIN(1,0) | FUNC(0) | PU)
+#define GPB1_TOUT1 (PIN(1,1) | FUNC(2) | PU)
+#define GPB1_GPIO (PIN(1,1) | FUNC(0) | PU)
+#define GPB2_TOUT2 (PIN(1,2) | FUNC(2) | PU)
+#define GPB2_GPIO (PIN(1,2) | FUNC(0) | PU)
+#define GPB3_TOUT3 (PIN(1,3) | FUNC(2) | PU)
+#define GPB3_GPIO (PIN(1,3) | FUNC(0) | PU)
+#define GPB4_TCLK0 (PIN(1,4) | FUNC(2) | PU)
+#define GPB4_GPIO (PIN(1,4) | FUNC(0) | PU)
+#define GPB5_NXBACK (PIN(1,5) | FUNC(2) | PU)
+#define GPB5_GPIO (PIN(1,5) | FUNC(0) | PU)
+#define GPB6_NXBREQ (PIN(1,6) | FUNC(2) | PU)
+#define GPB6_GPIO (PIN(1,6) | FUNC(0) | PU)
+#define GPB7_NXDACK1 (PIN(1,7) | FUNC(2) | PU)
+#define GPB7_GPIO (PIN(1,7) | FUNC(0) | PU)
+#define GPB8_NXDREQ1 (PIN(1,8) | FUNC(2) | PU)
+#define GPB8_GPIO (PIN(1,8) | FUNC(0) | PU)
+#define GPB9_NXDACK0 (PIN(1,9) | FUNC(2) | PU)
+#define GPB9_GPIO (PIN(1,9) | FUNC(0) | PU)
+#define GPB10_NXDREQ0 (PIN(1,10) | FUNC(2) | PU)
+#define GPB10_GPIO (PIN(1,10) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 64...95
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPC0_LEND (PIN(2,0) | FUNC(2) | PU)
+#define GPC0_GPIO (PIN(2,0) | FUNC(0) | PU)
+#define GPC1_VCLK (PIN(2,1) | FUNC(2) | PU)
+#define GPC1_GPIO (PIN(2,1) | FUNC(0) | PU)
+#define GPC2_VLINE (PIN(2,2) | FUNC(2) | PU)
+#define GPC2_GPIO (PIN(2,2) | FUNC(0) | PU)
+#define GPC3_VFRAME (PIN(2,3) | FUNC(2) | PU)
+#define GPC3_GPIO (PIN(2,3) | FUNC(0) | PU)
+#define GPC4_VM (PIN(2,4) | FUNC(2) | PU)
+#define GPC4_GPIO (PIN(2,4) | FUNC(0) | PU)
+#define GPC5_LPCOE (PIN(2,5) | FUNC(2) | PU)
+#define GPC5_GPIO (PIN(2,5) | FUNC(0) | PU)
+#define GPC6_LPCREV (PIN(2,6) | FUNC(2) | PU)
+#define GPC6_GPIO (PIN(2,6) | FUNC(0) | PU)
+#define GPC7_LPCREVB (PIN(2,7) | FUNC(2) | PU)
+#define GPC7_GPIO (PIN(2,7) | FUNC(0) | PU)
+#define GPC8_VD0 (PIN(2,8) | FUNC(2) | PU)
+#define GPC8_GPIO (PIN(2,8) | FUNC(0) | PU)
+#define GPC9_VD1 (PIN(2,9) | FUNC(2) | PU)
+#define GPC9_GPIO (PIN(2,9) | FUNC(0) | PU)
+#define GPC10_VD2 (PIN(2,10) | FUNC(2) | PU)
+#define GPC10_GPIO (PIN(2,10) | FUNC(0) | PU)
+#define GPC11_VD3 (PIN(2,11) | FUNC(2) | PU)
+#define GPC11_GPIO (PIN(2,11) | FUNC(0) | PU)
+#define GPC12_VD4 (PIN(2,12) | FUNC(2) | PU)
+#define GPC12_GPIO (PIN(2,12) | FUNC(0) | PU)
+#define GPC13_VD5 (PIN(2,13) | FUNC(2) | PU)
+#define GPC13_GPIO (PIN(2,13) | FUNC(0) | PU)
+#define GPC14_VD6 (PIN(2,14) | FUNC(2) | PU)
+#define GPC14_GPIO (PIN(2,14) | FUNC(0) | PU)
+#define GPC15_VD7 (PIN(2,15) | FUNC(2) | PU)
+#define GPC15_GPIO (PIN(2,15) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 96...127
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPD0_VD8 (PIN(3,0) | FUNC(2) | PU)
+#define GPD0_GPIO (PIN(3,0) | FUNC(0) | PU)
+#define GPD1_VD9 (PIN(3,1) | FUNC(2) | PU)
+#define GPD1_GPIO (PIN(3,1) | FUNC(0) | PU)
+#define GPD2_VD10 (PIN(3,2) | FUNC(2) | PU)
+#define GPD2_GPIO (PIN(3,2) | FUNC(0) | PU)
+#define GPD3_VD11 (PIN(3,3) | FUNC(2) | PU)
+#define GPD3_GPIO (PIN(3,3) | FUNC(0) | PU)
+#define GPD4_VD12 (PIN(3,4) | FUNC(2) | PU)
+#define GPD4_GPIO (PIN(3,4) | FUNC(0) | PU)
+#define GPD5_VD13 (PIN(3,5) | FUNC(2) | PU)
+#define GPD5_GPIO (PIN(3,5) | FUNC(0) | PU)
+#define GPD6_VD14 (PIN(3,6) | FUNC(2) | PU)
+#define GPD6_GPIO (PIN(3,6) | FUNC(0) | PU)
+#define GPD7_VD15 (PIN(3,7) | FUNC(2) | PU)
+#define GPD7_GPIO (PIN(3,7) | FUNC(0) | PU)
+#define GPD8_VD16 (PIN(3,8) | FUNC(2) | PU)
+#define GPD8_GPIO (PIN(3,8) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD8_SPIMISO1 (PIN(3,8) | FUNC(3) | PU)
+#endif
+#define GPD9_VD17 (PIN(3,9) | FUNC(2) | PU)
+#define GPD9_GPIO (PIN(3,9) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD9_SPIMOSI1 (PIN(3,9) | FUNC(3) | PU)
+#endif
+#define GPD10_VD18 (PIN(3,10) | FUNC(2) | PU)
+#define GPD10_GPIO (PIN(3,10) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD10_SPICLK (PIN(3,10) | FUNC(3) | PU)
+#endif
+#define GPD11_VD19 (PIN(3,11) | FUNC(2) | PU)
+#define GPD11_GPIO (PIN(3,11) | FUNC(0) | PU)
+#define GPD12_VD20 (PIN(3,12) | FUNC(2) | PU)
+#define GPD12_GPIO (PIN(3,12) | FUNC(0) | PU)
+#define GPD13_VD21 (PIN(3,13) | FUNC(2) | PU)
+#define GPD13_GPIO (PIN(3,13) | FUNC(0) | PU)
+#define GPD14_VD22 (PIN(3,14) | FUNC(2) | PU)
+#define GPD14_GPIO (PIN(3,14) | FUNC(0) | PU)
+#define GPD14_NSS1 (PIN(3,14) | FUNC(3) | PU)
+#define GPD15_VD23 (PIN(3,15) | FUNC(2) | PU)
+#define GPD15_GPIO (PIN(3,15) | FUNC(0) | PU)
+#define GPD15_NSS0 (PIN(3,15) | FUNC(3) | PU)
+
+/*
+ * Group 1: GPIO 128...159
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPE0_I2SLRCK (PIN(4,0) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE0_AC_SYNC (PIN(4,0) | FUNC(3) | PU)
+#endif
+#define GPE0_GPIO (PIN(4,0) | FUNC(0) | PU)
+#define GPE1_I2SSCLK (PIN(4,1) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU)
+#endif
+#define GPE1_GPIO (PIN(4,1) | FUNC(0) | PU)
+#define GPE2_CDCLK (PIN(4,2) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE2_AC_NRESET (PIN(4,2) | FUNC(3) | PU)
+#endif
+#define GPE2_GPIO (PIN(4,2) | FUNC(0) | PU)
+#define GPE3_I2SDI (PIN(4,3) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU)
+#endif
+#ifdef CONFIG_CPU_S3C2410
+# define GPE_NSS0 (PIN(4,3) | FUNC(3) | PU)
+#endif
+#define GPE3_GPIO (PIN(4,3) | FUNC(0) | PU)
+#define GPE4_I2SDO (PIN(4,4) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU)
+#endif
+#ifdef CONFIG_CPU_S3C2440
+# define GPE4_I2SSDI (PIN(4,4) | FUNC(3) | PU)
+#endif
+#define GPE4_GPIO (PIN(4,4) | FUNC(0) | PU)
+#define GPE5_SDCLK (PIN(4,5) | FUNC(2) | PU)
+#define GPE5_GPIO (PIN(4,5) | FUNC(0) | PU)
+#define GPE6_SDCMD (PIN(4,6) | FUNC(2) | PU)
+#define GPE6_GPIO (PIN(4,6) | FUNC(0) | PU)
+#define GPE7_SDDAT0 (PIN(4,7) | FUNC(2) | PU)
+#define GPE7_GPIO (PIN(4,7) | FUNC(0) | PU)
+#define GPE8_SDDAT1 (PIN(4,8) | FUNC(2) | PU)
+#define GPE8_GPIO (PIN(4,8) | FUNC(0) | PU)
+#define GPE9_SDDAT2 (PIN(4,9) | FUNC(2) | PU)
+#define GPE9_GPIO (PIN(4,9) | FUNC(0) | PU)
+#define GPE10_SDDAT3 (PIN(4,10) | FUNC(2) | PU)
+#define GPE10_GPIO (PIN(4,10) | FUNC(0) | PU)
+#define GPE11_SPIMISO0 (PIN(4,11) | FUNC(2) | PU)
+#define GPE11_GPIO (PIN(4,11) | FUNC(0) | PU)
+#define GPE12_SPIMOSI0 (PIN(4,12) | FUNC(2) | PU)
+#define GPE12_GPIO (PIN(4,12) | FUNC(0) | PU)
+#define GPE13_SPICLK0 (PIN(4,13) | FUNC(2) | PU)
+#define GPE13_GPIO (PIN(4,13) | FUNC(0) | PU)
+#define GPE14_IICSCL (PIN(4,14) | FUNC(2)) /* no pullup option */
+#define GPE14_GPIO (PIN(4,14) | FUNC(0)) /* no pullup option */
+#define GPE15_IICSDA (PIN(4,15) | FUNC(2)) /* no pullup option */
+#define GPE15_GPIO (PIN(4,15) | FUNC(0)) /* no pullup option */
+
+/*
+ * Group 1: GPIO 160...191
+ * Used GPIO: 0...7
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPF0_EINT0 (PIN(5,0) | FUNC(2) | PU)
+#define GPF0_GPIO (PIN(5,0) | FUNC(0) | PU)
+#define GPF1_EINT1 (PIN(5,1) | FUNC(2) | PU)
+#define GPF1_GPIO (PIN(5,1) | FUNC(0) | PU)
+#define GPF2_EINT2 (PIN(5,2) | FUNC(2) | PU)
+#define GPF2_GPIO (PIN(5,2) | FUNC(0) | PU)
+#define GPF3_EINT3 (PIN(5,3) | FUNC(2) | PU)
+#define GPF3_GPIO (PIN(5,3) | FUNC(0) | PU)
+#define GPF4_EINT4 (PIN(5,4) | FUNC(2) | PU)
+#define GPF4_GPIO (PIN(5,4) | FUNC(0) | PU)
+#define GPF5_EINT5 (PIN(5,5) | FUNC(2) | PU)
+#define GPF5_GPIO (PIN(5,5) | FUNC(0) | PU)
+#define GPF6_EINT6 (PIN(5,6) | FUNC(2) | PU)
+#define GPF6_GPIO (PIN(5,6) | FUNC(0) | PU)
+#define GPF7_EINT7 (PIN(5,7) | FUNC(2) | PU)
+#define GPF7_GPIO (PIN(5,7) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 192..223
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPG0_EINT8 (PIN(6,0) | FUNC(2) | PU)
+#define GPG0_GPIO (PIN(6,0) | FUNC(0) | PU)
+#define GPG1_EINT9 (PIN(6,1) | FUNC(2) | PU)
+#define GPG1_GPIO (PIN(6,1) | FUNC(0) | PU)
+#define GPG2_EINT10 (PIN(6,2) | FUNC(2) | PU)
+#define GPG2_NSS0 (PIN(6,2) | FUNC(3) | PU)
+#define GPG2_GPIO (PIN(6,2) | FUNC(0) | PU)
+#define GPG3_EINT11 (PIN(6,3) | FUNC(2) | PU)
+#define GPG3_NSS1 (PIN(6,3) | FUNC(3) | PU)
+#define GPG3_GPIO (PIN(6,3) | FUNC(0) | PU)
+#define GPG4_EINT12 (PIN(6,4) | FUNC(2) | PU)
+#define GPG4_LCD_PWREN (PIN(6,4) | FUNC(3) | PU)
+#define GPG4_GPIO (PIN(6,4) | FUNC(0) | PU)
+#define GPG5_EINT13 (PIN(6,5) | FUNC(2) | PU)
+#define GPG5_SPIMISO1 (PIN(6,5) | FUNC(3) | PU)
+#define GPG5_GPIO (PIN(6,5) | FUNC(0) | PU)
+#define GPG6_EINT14 (PIN(6,6) | FUNC(2) | PU)
+#define GPG6_SPIMOSI1 (PIN(6,6) | FUNC(3) | PU)
+#define GPG6_GPIO (PIN(6,6) | FUNC(0) | PU)
+#define GPG7_EINT15 (PIN(6,7) | FUNC(2) | PU)
+#define GPG7_SPICLK1 (PIN(6,7) | FUNC(3) | PU)
+#define GPG7_GPIO (PIN(6,7) | FUNC(0) | PU)
+#define GPG8_EINT16 (PIN(6,8) | FUNC(2) | PU)
+#define GPG8_GPIO (PIN(6,8) | FUNC(0) | PU)
+#define GPG9_EINT17 (PIN(6,9) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPG9_NRTS1 (PIN(6,9) | FUNC(3) | PU)
+#endif
+#define GPG9_GPIO (PIN(6,9) | FUNC(0) | PU)
+#define GPG10_EINT18 (PIN(6,10) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPG10_NCTS1 (PIN(6,10) | FUNC(3) | PU)
+#endif
+#define GPG10_GPIO (PIN(6,10) | FUNC(0) | PU)
+#define GPG11_EINT19 (PIN(6,11) | FUNC(2) | PU)
+#define GPG11_TCLK (PIN(6,11) | FUNC(3) | PU)
+#define GPG11_GPIO (PIN(6,11) | FUNC(0) | PU)
+#define GPG12_EINT20 (PIN(6,12) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG12_XMON (PIN(6,12) | FUNC(3) | PU)
+#endif
+#define GPG12_GPIO (PIN(6,12) | FUNC(0) | PU)
+#define GPG13_EINT21 (PIN(6,13) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG13_NXPON (PIN(6,13) | FUNC(3) | PU)
+#endif
+#define GPG13_GPIO (PIN(6,13) | FUNC(0) | PU) /* must be input in NAND boot mode */
+#define GPG14_EINT22 (PIN(6,14) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG14_YMON (PIN(6,14) | FUNC(3) | PU)
+#endif
+#define GPG14_GPIO (PIN(6,14) | FUNC(0) | PU) /* must be input in NAND boot mode */
+#define GPG15_EINT23 (PIN(6,15) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG15_YPON (PIN(6,15) | FUNC(3) | PU)
+#endif
+#define GPG15_GPIO (PIN(6,15) | FUNC(0) | PU) /* must be input in NAND boot mode */
+
+/*
+ * Group 1: GPIO 224..255
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPH0_NCTS0 (PIN(7,0) | FUNC(2) | PU)
+#define GPH0_GPIO (PIN(7,0) | FUNC(0) | PU)
+#define GPH1_NRTS0 (PIN(7,1) | FUNC(2) | PU)
+#define GPH1_GPIO (PIN(7,1) | FUNC(0) | PU)
+#define GPH2_TXD0 (PIN(7,2) | FUNC(2) | PU)
+#define GPH2_GPIO (PIN(7,2) | FUNC(0) | PU)
+#define GPH3_RXD0 (PIN(7,3) | FUNC(2) | PU)
+#define GPH3_GPIO (PIN(7,3) | FUNC(0) | PU)
+#define GPH4_TXD1 (PIN(7,4) | FUNC(2) | PU)
+#define GPH4_GPIO (PIN(7,4) | FUNC(0) | PU)
+#define GPH5_RXD1 (PIN(7,5) | FUNC(2) | PU)
+#define GPH5_GPIO (PIN(7,5) | FUNC(0) | PU)
+#define GPH6_TXD2 (PIN(7,6) | FUNC(2) | PU)
+#define GPH6_NRTS1 (PIN(7,6) | FUNC(3) | PU)
+#define GPH6_GPIO (PIN(7,6) | FUNC(0) | PU)
+#define GPH7_RXD2 (PIN(7,7) | FUNC(2) | PU)
+#define GPH7_NCTS1 (PIN(7,7) | FUNC(3) | PU)
+#define GPH7_GPIO (PIN(7,7) | FUNC(0) | PU)
+#define GPH8_UEXTCLK (PIN(7,8) | FUNC(2) | PU)
+#define GPH8_GPIO (PIN(7,8) | FUNC(0) | PU)
+#define GPH9_CLOCKOUT0 (PIN(7,9) | FUNC(2) | PU)
+#define GPH9_GPIO (PIN(7,9) | FUNC(0) | PU)
+#define GPH10_CLKOUT1 (PIN(7,10) | FUNC(2) | PU)
+#define GPH10_GPIO (PIN(7,10) | FUNC(0) | PU)
+
+#ifdef CONFIG_CPU_S3C2440
+/*
+ * Group 1: GPIO 256..287
+ * Used GPIO: 0...12
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPJ0_CAMDATA0 (PIN(8,0) | FUNC(2) | PU)
+#define GPJ0_GPIO (PIN(8,0) | FUNC(0) | PU)
+#define GPJ1_CAMDATA1 (PIN(8,1) | FUNC(2) | PU)
+#define GPJ1_GPIO (PIN(8,1) | FUNC(0) | PU)
+#define GPJ2_CAMDATA2 (PIN(8,2) | FUNC(2) | PU)
+#define GPJ2_GPIO (PIN(8,2) | FUNC(0) | PU)
+#define GPJ3_CAMDATA3 (PIN(8,3) | FUNC(2) | PU)
+#define GPJ3_GPIO (PIN(8,3) | FUNC(0) | PU)
+#define GPJ4_CAMDATA4 (PIN(8,4) | FUNC(2) | PU)
+#define GPJ4_GPIO (PIN(8,4) | FUNC(0) | PU)
+#define GPJ5_CAMDATA5 (PIN(8,5) | FUNC(2) | PU)
+#define GPJ5_GPIO (PIN(8,5) | FUNC(0) | PU)
+#define GPJ6_CAMDATA6 (PIN(8,6) | FUNC(2) | PU)
+#define GPJ6_GPIO (PIN(8,6) | FUNC(0) | PU)
+#define GPJ7_CAMDATA7 (PIN(8,7) | FUNC(2) | PU)
+#define GPJ7_GPIO (PIN(8,7) | FUNC(0) | PU)
+#define GPJ8_CAMPCLK (PIN(8,8) | FUNC(2) | PU)
+#define GPJ8_GPIO (PIN(8,8) | FUNC(0) | PU)
+#define GPJ9_CAMVSYNC (PIN(8,9) | FUNC(2) | PU)
+#define GPJ9_GPIO (PIN(8,9) | FUNC(0) | PU)
+#define GPJ10_CAMHREF (PIN(8,10) | FUNC(2) | PU)
+#define GPJ10_GPIO (PIN(8,10) | FUNC(0) | PU)
+#define GPJ11_CAMCLKOUT (PIN(8,11) | FUNC(2) | PU)
+#define GPJ11_GPIO (PIN(8,11) | FUNC(0) | PU)
+#define GPJ12_CAMRESET (PIN(8,12) | FUNC(0) | PU)
+#define GPJ12_GPIO (PIN(8,12) | FUNC(0) | PU)
+
+#endif
+
+#endif /* __MACH_IOMUX_S3C24x0_H */
diff --git a/arch/arm/mach-samsung/include/mach/mci.h b/arch/arm/mach-samsung/include/mach/mci.h
new file mode 100644
index 0000000..6ba8961
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/mci.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is partially based on u-boot code:
+ *
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MMC_H_
+#define __MACH_MMC_H_
+
+struct s3c_mci_platform_data {
+ unsigned caps; /**< supported operating modes (MMC_MODE_*) */
+ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
+ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
+ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
+ /* TODO */
+ /* function to modify the voltage */
+ /* function to switch the voltage */
+ /* function to detect the presence of a SD card in the socket */
+ unsigned gpio_detect;
+ unsigned detect_invert;
+};
+
+#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
new file mode 100644
index 0000000..a990d80
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* S3C2410 device base addresses */
+#define S3C24X0_SDRAM_BASE 0x30000000
+#define S3C24X0_SDRAM_END 0x40000000
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C2410_USB_HOST_BASE 0x49000000
+#define S3C2410_INTERRUPT_BASE 0x4A000000
+#define S3C2410_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C2410_LCD_BASE 0x4D000000
+#define S3C24X0_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C2410_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C2410_I2C_BASE 0x54000000
+#define S3C2410_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C2410_RTC_BASE 0x57000000
+#define S3C2410_ADC_BASE 0x58000000
+#define S3C2410_SPI_BASE 0x59000000
+#define S3C2410_SDI_BASE 0x5A000000
+
+/* Clock control (direct access) */
+
+#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
+#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
+#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
+#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
+#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
+#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
+
+/* Timer (direct access) */
+#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
+#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
+#define TCON (S3C24X0_TIMER_BASE + 0x08)
+#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
+#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
+#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
+#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
+#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
+#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
+#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
+#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
+#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
+#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
+#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
+#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
+#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
+#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
+
+/* Watchdog (direct access) */
+#define WTCON (S3C24X0_WATCHDOG_BASE)
+#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
+#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
+
+/*
+ * if we are booting from NAND, its internal SRAM occures at
+ * a different address than without this feature
+ */
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+# define NFC_RAM_AREA 0x00000000
+#else
+# define NFC_RAM_AREA 0x40000000
+#endif
+#define NFC_RAM_SIZE 4096
+
+/* internal UARTs (driver based) */
+#define UART1_BASE (S3C24X0_UART_BASE)
+#define UART1_SIZE 0x4000
+#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
+#define UART2_SIZE 0x4000
+#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
+#define UART3_SIZE 0x4000
+
+/* CS configuration (direct access) */
+#define BWSCON (S3C24X0_MEMCTL_BASE)
+#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
+#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
+#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
+#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
+#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
+#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
+#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
+#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
+#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
+#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
+#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
+#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
+
+/* GPIO registers (direct access) */
+#define GPACON (S3C24X0_GPIO_BASE)
+#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
+
+#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
+#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
+#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
+
+#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
+#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
+#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
+
+#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
+#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
+#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
+
+#define GPECON (S3C24X0_GPIO_BASE + 0x40)
+#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
+#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
+
+#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
+#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
+#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
+
+#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
+#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
+#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
+
+#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
+#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
+#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
+
+#ifdef CONFIG_CPU_S3C2440
+# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
+# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
+# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
+#endif
+
+#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
+#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
+#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
+#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
+#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
+#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
+#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
+#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
+#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
+#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
+#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
+#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
+#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
+#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
+#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
+#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
+
+#ifdef CONFIG_CPU_S3C2440
+# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
+# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
+#endif
+
+/* external IO space */
+#define CS0_BASE 0x00000000
+#define CS1_BASE 0x08000000
+#define CS2_BASE 0x10000000
+#define CS3_BASE 0x18000000
+#define CS4_BASE 0x20000000
+#define CS5_BASE 0x28000000
+#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h b/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
new file mode 100644
index 0000000..7610b4e
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+extern void s3c24x0_nand_load_image(void*, int, int);
+#endif
+
+/**
+ * Locate the timing bits for the NFCONF register
+ * @param setup is the TACLS clock count
+ * @param access is the TWRPH0 clock count
+ * @param hold is the TWRPH1 clock count
+ *
+ * @note A clock count of 0 means always 1 HCLK clock.
+ * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
+ */
+#ifdef CONFIG_CPU_S3C2410
+# define CALC_NFCONF_TIMING(setup, access, hold) \
+ ((setup << 8) + (access << 4) + (hold << 0))
+#endif
+#ifdef CONFIG_CPU_S3C2440
+# define CALC_NFCONF_TIMING(setup, access, hold) \
+ ((setup << 12) + (access << 8) + (hold << 4))
+#endif
+
+/**
+ * Define platform specific data for the NAND controller and its device
+ */
+struct s3c24x0_nand_platform_data {
+ uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */
+ char flash_bbt; /**< force a flash based BBT */
+};
+
+/**
+ * @file
+ * @brief Basic declaration to use the s3c24x0 NAND driver
+ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h b/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
new file mode 100644
index 0000000..b8abcf1
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009
+ * Juergen Beisert, Pengutronix
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+uint32_t s3c24xx_get_mpllclk(void);
+uint32_t s3c24xx_get_upllclk(void);
+uint32_t s3c24xx_get_fclk(void);
+uint32_t s3c24xx_get_hclk(void);
+uint32_t s3c24xx_get_pclk(void);
+uint32_t s3c24xx_get_uclk(void);
+uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
new file mode 100644
index 0000000..e8004e5
--- /dev/null
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2009
+ * Juergen Beisert <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <mach/s3c24x0-iomap.h>
+
+ .section ".text_bare_init.s3c24x0_disable_wd","ax"
+
+/*
+ * Disable the watchdog, else it continues to bark
+ */
+.globl s3c24x0_disable_wd
+s3c24x0_disable_wd:
+
+ ldr r0, =S3C24X0_WATCHDOG_BASE
+ mov r1, #0x0
+ str r1, [r0]
+ mov pc, lr
+
+/**
+@page dev_s3c24xx_wd_handling Watchdog handling
+
+The watchdog must be disabled very early, because if it resets the system
+it is still active and will continue to reset the system. So, call this
+routine very early in your board_init_lowlevel routine.
+*/
+
+/*
+ * S3C2410 PLL configuration
+ * -------------------------
+ *
+ * Basic frequency calculation
+ *
+ * m * REFclk s = SDIV
+ * PLLclk = ------------ p = PDIV + 2
+ * p * 2^s m = MDIV + 8
+ *
+ * After reset the PLL of the s3c2410 processor uses:
+ *
+ * MPLL UPLL
+ * MDIV 0x5c 0x28
+ * PDIV 0x08 0x08
+ * SDIV 0x0 0x0
+ *
+ * 100 * 12MHz 1200MHz
+ * MPLLclk = ------------- = -------- = 120MHz
+ * 10 * 2^0 10
+ *
+ * 48 * 12MHz 576MHz
+ * UPLLclk = ------------- = -------- = 57,6MHz
+ * 10 * 2^0 10
+ *
+ * Note: Do not use "r10" here in this code
+ */
+
+#ifdef CONFIG_S3C24XX_PLL_INIT
+
+ .section ".text_bare_init.s3c24x0_pll_init","ax"
+
+.globl s3c24x0_pll_init
+s3c24x0_pll_init:
+
+ mov r0, #S3C24X0_CLOCK_POWER_BASE
+
+ /* configure internal clock ratio */
+ mov r1, #BOARD_SPECIFIC_CLKDIVN
+ str r1, [r0, #20]
+
+ /* enable all devices on this chip */
+ mov r1, #0xFFFFFFF0
+ str r1, [r0, #12]
+
+ /* ??????? */
+#ifdef CONFIG_CPU_S3C2440
+ mov r1, #0xFFFFFFFF
+#endif
+#ifdef CONFIG_CPU_S3C2410
+ mov r1, #0x00FFFFFF
+#endif
+ str r1, [r0, #0]
+
+#ifdef CONFIG_CPU_S3C2440
+ /*
+ * Most of the time HDIVN is not 0, so we must use the
+ * asynchronous bus mode (refer datasheet "Clock and Power Management")
+ */
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, #0xc0000000
+ mcr p15, 0, r1, c1, c0, 0
+#endif
+
+ /* configure UPLL */
+ ldr r1, =BOARD_SPECIFIC_UPLL
+ str r1, [r0, #8]
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* configure MPLL */
+ ldr r1, =BOARD_SPECIFIC_MPLL
+ str r1, [r0, #4]
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ mov pc, lr
+
+#endif
+
+/**
+@page dev_s3c24xx_pll_handling PLL clock handling
+
+To control the speed of your machine the PLLs must be reconfigured after reset.
+
+For example the S3C2410 CPU wakes up after reset at 120MHz main PLL speed,
+shared with all other system on chip components. Most of the time this
+configuration is to slow for the CPU and to fast for the other components.
+
+PLL reprogramming can be done in the machine specific manner very early when
+the CONFIG_S3C24XX_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
+defined. The board must provide a board_init_lowlevel() assembler function in
+this case and calling the s3c24x0_pll_init() assembler function.
+
+If the s3c24x0_pll_init() is called a few further symbols must be defined to
+setup the correct values for the machine.
+
+Define in the machine specific config.h the following symbols:
+
+- S3C24XX_CLOCK_REFERENCE with the frequency in Hz of your reference crystal.
+- BOARD_SPECIFIC_CLKDIVN with the value for the main clock ratio register (CLKDIVN)
+- BOARD_SPECIFIC_MPLL with the value for the main PLL setup register
+- BOARD_SPECIFIC_UPLL with the value for the USB PLL setup register
+
+@note Valid values for the PLL settings can be found in the CPU manual.
+
+@par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs) and S3C2440 (UPLL only)
+
+@f[
+ f_{PLL} = \frac{m * f_{Ref}}{p * 2^s}
+@f]
+
+With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
+
+@par Background: PLL frequency calculation for the S3C2440 CPU (MPLL only)
+
+@f[
+ f_{PLL} = \frac{2 * m * f_{Ref}}{p * 2^s}
+@f]
+
+With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
+
+@note This routine can be used for the S3C2410 and the S3C2440 CPU.
+
+*/
+
+/* ----------------------------------------------------------------------- */
+
+#ifdef CONFIG_S3C24XX_SDRAM_INIT
+
+ .section ".text_bare_init.s3c24x0_sdram_init","ax"
+
+ .globl s3c24x0_sdram_init
+s3c24x0_sdram_init:
+
+ adr r0, SDRAMDATA /* get the current relative address of the table */
+ mov r1, #S3C24X0_MEMCTL_BASE
+ mov r2, #6 /* we *know* it contains 6 entries */
+
+ ldr r3, [r0], #4 /* write BSWCON first */
+ str r3, [r1], #0x1c /* post add register offset for bank6 */
+/*
+ * Initializing the SDRAM controller is very simple:
+ * Just write some useful values into the SDRAM controller.
+ */
+0: ldr r3, [r0], #4
+ str r3, [r1], #4
+ subs r2, r2, #1
+ bne 0b
+
+ mov pc, lr
+
+SDRAMDATA:
+ .word BOARD_SPECIFIC_BWSCON
+ .word BOARD_SPECIFIC_BANKCON6
+ .word BOARD_SPECIFIC_BANKCON7
+ .word BOARD_SPECIFIC_REFRESH
+ .word BOARD_SPECIFIC_BANKSIZE
+ .word BOARD_SPECIFIC_MRSRB6
+ .word BOARD_SPECIFIC_MRSRB7
+
+#endif
+
+/**
+@page dev_s3c24xx_sdram_handling SDRAM controller initialisation
+
+The SDRAM controller is very simple and its initialisation requires only a
+few steps. barebox provides a generic routine to do this step.
+
+Enable CONFIG_S3C24XX_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
+to call the generic s3c24x0_sdram_init() assembler function from within the
+machine specific board_init_lowlevel() assembler function.
+
+To use the s3c24x0_sdram_init() assembler function a few symbols must be
+defined to setup correct values for the machine.
+
+Define in the machine specific config.h the following list of symbols:
+
+- BOARD_SPECIFIC_BWSCON with the values for SDRAM banks 6 and 7
+- BOARD_SPECIFIC_BANKCON6 with the value for the BANKCON6 register
+- BOARD_SPECIFIC_BANKCON7 with the value for the BANKCON7 register
+- BOARD_SPECIFIC_REFRESH with the value for the REFRESH register
+- BOARD_SPECIFIC_BANKSIZE with the value for the BANKSIZE register
+- BOARD_SPECIFIC_MRSRB6 with the value for the MRSRB6 register
+- BOARD_SPECIFIC_MRSRB7 with the value for the MRSRB7 register
+*/
+
+/* ----------------------------------------------------------------------- */
+
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+
+ .section ".text_bare_init.s3c24x0_nand_boot","ax"
+
+ .globl s3c24x0_nand_boot
+s3c24x0_nand_boot:
+/*
+ * In the case of NOR boot we are running from the same address space.
+ * Detect this case to handle it correctly.
+ */
+ mov r1, #S3C24X0_MEMCTL_BASE
+ ldr r3, [r1]
+ and r3, r3, #0x6
+ cmp r3, #0x0 /* check for NAND case */
+ beq 2f
+ mov pc, lr /* NOR case: nothing to do here */
+
+2: ldr sp, =TEXT_BASE /* Setup a temporary stack in SDRAM */
+/*
+ * We still run at a location we are not linked to. But lets still running
+ * from the internal SRAM, this may speed up the boot
+ */
+ push {lr}
+ bl nand_boot
+ pop {lr}
+/*
+ * Adjust the return address to the correct address in SDRAM
+ */
+ ldr r1, =TEXT_BASE
+ add lr, lr, r1
+
+ mov pc, lr
+
+#endif
+
+/**
+@page dev_s3c24xx_nandboot_handling Booting from NAND
+
+To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
+enable CONFIG_S3C24XX_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
+able to call the s3c24x0_nand_boot() assembler routine from within the
+machine specific board_init_lowlevel() assembler function.
+
+@note This routine assumes an already working SDRAM controller and
+an initialized stack pointer.
+
+@note Basicly this routine runs from inside the internal SRAM. After load of
+the whole barebox image from the NAND flash memory into the SDRAM it adjusts
+the link register to the final SDRAM adress and returns.
+
+@note In the NAND boot mode, ECC is not checked. So, the first x KBytes used
+by barebox should have no bit error.
+
+Due to the fact the code to load the whole barebox from NAND must fit into
+the first 4kiB of the barebox image, the shrinked NAND driver is very
+minimalistic. Setup the NAND access timing is done in a safe manner, what
+means: Slowest possible values are used. If you want to increase the speed you
+should define the BOARD_DEFAULT_NAND_TIMING to a valid setting into the
+NFCONF register and add it to your board specific config.h. Refer S3C24x0's
+datasheet for further details. The macro #CALC_NFCONF_TIMING could help to
+calculate the register setting in a hardware independent manner.
+
+@note The regular NAND driver uses a platform data structure to define the
+NAND access timings.
+
+@note Its still possible to boot this image from NOR memory. If this routine
+detects it is running from NOR instead of the internal SRAM it skips any
+loading and returns immediately.
+
+*/
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
2011-12-25 20:38 ` [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates Juergen Beisert
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 88d45fe..f329cdb 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,2 +1,3 @@
-obj-y += generic.o gpio-s3c24x0.o
+obj-y += generic.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
2011-12-25 20:38 ` [PATCH 01/14] MACH SAMSUNG: Rename the whole mach to add more CPUs in future Juergen Beisert
2011-12-25 20:38 ` [PATCH 02/14] MACH SAMSUNG/S3C: Do not compile S3C24xx's GPIO support unconditionally Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage Juergen Beisert
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Start with renaming files to share them in the S3C CPU family,
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2410/lowlevel_init.S | 2 +-
arch/arm/boards/a9m2440/a9m2410dev.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 4 +-
arch/arm/boards/a9m2440/lowlevel_init.S | 2 +-
arch/arm/boards/mini2440/lowlevel_init.S | 2 +-
arch/arm/boards/mini2440/mini2440.c | 4 +-
arch/arm/mach-samsung/generic.c | 2 +-
arch/arm/mach-samsung/gpio-s3c24x0.c | 2 +-
arch/arm/mach-samsung/include/mach/gpio.h | 7 +-
arch/arm/mach-samsung/include/mach/s3c-generic.h | 33 ++++
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 177 ++++++++++++++++++++
arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h | 177 --------------------
.../mach-samsung/include/mach/s3c24xx-generic.h | 33 ----
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
drivers/mci/s3c.c | 4 +-
drivers/mtd/nand/nand_s3c2410.c | 4 +-
drivers/serial/serial_s3c24x0.c | 4 +-
drivers/video/s3c.c | 2 +-
19 files changed, 230 insertions(+), 235 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-generic.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-iomap.h
delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index bbe1604..14eaa1b 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,7 +32,7 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
index 461b93c..752c668 100644
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ b/arch/arm/boards/a9m2410/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index 5f7c53b..aa5da88 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -28,7 +28,7 @@
#include <driver.h>
#include <init.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 964d376..9002052 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,9 +32,9 @@
#include <partition.h>
#include <nand.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include "baseboards.h"
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index 4b5c596..bfdd7f0 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S b/arch/arm/boards/mini2440/lowlevel_init.S
index 41f50cb..f114bb7 100644
--- a/arch/arm/boards/mini2440/lowlevel_init.S
+++ b/arch/arm/boards/mini2440/lowlevel_init.S
@@ -3,7 +3,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.board_init_lowlevel","ax"
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index b4cc0f8..5e6910b 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -38,9 +38,9 @@
#include <asm/armlinux.h>
#include <io.h>
#include <mach/gpio.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include <mach/mci.h>
#include <mach/fb.h>
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index d2f2ac7..3c24b1a 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -27,7 +27,7 @@
#include <init.h>
#include <clock.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
/**
* Calculate the current M-PLL clock.
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
index 946ec33..23b2609 100644
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ b/arch/arm/mach-samsung/gpio-s3c24x0.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <errno.h>
#include <io.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
#include <mach/gpio.h>
static const unsigned char group_offset[] =
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
index 37db4f5..3723394 100644
--- a/arch/arm/mach-samsung/include/mach/gpio.h
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -8,17 +8,12 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#ifndef __ASM_MACH_GPIO_H
#define __ASM_MACH_GPIO_H
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410)
+#ifdef CONFIG_ARCH_S3C24xx
# include <mach/iomux-s3c24x0.h>
#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
new file mode 100644
index 0000000..b8abcf1
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009
+ * Juergen Beisert, Pengutronix
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+uint32_t s3c24xx_get_mpllclk(void);
+uint32_t s3c24xx_get_upllclk(void);
+uint32_t s3c24xx_get_fclk(void);
+uint32_t s3c24xx_get_hclk(void);
+uint32_t s3c24xx_get_pclk(void);
+uint32_t s3c24xx_get_uclk(void);
+uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
new file mode 100644
index 0000000..a990d80
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* S3C2410 device base addresses */
+#define S3C24X0_SDRAM_BASE 0x30000000
+#define S3C24X0_SDRAM_END 0x40000000
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C2410_USB_HOST_BASE 0x49000000
+#define S3C2410_INTERRUPT_BASE 0x4A000000
+#define S3C2410_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C2410_LCD_BASE 0x4D000000
+#define S3C24X0_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C2410_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C2410_I2C_BASE 0x54000000
+#define S3C2410_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C2410_RTC_BASE 0x57000000
+#define S3C2410_ADC_BASE 0x58000000
+#define S3C2410_SPI_BASE 0x59000000
+#define S3C2410_SDI_BASE 0x5A000000
+
+/* Clock control (direct access) */
+
+#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
+#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
+#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
+#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
+#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
+#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
+
+/* Timer (direct access) */
+#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
+#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
+#define TCON (S3C24X0_TIMER_BASE + 0x08)
+#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
+#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
+#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
+#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
+#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
+#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
+#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
+#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
+#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
+#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
+#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
+#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
+#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
+#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
+
+/* Watchdog (direct access) */
+#define WTCON (S3C24X0_WATCHDOG_BASE)
+#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
+#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
+
+/*
+ * if we are booting from NAND, its internal SRAM occures at
+ * a different address than without this feature
+ */
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+# define NFC_RAM_AREA 0x00000000
+#else
+# define NFC_RAM_AREA 0x40000000
+#endif
+#define NFC_RAM_SIZE 4096
+
+/* internal UARTs (driver based) */
+#define UART1_BASE (S3C24X0_UART_BASE)
+#define UART1_SIZE 0x4000
+#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
+#define UART2_SIZE 0x4000
+#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
+#define UART3_SIZE 0x4000
+
+/* CS configuration (direct access) */
+#define BWSCON (S3C24X0_MEMCTL_BASE)
+#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
+#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
+#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
+#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
+#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
+#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
+#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
+#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
+#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
+#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
+#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
+#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
+
+/* GPIO registers (direct access) */
+#define GPACON (S3C24X0_GPIO_BASE)
+#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
+
+#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
+#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
+#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
+
+#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
+#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
+#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
+
+#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
+#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
+#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
+
+#define GPECON (S3C24X0_GPIO_BASE + 0x40)
+#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
+#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
+
+#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
+#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
+#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
+
+#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
+#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
+#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
+
+#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
+#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
+#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
+
+#ifdef CONFIG_CPU_S3C2440
+# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
+# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
+# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
+#endif
+
+#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
+#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
+#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
+#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
+#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
+#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
+#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
+#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
+#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
+#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
+#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
+#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
+#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
+#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
+#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
+#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
+
+#ifdef CONFIG_CPU_S3C2440
+# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
+# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
+#endif
+
+/* external IO space */
+#define CS0_BASE 0x00000000
+#define CS1_BASE 0x08000000
+#define CS2_BASE 0x10000000
+#define CS3_BASE 0x18000000
+#define CS4_BASE 0x20000000
+#define CS5_BASE 0x28000000
+#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
deleted file mode 100644
index a990d80..0000000
--- a/arch/arm/mach-samsung/include/mach/s3c24x0-iomap.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/* S3C2410 device base addresses */
-#define S3C24X0_SDRAM_BASE 0x30000000
-#define S3C24X0_SDRAM_END 0x40000000
-#define S3C24X0_MEMCTL_BASE 0x48000000
-#define S3C2410_USB_HOST_BASE 0x49000000
-#define S3C2410_INTERRUPT_BASE 0x4A000000
-#define S3C2410_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
-#define S3C2410_LCD_BASE 0x4D000000
-#define S3C24X0_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
-#define S3C2410_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
-#define S3C2410_I2C_BASE 0x54000000
-#define S3C2410_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
-#define S3C2410_RTC_BASE 0x57000000
-#define S3C2410_ADC_BASE 0x58000000
-#define S3C2410_SPI_BASE 0x59000000
-#define S3C2410_SDI_BASE 0x5A000000
-
-/* Clock control (direct access) */
-
-#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
-#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
-#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
-#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
-#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
-#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
-
-/* Timer (direct access) */
-#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
-#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
-#define TCON (S3C24X0_TIMER_BASE + 0x08)
-#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
-#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
-#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
-#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
-#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
-#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
-#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
-#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
-#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
-#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
-#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
-#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
-#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
-#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
-
-/* Watchdog (direct access) */
-#define WTCON (S3C24X0_WATCHDOG_BASE)
-#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
-#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
-
-/*
- * if we are booting from NAND, its internal SRAM occures at
- * a different address than without this feature
- */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-# define NFC_RAM_AREA 0x00000000
-#else
-# define NFC_RAM_AREA 0x40000000
-#endif
-#define NFC_RAM_SIZE 4096
-
-/* internal UARTs (driver based) */
-#define UART1_BASE (S3C24X0_UART_BASE)
-#define UART1_SIZE 0x4000
-#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
-#define UART2_SIZE 0x4000
-#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
-#define UART3_SIZE 0x4000
-
-/* CS configuration (direct access) */
-#define BWSCON (S3C24X0_MEMCTL_BASE)
-#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
-#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
-#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
-#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
-#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
-#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
-#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
-#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
-#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
-#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
-#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
-#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
-
-/* GPIO registers (direct access) */
-#define GPACON (S3C24X0_GPIO_BASE)
-#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
-
-#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
-#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
-#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
-
-#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
-#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
-#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
-
-#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
-#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
-#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
-
-#define GPECON (S3C24X0_GPIO_BASE + 0x40)
-#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
-#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
-
-#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
-#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
-#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
-
-#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
-#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
-#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
-
-#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
-#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
-#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
-# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
-# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
-#endif
-
-#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
-#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
-#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
-#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
-#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
-#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
-#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
-#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
-#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
-#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
-#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
-#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
-#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
-#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
-#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
-#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
-# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
-#endif
-
-/* external IO space */
-#define CS0_BASE 0x00000000
-#define CS1_BASE 0x08000000
-#define CS2_BASE 0x10000000
-#define CS3_BASE 0x18000000
-#define CS4_BASE 0x20000000
-#define CS5_BASE 0x28000000
-#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h b/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
deleted file mode 100644
index b8abcf1..0000000
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-generic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2009
- * Juergen Beisert, Pengutronix
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-uint32_t s3c24xx_get_mpllclk(void);
-uint32_t s3c24xx_get_upllclk(void);
-uint32_t s3c24xx_get_fclk(void);
-uint32_t s3c24xx_get_hclk(void);
-uint32_t s3c24xx_get_pclk(void);
-uint32_t s3c24xx_get_uclk(void);
-uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index e8004e5..8529283 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -19,7 +19,7 @@
*/
#include <config.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-iomap.h>
.section ".text_bare_init.s3c24x0_disable_wd","ax"
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index 89c8168..c877e09 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -41,8 +41,8 @@
#include <clock.h>
#include <io.h>
#include <mach/mci.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
#define SDICON 0x0
# define SDICON_SDRESET (1 << 8)
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index ed45788..3117614 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -30,8 +30,8 @@
#include <init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
#include <mach/s3c24x0-nand.h>
#include <io.h>
#include <asm-generic/errno.h>
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 1e27d48..4e95e5c 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -25,8 +25,8 @@
#include <init.h>
#include <malloc.h>
#include <io.h>
-#include <mach/s3c24xx-generic.h>
-#include <mach/s3c24x0-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
/* Note: Offsets are for little endian access */
#define ULCON 0x00 /* line control */
diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c
index b17aeb6..a03ec3d 100644
--- a/drivers/video/s3c.c
+++ b/drivers/video/s3c.c
@@ -31,7 +31,7 @@
#include <errno.h>
#include <io.h>
#include <mach/gpio.h>
-#include <mach/s3c24xx-generic.h>
+#include <mach/s3c-generic.h>
#include <mach/fb.h>
#define LCDCON1 0x00
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (2 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 03/14] MACH SAMSUNG/S3C: Make it more generic for future updates Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family Juergen Beisert
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
The aready existing NAND controller driver in Barebox is for the S3C24XX family
only. Change the name of the file to reflect this fact (and free the way to add
more recent Samsung NAND controllers)
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 2 +-
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/Kconfig | 2 +-
arch/arm/mach-samsung/include/mach/s3c24x0-nand.h | 54 --
arch/arm/mach-samsung/include/mach/s3c24xx-nand.h | 54 ++
drivers/mtd/nand/Kconfig | 4 +-
drivers/mtd/nand/Makefile | 2 +-
drivers/mtd/nand/nand_s3c2410.c | 665 ---------------------
drivers/mtd/nand/nand_s3c24xx.c | 665 +++++++++++++++++++++
10 files changed, 726 insertions(+), 726 deletions(-)
delete mode 100644 arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
delete mode 100644 drivers/mtd/nand/nand_s3c2410.c
create mode 100644 drivers/mtd/nand/nand_s3c24xx.c
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 14eaa1b..989dcf7 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -33,7 +33,7 @@
#include <nand.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 9002052..1986efb 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -33,7 +33,7 @@
#include <nand.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include "baseboards.h"
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 5e6910b..dca9083 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,7 +39,7 @@
#include <io.h>
#include <mach/gpio.h>
#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
+#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/mci.h>
#include <mach/fb.h>
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index a800cb8..bc283dc 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -105,7 +105,7 @@ config S3C24XX_NAND_BOOT
prompt "Booting from NAND"
select MTD
select NAND
- select NAND_S3C24X0
+ select NAND_S3C24XX
help
Add generic support to boot from NAND flash. Image loading will be
skipped if the code is running from NOR or already from SDRAM.
diff --git a/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h b/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
deleted file mode 100644
index 7610b4e..0000000
--- a/arch/arm/mach-samsung/include/mach/s3c24x0-nand.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-extern void s3c24x0_nand_load_image(void*, int, int);
-#endif
-
-/**
- * Locate the timing bits for the NFCONF register
- * @param setup is the TACLS clock count
- * @param access is the TWRPH0 clock count
- * @param hold is the TWRPH1 clock count
- *
- * @note A clock count of 0 means always 1 HCLK clock.
- * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
- */
-#ifdef CONFIG_CPU_S3C2410
-# define CALC_NFCONF_TIMING(setup, access, hold) \
- ((setup << 8) + (access << 4) + (hold << 0))
-#endif
-#ifdef CONFIG_CPU_S3C2440
-# define CALC_NFCONF_TIMING(setup, access, hold) \
- ((setup << 12) + (access << 8) + (hold << 4))
-#endif
-
-/**
- * Define platform specific data for the NAND controller and its device
- */
-struct s3c24x0_nand_platform_data {
- uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */
- char flash_bbt; /**< force a flash based BBT */
-};
-
-/**
- * @file
- * @brief Basic declaration to use the s3c24x0 NAND driver
- */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
new file mode 100644
index 0000000..7610b4e
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+extern void s3c24x0_nand_load_image(void*, int, int);
+#endif
+
+/**
+ * Locate the timing bits for the NFCONF register
+ * @param setup is the TACLS clock count
+ * @param access is the TWRPH0 clock count
+ * @param hold is the TWRPH1 clock count
+ *
+ * @note A clock count of 0 means always 1 HCLK clock.
+ * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed
+ */
+#ifdef CONFIG_CPU_S3C2410
+# define CALC_NFCONF_TIMING(setup, access, hold) \
+ ((setup << 8) + (access << 4) + (hold << 0))
+#endif
+#ifdef CONFIG_CPU_S3C2440
+# define CALC_NFCONF_TIMING(setup, access, hold) \
+ ((setup << 12) + (access << 8) + (hold << 4))
+#endif
+
+/**
+ * Define platform specific data for the NAND controller and its device
+ */
+struct s3c24x0_nand_platform_data {
+ uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */
+ char flash_bbt; /**< force a flash based BBT */
+};
+
+/**
+ * @file
+ * @brief Basic declaration to use the s3c24x0 NAND driver
+ */
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index bda0529..926a64b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -65,9 +65,9 @@ config NAND_ATMEL
prompt "Atmel (AT91SAM9xxx) NAND driver"
depends on ARCH_AT91
-config NAND_S3C24X0
+config NAND_S3C24XX
bool
- prompt "Samsung S3C24X0 NAND driver"
+ prompt "Samsung S3C24XX NAND driver"
depends on ARCH_S3C24xx
help
Add support for processor's NAND device controller.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 00b7b27..5c6d8b3 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -14,4 +14,4 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
-obj-$(CONFIG_NAND_S3C24X0) += nand_s3c2410.o
+obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
deleted file mode 100644
index 3117614..0000000
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ /dev/null
@@ -1,665 +0,0 @@
-/* linux/drivers/mtd/nand/s3c2410.c
- *
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
- *
- * Copyright © 2004-2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C2410 NAND driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <driver.h>
-#include <malloc.h>
-#include <init.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c24x0-nand.h>
-#include <io.h>
-#include <asm-generic/errno.h>
-
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-# define __nand_boot_init __bare_init
-# ifndef BOARD_DEFAULT_NAND_TIMING
-# define BOARD_DEFAULT_NAND_TIMING 0x0737
-# endif
-#else
-# define __nand_boot_init
-#endif
-
-/**
- * Define this symbol for testing purpose. It will add a command to read an
- * image from the NAND like it the boot strap code will do.
- */
-#define CONFIG_NAND_S3C24XX_BOOT_DEBUG
-
-/* NAND controller's register */
-
-#define NFCONF 0x00
-
-#ifdef CONFIG_CPU_S3C2410
-
-#define NFCMD 0x04
-#define NFADDR 0x08
-#define NFDATA 0x0c
-#define NFSTAT 0x10
-#define NFECC 0x14
-
-/* S3C2410 specific bits */
-#define NFSTAT_BUSY (1)
-#define NFCONF_nFCE (1 << 11)
-#define NFCONF_INITECC (1 << 12)
-#define NFCONF_EN (1 << 15)
-
-#endif /* CONFIG_CPU_S3C2410 */
-
-#ifdef CONFIG_CPU_S3C2440
-
-#define NFCONT 0x04
-#define NFCMD 0x08
-#define NFADDR 0x0C
-#define NFDATA 0x10
-#define NFSTAT 0x20
-#define NFECC 0x2C
-
-/* S3C2440 specific bits */
-#define NFSTAT_BUSY (1)
-#define NFCONT_nFCE (1 << 1)
-#define NFCONT_INITECC (1 << 4)
-#define NFCONT_EN (1)
-
-#endif /* CONFIG_CPU_S3C2440 */
-
-
-struct s3c24x0_nand_host {
- struct mtd_info mtd;
- struct nand_chip nand;
- struct mtd_partition *parts;
- struct device_d *dev;
-
- void __iomem *base;
-};
-
-/**
- * oob placement block for use with hardware ecc generation on small page
- */
-static struct nand_ecclayout nand_hw_eccoob = {
- .eccbytes = 3,
- .eccpos = { 0, 1, 2},
- .oobfree = {
- {
- .offset = 8,
- .length = 8
- }
- }
-};
-
-/* - Functions shared between the boot strap code and the regular driver - */
-
-/**
- * Issue the specified command to the NAND device
- * @param[in] host Base address of the NAND controller
- * @param[in] cmd Command for NAND flash
- */
-static void __nand_boot_init send_cmd(void __iomem *host, uint8_t cmd)
-{
- writeb(cmd, host + NFCMD);
-}
-
-/**
- * Issue the specified address to the NAND device
- * @param[in] host Base address of the NAND controller
- * @param[in] addr Address for the NAND flash
- */
-static void __nand_boot_init send_addr(void __iomem *host, uint8_t addr)
-{
- writeb(addr, host + NFADDR);
-}
-
-/**
- * Enable the NAND flash access
- * @param[in] host Base address of the NAND controller
- */
-static void __nand_boot_init enable_cs(void __iomem *host)
-{
-#ifdef CONFIG_CPU_S3C2410
- writew(readw(host + NFCONF) & ~NFCONF_nFCE, host + NFCONF);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- writew(readw(host + NFCONT) & ~NFCONT_nFCE, host + NFCONT);
-#endif
-}
-
-/**
- * Disable the NAND flash access
- * @param[in] host Base address of the NAND controller
- */
-static void __nand_boot_init disable_cs(void __iomem *host)
-{
-#ifdef CONFIG_CPU_S3C2410
- writew(readw(host + NFCONF) | NFCONF_nFCE, host + NFCONF);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- writew(readw(host + NFCONT) | NFCONT_nFCE, host + NFCONT);
-#endif
-}
-
-/**
- * Enable the NAND flash controller
- * @param[in] host Base address of the NAND controller
- * @param[in] timing Timing to access the NAND memory
- */
-static void __nand_boot_init enable_nand_controller(void __iomem *host, uint32_t timing)
-{
-#ifdef CONFIG_CPU_S3C2410
- writew(timing + NFCONF_EN + NFCONF_nFCE, host + NFCONF);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- writew(NFCONT_EN + NFCONT_nFCE, host + NFCONT);
- writew(timing, host + NFCONF);
-#endif
-}
-
-/**
- * Diable the NAND flash controller
- * @param[in] host Base address of the NAND controller
- */
-static void __nand_boot_init disable_nand_controller(void __iomem *host)
-{
-#ifdef CONFIG_CPU_S3C2410
- writew(NFCONF_nFCE, host + NFCONF);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- writew(NFCONT_nFCE, host + NFCONT);
-#endif
-}
-
-/* ----------------------------------------------------------------------- */
-
-#ifdef CONFIG_CPU_S3C2440
-/**
- * Read one block of data from the NAND port
- * @param[in] mtd Instance data
- * @param[out] buf buffer to write data to
- * @param[in] len byte count
- *
- * This is a special block read variant for the S3C2440 CPU.
- */
-static void s3c2440_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
- readsl(host->base + NFDATA, buf, len >> 2);
-
- /* cleanup any fractional read */
- if (len & 3) {
- buf += len & ~3;
-
- for (; len & 3; len--)
- *buf++ = readb(host->base + NFDATA);
- }
-}
-
-/**
- * Write one block of data to the NAND port
- * @param[in] mtd Instance data
- * @param[out] buf buffer to read data from
- * @param[in] len byte count
- *
- * This is a special block write variant for the S3C2440 CPU.
- */
-static void s3c2440_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
- int len)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
- writesl(host->base + NFDATA, buf, len >> 2);
-
- /* cleanup any fractional write */
- if (len & 3) {
- buf += len & ~3;
-
- for (; len & 3; len--, buf++)
- writeb(*buf, host->base + NFDATA);
- }
-}
-#endif
-
-/**
- * Check the ECC and try to repair the data if possible
- * @param[in] mtd_info Not used
- * @param[inout] dat Pointer to the data buffer that might contain a bit error
- * @param[in] read_ecc ECC data from the OOB space
- * @param[in] calc_ecc ECC data calculated from the data
- * @return 0 no error, 1 repaired error, -1 no way...
- *
- * @note: This routine works always on a 24 bit ECC
- */
-static int s3c2410_nand_correct_data(struct mtd_info *mtd, uint8_t *dat,
- uint8_t *read_ecc, uint8_t *calc_ecc)
-{
- unsigned int diff0, diff1, diff2;
- unsigned int bit, byte;
-
- diff0 = read_ecc[0] ^ calc_ecc[0];
- diff1 = read_ecc[1] ^ calc_ecc[1];
- diff2 = read_ecc[2] ^ calc_ecc[2];
-
- if (diff0 == 0 && diff1 == 0 && diff2 == 0)
- return 0; /* ECC is ok */
-
- /* sometimes people do not think about using the ECC, so check
- * to see if we have an 0xff,0xff,0xff read ECC and then ignore
- * the error, on the assumption that this is an un-eccd page.
- */
- if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff)
- return 0;
-
- /* Can we correct this ECC (ie, one row and column change).
- * Note, this is similar to the 256 error code on smartmedia */
-
- if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
- ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
- ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
- /* calculate the bit position of the error */
-
- bit = ((diff2 >> 3) & 1) |
- ((diff2 >> 4) & 2) |
- ((diff2 >> 5) & 4);
-
- /* calculate the byte position of the error */
-
- byte = ((diff2 << 7) & 0x100) |
- ((diff1 << 0) & 0x80) |
- ((diff1 << 1) & 0x40) |
- ((diff1 << 2) & 0x20) |
- ((diff1 << 3) & 0x10) |
- ((diff0 >> 4) & 0x08) |
- ((diff0 >> 3) & 0x04) |
- ((diff0 >> 2) & 0x02) |
- ((diff0 >> 1) & 0x01);
-
- dat[byte] ^= (1 << bit);
- return 1;
- }
-
- /* if there is only one bit difference in the ECC, then
- * one of only a row or column parity has changed, which
- * means the error is most probably in the ECC itself */
-
- diff0 |= (diff1 << 8);
- diff0 |= (diff2 << 16);
-
- if ((diff0 & ~(1<<fls(diff0))) == 0)
- return 1;
-
- return -1;
-}
-
-static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
-#ifdef CONFIG_CPU_S3C2410
- writel(readl(host->base + NFCONF) | NFCONF_INITECC , host->base + NFCONF);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- writel(readl(host->base + NFCONT) | NFCONT_INITECC , host->base + NFCONT);
-#endif
-}
-
-static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
-#ifdef CONFIG_CPU_S3C2410
- ecc_code[0] = readb(host->base + NFECC);
- ecc_code[1] = readb(host->base + NFECC + 1);
- ecc_code[2] = readb(host->base + NFECC + 2);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- unsigned long ecc = readl(host->base + NFECC);
-
- ecc_code[0] = ecc;
- ecc_code[1] = ecc >> 8;
- ecc_code[2] = ecc >> 16;
-#endif
- return 0;
-}
-
-static void s3c24x0_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
- if (chip == -1)
- disable_cs(host->base);
- else
- enable_cs(host->base);
-}
-
-static int s3c24x0_nand_devready(struct mtd_info *mtd)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
- return readw(host->base + NFSTAT) & NFSTAT_BUSY;
-}
-
-static void s3c24x0_nand_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct s3c24x0_nand_host *host = nand_chip->priv;
-
- if (cmd == NAND_CMD_NONE)
- return;
- /*
- * If the CLE should be active, this call is a NAND command
- */
- if (ctrl & NAND_CLE)
- send_cmd(host->base, cmd);
- /*
- * If the ALE should be active, this call is a NAND address
- */
- if (ctrl & NAND_ALE)
- send_addr(host->base, cmd);
-}
-
-static int s3c24x0_nand_inithw(struct s3c24x0_nand_host *host)
-{
- struct s3c24x0_nand_platform_data *pdata = host->dev->platform_data;
- uint32_t tmp;
-
- /* reset the NAND controller */
- disable_nand_controller(host->base);
-
- if (pdata != NULL)
- tmp = pdata->nand_timing;
- else
- /* else slowest possible timing */
- tmp = CALC_NFCONF_TIMING(4, 8, 8);
-
- /* reenable the NAND controller */
- enable_nand_controller(host->base, tmp);
-
- return 0;
-}
-
-static int s3c24x0_nand_probe(struct device_d *dev)
-{
- struct nand_chip *chip;
- struct s3c24x0_nand_platform_data *pdata = dev->platform_data;
- struct mtd_info *mtd;
- struct s3c24x0_nand_host *host;
- int ret;
-
- /* Allocate memory for MTD device structure and private data */
- host = kzalloc(sizeof(struct s3c24x0_nand_host), GFP_KERNEL);
- if (!host)
- return -ENOMEM;
-
- host->dev = dev;
- host->base = dev_request_mem_region(dev, 0);
-
- /* structures must be linked */
- chip = &host->nand;
- mtd = &host->mtd;
- mtd->priv = chip;
-
- /* init the default settings */
-
- /* 50 us command delay time */
- chip->chip_delay = 50;
- chip->priv = host;
-
- chip->IO_ADDR_R = chip->IO_ADDR_W = host->base + NFDATA;
-
-#ifdef CONFIG_CPU_S3C2440
- chip->read_buf = s3c2440_nand_read_buf;
- chip->write_buf = s3c2440_nand_write_buf;
-#endif
- chip->cmd_ctrl = s3c24x0_nand_hwcontrol;
- chip->dev_ready = s3c24x0_nand_devready;
- chip->select_chip = s3c24x0_nand_select_chip;
-
- /* we are using the hardware ECC feature of this device */
- chip->ecc.calculate = s3c2410_nand_calculate_ecc;
- chip->ecc.correct = s3c2410_nand_correct_data;
- chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
-
- /*
- * Setup ECC handling in accordance to the kernel
- * - 1 times 512 bytes with 24 bit ECC for small page
- * - 8 times 256 bytes with 24 bit ECC each for large page
- */
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.bytes = 3; /* always 24 bit ECC per turn */
-#ifdef CONFIG_CPU_S3C2440
- if (readl(host->base) & 0x8) {
- /* large page (2048 bytes per page) */
- chip->ecc.size = 256;
- } else
-#endif
- {
- /* small page (512 bytes per page) */
- chip->ecc.size = 512;
- chip->ecc.layout = &nand_hw_eccoob;
- }
-
- if (pdata->flash_bbt) {
- /* use a flash based bbt */
- chip->options |= NAND_USE_FLASH_BBT;
- }
-
- ret = s3c24x0_nand_inithw(host);
- if (ret != 0)
- goto on_error;
-
- /* Scan to find existence of the device */
- ret = nand_scan(mtd, 1);
- if (ret != 0) {
- ret = -ENXIO;
- goto on_error;
- }
-
- return add_mtd_device(mtd, "nand");
-
-on_error:
- free(host);
- return ret;
-}
-
-static struct driver_d s3c24x0_nand_driver = {
- .name = "s3c24x0_nand",
- .probe = s3c24x0_nand_probe,
-};
-
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-
-static void __nand_boot_init wait_for_completion(void __iomem *host)
-{
- while (!(readw(host + NFSTAT) & NFSTAT_BUSY))
- ;
-}
-
-/**
- * Convert a page offset into a page address for the NAND
- * @param host Where to write the address to
- * @param offs Page's offset in the NAND
- * @param ps Page size (512 or 2048)
- * @param c Address cycle count (3, 4 or 5)
- *
- * Uses the offset of the page to generate an page address into the NAND. This
- * differs when using a 512 byte or 2048 bytes per page NAND.
- * The collumn part of the page address to be generated is always forced to '0'.
- */
-static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
- int ps, int c)
-{
- send_addr(host, 0); /* collumn part 1 */
-
- if (ps == 512) {
- send_addr(host, offs >> 9);
- send_addr(host, offs >> 17);
- if (c > 3)
- send_addr(host, offs >> 25);
- } else {
- send_addr(host, 0); /* collumn part 2 */
- send_addr(host, offs >> 11);
- send_addr(host, offs >> 19);
- if (c > 4)
- send_addr(host, offs >> 27);
- send_cmd(host, NAND_CMD_READSTART);
- }
-}
-
-/**
- * Load a sequential count of pages from the NAND into memory
- * @param[out] dest Pointer to target area (in SDRAM)
- * @param[in] size Bytes to read from NAND device
- * @param[in] page Start page to read from
- *
- * This function must be located in the first 4kiB of the barebox image
- * (guess why).
- */
-void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
-{
- void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
- unsigned pagesize;
- int i, cycle;
-
- /*
- * Reenable the NFC and use the default (but slow) access
- * timing or the board specific setting if provided.
- */
- enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
-
- /* use the current NAND hardware configuration */
- switch (readl(S3C24X0_NAND_BASE) & 0xf) {
- case 0x6: /* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
- pagesize = 512;
- cycle = 4;
- break;
- case 0xc: /* 8 bit, 4 addr cycles, 2048 bpp, advanced NAND */
- pagesize = 2048;
- cycle = 4;
- break;
- case 0xe: /* 8 bit, 5 addr cycles, 2048 bpp, advanced NAND */
- pagesize = 2048;
- cycle = 5;
- break;
- default:
- /* we cannot output an error message here :-( */
- disable_nand_controller(host);
- return;
- }
-
- enable_cs(host);
-
- /* Reset the NAND device */
- send_cmd(host, NAND_CMD_RESET);
- wait_for_completion(host);
- disable_cs(host);
-
- do {
- enable_cs(host);
- send_cmd(host, NAND_CMD_READ0);
- nfc_addr(host, page * pagesize, pagesize, cycle);
- wait_for_completion(host);
- /* copy one page (do *not* use readsb() here!)*/
- for (i = 0; i < pagesize; i++)
- writeb(readb(host + NFDATA), (void __iomem *)(dest + i));
- disable_cs(host);
-
- page++;
- dest += pagesize;
- size -= pagesize;
- } while (size >= 0);
-
- /* disable the controller again */
- disable_nand_controller(host);
-}
-
-#ifdef CONFIG_NAND_S3C24XX_BOOT_DEBUG
-#include <command.h>
-
-static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
-{
- void *dest;
- int size;
-
- if (argc < 3)
- return COMMAND_ERROR_USAGE;
-
- dest = (void *)strtoul_suffix(argv[1], NULL, 0);
- size = strtoul_suffix(argv[2], NULL, 0);
-
- s3c24x0_nand_load_image(dest, size, 0);
-
- /* re-enable the controller again, as this was a test only */
- enable_nand_controller((void *)S3C24X0_NAND_BASE,
- BOARD_DEFAULT_NAND_TIMING);
-
- return 0;
-}
-
-static const __maybe_unused char cmd_nand_boot_test_help[] =
-"Usage: nand_boot_test <dest> <size>\n";
-
-BAREBOX_CMD_START(nand_boot_test)
- .cmd = do_nand_boot_test,
- .usage = "load an image from NAND",
- BAREBOX_CMD_HELP(cmd_nand_boot_test_help)
-BAREBOX_CMD_END
-#endif
-
-#endif /* CONFIG_S3C24XX_NAND_BOOT */
-
-/*
- * Main initialization routine
- * @return 0 if successful; non-zero otherwise
- */
-static int __init s3c24x0_nand_init(void)
-{
- return register_driver(&s3c24x0_nand_driver);
-}
-
-device_initcall(s3c24x0_nand_init);
-
-/**
- * @file
- * @brief Support for various kinds of NAND devices
- *
- * ECC handling in this driver (in accordance to the current 2.6.38 kernel):
- * - for small page NANDs it generates 3 ECC bytes out of 512 data bytes
- * - for large page NANDs it generates 24 ECC bytes out of 2048 data bytes
- *
- * As small page NANDs are using 48 bits ECC per default, this driver uses a
- * local OOB layout description, to shrink it down to 24 bits. This is a bad
- * idea, but we cannot change it here, as the kernel is using this layout.
- *
- * For large page NANDs this driver uses the default layout, as the kernel does.
- */
diff --git a/drivers/mtd/nand/nand_s3c24xx.c b/drivers/mtd/nand/nand_s3c24xx.c
new file mode 100644
index 0000000..c4fd13e
--- /dev/null
+++ b/drivers/mtd/nand/nand_s3c24xx.c
@@ -0,0 +1,665 @@
+/* linux/drivers/mtd/nand/s3c2410.c
+ *
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * Copyright © 2004-2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C2410 NAND driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c24xx-nand.h>
+#include <io.h>
+#include <asm-generic/errno.h>
+
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+# define __nand_boot_init __bare_init
+# ifndef BOARD_DEFAULT_NAND_TIMING
+# define BOARD_DEFAULT_NAND_TIMING 0x0737
+# endif
+#else
+# define __nand_boot_init
+#endif
+
+/**
+ * Define this symbol for testing purpose. It will add a command to read an
+ * image from the NAND like it the boot strap code will do.
+ */
+#define CONFIG_NAND_S3C24XX_BOOT_DEBUG
+
+/* NAND controller's register */
+
+#define NFCONF 0x00
+
+#ifdef CONFIG_CPU_S3C2410
+
+#define NFCMD 0x04
+#define NFADDR 0x08
+#define NFDATA 0x0c
+#define NFSTAT 0x10
+#define NFECC 0x14
+
+/* S3C2410 specific bits */
+#define NFSTAT_BUSY (1)
+#define NFCONF_nFCE (1 << 11)
+#define NFCONF_INITECC (1 << 12)
+#define NFCONF_EN (1 << 15)
+
+#endif /* CONFIG_CPU_S3C2410 */
+
+#ifdef CONFIG_CPU_S3C2440
+
+#define NFCONT 0x04
+#define NFCMD 0x08
+#define NFADDR 0x0C
+#define NFDATA 0x10
+#define NFSTAT 0x20
+#define NFECC 0x2C
+
+/* S3C2440 specific bits */
+#define NFSTAT_BUSY (1)
+#define NFCONT_nFCE (1 << 1)
+#define NFCONT_INITECC (1 << 4)
+#define NFCONT_EN (1)
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+
+struct s3c24x0_nand_host {
+ struct mtd_info mtd;
+ struct nand_chip nand;
+ struct mtd_partition *parts;
+ struct device_d *dev;
+
+ void __iomem *base;
+};
+
+/**
+ * oob placement block for use with hardware ecc generation on small page
+ */
+static struct nand_ecclayout nand_hw_eccoob = {
+ .eccbytes = 3,
+ .eccpos = { 0, 1, 2},
+ .oobfree = {
+ {
+ .offset = 8,
+ .length = 8
+ }
+ }
+};
+
+/* - Functions shared between the boot strap code and the regular driver - */
+
+/**
+ * Issue the specified command to the NAND device
+ * @param[in] host Base address of the NAND controller
+ * @param[in] cmd Command for NAND flash
+ */
+static void __nand_boot_init send_cmd(void __iomem *host, uint8_t cmd)
+{
+ writeb(cmd, host + NFCMD);
+}
+
+/**
+ * Issue the specified address to the NAND device
+ * @param[in] host Base address of the NAND controller
+ * @param[in] addr Address for the NAND flash
+ */
+static void __nand_boot_init send_addr(void __iomem *host, uint8_t addr)
+{
+ writeb(addr, host + NFADDR);
+}
+
+/**
+ * Enable the NAND flash access
+ * @param[in] host Base address of the NAND controller
+ */
+static void __nand_boot_init enable_cs(void __iomem *host)
+{
+#ifdef CONFIG_CPU_S3C2410
+ writew(readw(host + NFCONF) & ~NFCONF_nFCE, host + NFCONF);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ writew(readw(host + NFCONT) & ~NFCONT_nFCE, host + NFCONT);
+#endif
+}
+
+/**
+ * Disable the NAND flash access
+ * @param[in] host Base address of the NAND controller
+ */
+static void __nand_boot_init disable_cs(void __iomem *host)
+{
+#ifdef CONFIG_CPU_S3C2410
+ writew(readw(host + NFCONF) | NFCONF_nFCE, host + NFCONF);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ writew(readw(host + NFCONT) | NFCONT_nFCE, host + NFCONT);
+#endif
+}
+
+/**
+ * Enable the NAND flash controller
+ * @param[in] host Base address of the NAND controller
+ * @param[in] timing Timing to access the NAND memory
+ */
+static void __nand_boot_init enable_nand_controller(void __iomem *host, uint32_t timing)
+{
+#ifdef CONFIG_CPU_S3C2410
+ writew(timing + NFCONF_EN + NFCONF_nFCE, host + NFCONF);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ writew(NFCONT_EN + NFCONT_nFCE, host + NFCONT);
+ writew(timing, host + NFCONF);
+#endif
+}
+
+/**
+ * Diable the NAND flash controller
+ * @param[in] host Base address of the NAND controller
+ */
+static void __nand_boot_init disable_nand_controller(void __iomem *host)
+{
+#ifdef CONFIG_CPU_S3C2410
+ writew(NFCONF_nFCE, host + NFCONF);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ writew(NFCONT_nFCE, host + NFCONT);
+#endif
+}
+
+/* ----------------------------------------------------------------------- */
+
+#ifdef CONFIG_CPU_S3C2440
+/**
+ * Read one block of data from the NAND port
+ * @param[in] mtd Instance data
+ * @param[out] buf buffer to write data to
+ * @param[in] len byte count
+ *
+ * This is a special block read variant for the S3C2440 CPU.
+ */
+static void s3c2440_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+ readsl(host->base + NFDATA, buf, len >> 2);
+
+ /* cleanup any fractional read */
+ if (len & 3) {
+ buf += len & ~3;
+
+ for (; len & 3; len--)
+ *buf++ = readb(host->base + NFDATA);
+ }
+}
+
+/**
+ * Write one block of data to the NAND port
+ * @param[in] mtd Instance data
+ * @param[out] buf buffer to read data from
+ * @param[in] len byte count
+ *
+ * This is a special block write variant for the S3C2440 CPU.
+ */
+static void s3c2440_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+ writesl(host->base + NFDATA, buf, len >> 2);
+
+ /* cleanup any fractional write */
+ if (len & 3) {
+ buf += len & ~3;
+
+ for (; len & 3; len--, buf++)
+ writeb(*buf, host->base + NFDATA);
+ }
+}
+#endif
+
+/**
+ * Check the ECC and try to repair the data if possible
+ * @param[in] mtd_info Not used
+ * @param[inout] dat Pointer to the data buffer that might contain a bit error
+ * @param[in] read_ecc ECC data from the OOB space
+ * @param[in] calc_ecc ECC data calculated from the data
+ * @return 0 no error, 1 repaired error, -1 no way...
+ *
+ * @note: This routine works always on a 24 bit ECC
+ */
+static int s3c2410_nand_correct_data(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ unsigned int diff0, diff1, diff2;
+ unsigned int bit, byte;
+
+ diff0 = read_ecc[0] ^ calc_ecc[0];
+ diff1 = read_ecc[1] ^ calc_ecc[1];
+ diff2 = read_ecc[2] ^ calc_ecc[2];
+
+ if (diff0 == 0 && diff1 == 0 && diff2 == 0)
+ return 0; /* ECC is ok */
+
+ /* sometimes people do not think about using the ECC, so check
+ * to see if we have an 0xff,0xff,0xff read ECC and then ignore
+ * the error, on the assumption that this is an un-eccd page.
+ */
+ if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff)
+ return 0;
+
+ /* Can we correct this ECC (ie, one row and column change).
+ * Note, this is similar to the 256 error code on smartmedia */
+
+ if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
+ ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
+ ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
+ /* calculate the bit position of the error */
+
+ bit = ((diff2 >> 3) & 1) |
+ ((diff2 >> 4) & 2) |
+ ((diff2 >> 5) & 4);
+
+ /* calculate the byte position of the error */
+
+ byte = ((diff2 << 7) & 0x100) |
+ ((diff1 << 0) & 0x80) |
+ ((diff1 << 1) & 0x40) |
+ ((diff1 << 2) & 0x20) |
+ ((diff1 << 3) & 0x10) |
+ ((diff0 >> 4) & 0x08) |
+ ((diff0 >> 3) & 0x04) |
+ ((diff0 >> 2) & 0x02) |
+ ((diff0 >> 1) & 0x01);
+
+ dat[byte] ^= (1 << bit);
+ return 1;
+ }
+
+ /* if there is only one bit difference in the ECC, then
+ * one of only a row or column parity has changed, which
+ * means the error is most probably in the ECC itself */
+
+ diff0 |= (diff1 << 8);
+ diff0 |= (diff2 << 16);
+
+ if ((diff0 & ~(1<<fls(diff0))) == 0)
+ return 1;
+
+ return -1;
+}
+
+static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+#ifdef CONFIG_CPU_S3C2410
+ writel(readl(host->base + NFCONF) | NFCONF_INITECC , host->base + NFCONF);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ writel(readl(host->base + NFCONT) | NFCONT_INITECC , host->base + NFCONT);
+#endif
+}
+
+static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+#ifdef CONFIG_CPU_S3C2410
+ ecc_code[0] = readb(host->base + NFECC);
+ ecc_code[1] = readb(host->base + NFECC + 1);
+ ecc_code[2] = readb(host->base + NFECC + 2);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ unsigned long ecc = readl(host->base + NFECC);
+
+ ecc_code[0] = ecc;
+ ecc_code[1] = ecc >> 8;
+ ecc_code[2] = ecc >> 16;
+#endif
+ return 0;
+}
+
+static void s3c24x0_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+ if (chip == -1)
+ disable_cs(host->base);
+ else
+ enable_cs(host->base);
+}
+
+static int s3c24x0_nand_devready(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+ return readw(host->base + NFSTAT) & NFSTAT_BUSY;
+}
+
+static void s3c24x0_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct s3c24x0_nand_host *host = nand_chip->priv;
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+ /*
+ * If the CLE should be active, this call is a NAND command
+ */
+ if (ctrl & NAND_CLE)
+ send_cmd(host->base, cmd);
+ /*
+ * If the ALE should be active, this call is a NAND address
+ */
+ if (ctrl & NAND_ALE)
+ send_addr(host->base, cmd);
+}
+
+static int s3c24x0_nand_inithw(struct s3c24x0_nand_host *host)
+{
+ struct s3c24x0_nand_platform_data *pdata = host->dev->platform_data;
+ uint32_t tmp;
+
+ /* reset the NAND controller */
+ disable_nand_controller(host->base);
+
+ if (pdata != NULL)
+ tmp = pdata->nand_timing;
+ else
+ /* else slowest possible timing */
+ tmp = CALC_NFCONF_TIMING(4, 8, 8);
+
+ /* reenable the NAND controller */
+ enable_nand_controller(host->base, tmp);
+
+ return 0;
+}
+
+static int s3c24x0_nand_probe(struct device_d *dev)
+{
+ struct nand_chip *chip;
+ struct s3c24x0_nand_platform_data *pdata = dev->platform_data;
+ struct mtd_info *mtd;
+ struct s3c24x0_nand_host *host;
+ int ret;
+
+ /* Allocate memory for MTD device structure and private data */
+ host = kzalloc(sizeof(struct s3c24x0_nand_host), GFP_KERNEL);
+ if (!host)
+ return -ENOMEM;
+
+ host->dev = dev;
+ host->base = dev_request_mem_region(dev, 0);
+
+ /* structures must be linked */
+ chip = &host->nand;
+ mtd = &host->mtd;
+ mtd->priv = chip;
+
+ /* init the default settings */
+
+ /* 50 us command delay time */
+ chip->chip_delay = 50;
+ chip->priv = host;
+
+ chip->IO_ADDR_R = chip->IO_ADDR_W = host->base + NFDATA;
+
+#ifdef CONFIG_CPU_S3C2440
+ chip->read_buf = s3c2440_nand_read_buf;
+ chip->write_buf = s3c2440_nand_write_buf;
+#endif
+ chip->cmd_ctrl = s3c24x0_nand_hwcontrol;
+ chip->dev_ready = s3c24x0_nand_devready;
+ chip->select_chip = s3c24x0_nand_select_chip;
+
+ /* we are using the hardware ECC feature of this device */
+ chip->ecc.calculate = s3c2410_nand_calculate_ecc;
+ chip->ecc.correct = s3c2410_nand_correct_data;
+ chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
+
+ /*
+ * Setup ECC handling in accordance to the kernel
+ * - 1 times 512 bytes with 24 bit ECC for small page
+ * - 8 times 256 bytes with 24 bit ECC each for large page
+ */
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.bytes = 3; /* always 24 bit ECC per turn */
+#ifdef CONFIG_CPU_S3C2440
+ if (readl(host->base) & 0x8) {
+ /* large page (2048 bytes per page) */
+ chip->ecc.size = 256;
+ } else
+#endif
+ {
+ /* small page (512 bytes per page) */
+ chip->ecc.size = 512;
+ chip->ecc.layout = &nand_hw_eccoob;
+ }
+
+ if (pdata->flash_bbt) {
+ /* use a flash based bbt */
+ chip->options |= NAND_USE_FLASH_BBT;
+ }
+
+ ret = s3c24x0_nand_inithw(host);
+ if (ret != 0)
+ goto on_error;
+
+ /* Scan to find existence of the device */
+ ret = nand_scan(mtd, 1);
+ if (ret != 0) {
+ ret = -ENXIO;
+ goto on_error;
+ }
+
+ return add_mtd_device(mtd);
+
+on_error:
+ free(host);
+ return ret;
+}
+
+static struct driver_d s3c24x0_nand_driver = {
+ .name = "s3c24x0_nand",
+ .probe = s3c24x0_nand_probe,
+};
+
+#ifdef CONFIG_S3C24XX_NAND_BOOT
+
+static void __nand_boot_init wait_for_completion(void __iomem *host)
+{
+ while (!(readw(host + NFSTAT) & NFSTAT_BUSY))
+ ;
+}
+
+/**
+ * Convert a page offset into a page address for the NAND
+ * @param host Where to write the address to
+ * @param offs Page's offset in the NAND
+ * @param ps Page size (512 or 2048)
+ * @param c Address cycle count (3, 4 or 5)
+ *
+ * Uses the offset of the page to generate an page address into the NAND. This
+ * differs when using a 512 byte or 2048 bytes per page NAND.
+ * The collumn part of the page address to be generated is always forced to '0'.
+ */
+static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
+ int ps, int c)
+{
+ send_addr(host, 0); /* collumn part 1 */
+
+ if (ps == 512) {
+ send_addr(host, offs >> 9);
+ send_addr(host, offs >> 17);
+ if (c > 3)
+ send_addr(host, offs >> 25);
+ } else {
+ send_addr(host, 0); /* collumn part 2 */
+ send_addr(host, offs >> 11);
+ send_addr(host, offs >> 19);
+ if (c > 4)
+ send_addr(host, offs >> 27);
+ send_cmd(host, NAND_CMD_READSTART);
+ }
+}
+
+/**
+ * Load a sequential count of pages from the NAND into memory
+ * @param[out] dest Pointer to target area (in SDRAM)
+ * @param[in] size Bytes to read from NAND device
+ * @param[in] page Start page to read from
+ *
+ * This function must be located in the first 4kiB of the barebox image
+ * (guess why).
+ */
+void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
+{
+ void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
+ unsigned pagesize;
+ int i, cycle;
+
+ /*
+ * Reenable the NFC and use the default (but slow) access
+ * timing or the board specific setting if provided.
+ */
+ enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
+
+ /* use the current NAND hardware configuration */
+ switch (readl(S3C24X0_NAND_BASE) & 0xf) {
+ case 0x6: /* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
+ pagesize = 512;
+ cycle = 4;
+ break;
+ case 0xc: /* 8 bit, 4 addr cycles, 2048 bpp, advanced NAND */
+ pagesize = 2048;
+ cycle = 4;
+ break;
+ case 0xe: /* 8 bit, 5 addr cycles, 2048 bpp, advanced NAND */
+ pagesize = 2048;
+ cycle = 5;
+ break;
+ default:
+ /* we cannot output an error message here :-( */
+ disable_nand_controller(host);
+ return;
+ }
+
+ enable_cs(host);
+
+ /* Reset the NAND device */
+ send_cmd(host, NAND_CMD_RESET);
+ wait_for_completion(host);
+ disable_cs(host);
+
+ do {
+ enable_cs(host);
+ send_cmd(host, NAND_CMD_READ0);
+ nfc_addr(host, page * pagesize, pagesize, cycle);
+ wait_for_completion(host);
+ /* copy one page (do *not* use readsb() here!)*/
+ for (i = 0; i < pagesize; i++)
+ writeb(readb(host + NFDATA), (void __iomem *)(dest + i));
+ disable_cs(host);
+
+ page++;
+ dest += pagesize;
+ size -= pagesize;
+ } while (size >= 0);
+
+ /* disable the controller again */
+ disable_nand_controller(host);
+}
+
+#ifdef CONFIG_NAND_S3C24XX_BOOT_DEBUG
+#include <command.h>
+
+static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
+{
+ void *dest;
+ int size;
+
+ if (argc < 3)
+ return COMMAND_ERROR_USAGE;
+
+ dest = (void *)strtoul_suffix(argv[1], NULL, 0);
+ size = strtoul_suffix(argv[2], NULL, 0);
+
+ s3c24x0_nand_load_image(dest, size, 0);
+
+ /* re-enable the controller again, as this was a test only */
+ enable_nand_controller((void *)S3C24X0_NAND_BASE,
+ BOARD_DEFAULT_NAND_TIMING);
+
+ return 0;
+}
+
+static const __maybe_unused char cmd_nand_boot_test_help[] =
+"Usage: nand_boot_test <dest> <size>\n";
+
+BAREBOX_CMD_START(nand_boot_test)
+ .cmd = do_nand_boot_test,
+ .usage = "load an image from NAND",
+ BAREBOX_CMD_HELP(cmd_nand_boot_test_help)
+BAREBOX_CMD_END
+#endif
+
+#endif /* CONFIG_S3C24XX_NAND_BOOT */
+
+/*
+ * Main initialization routine
+ * @return 0 if successful; non-zero otherwise
+ */
+static int __init s3c24x0_nand_init(void)
+{
+ return register_driver(&s3c24x0_nand_driver);
+}
+
+device_initcall(s3c24x0_nand_init);
+
+/**
+ * @file
+ * @brief Support for various kinds of NAND devices
+ *
+ * ECC handling in this driver (in accordance to the current 2.6.38 kernel):
+ * - for small page NANDs it generates 3 ECC bytes out of 512 data bytes
+ * - for large page NANDs it generates 24 ECC bytes out of 2048 data bytes
+ *
+ * As small page NANDs are using 48 bits ECC per default, this driver uses a
+ * local OOB layout description, to shrink it down to 24 bits. This is a bad
+ * idea, but we cannot change it here, as the kernel is using this layout.
+ *
+ * For large page NANDs this driver uses the default layout, as the kernel does.
+ */
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (3 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 04/14] MACH SAMSUNG/S3C: Use the correct CPU family name to reflect NAND driver's usage Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for Juergen Beisert
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/include/mach/mci.h | 46 --------------------------
arch/arm/mach-samsung/include/mach/s3c-mci.h | 46 ++++++++++++++++++++++++++
drivers/mci/s3c.c | 2 +-
4 files changed, 48 insertions(+), 48 deletions(-)
delete mode 100644 arch/arm/mach-samsung/include/mach/mci.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-mci.h
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index dca9083..233f337 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -41,7 +41,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
-#include <mach/mci.h>
+#include <mach/s3c-mci.h>
#include <mach/fb.h>
static struct s3c24x0_nand_platform_data nand_info = {
diff --git a/arch/arm/mach-samsung/include/mach/mci.h b/arch/arm/mach-samsung/include/mach/mci.h
deleted file mode 100644
index 6ba8961..0000000
--- a/arch/arm/mach-samsung/include/mach/mci.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2010 Juergen Beisert, Pengutronix
- *
- * This code is partially based on u-boot code:
- *
- * Copyright 2008, Freescale Semiconductor, Inc
- * Andy Fleming
- *
- * Based (loosely) on the Linux code
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MMC_H_
-#define __MACH_MMC_H_
-
-struct s3c_mci_platform_data {
- unsigned caps; /**< supported operating modes (MMC_MODE_*) */
- unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
- unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
- unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
- /* TODO */
- /* function to modify the voltage */
- /* function to switch the voltage */
- /* function to detect the presence of a SD card in the socket */
- unsigned gpio_detect;
- unsigned detect_invert;
-};
-
-#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-mci.h b/arch/arm/mach-samsung/include/mach/s3c-mci.h
new file mode 100644
index 0000000..6ba8961
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-mci.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is partially based on u-boot code:
+ *
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MMC_H_
+#define __MACH_MMC_H_
+
+struct s3c_mci_platform_data {
+ unsigned caps; /**< supported operating modes (MMC_MODE_*) */
+ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
+ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
+ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
+ /* TODO */
+ /* function to modify the voltage */
+ /* function to switch the voltage */
+ /* function to detect the presence of a SD card in the socket */
+ unsigned gpio_detect;
+ unsigned detect_invert;
+};
+
+#endif /* __MACH_MMC_H_ */
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index c877e09..12d2c03 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -40,7 +40,7 @@
#include <errno.h>
#include <clock.h>
#include <io.h>
-#include <mach/mci.h>
+#include <mach/s3c-mci.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-iomap.h>
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (4 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 05/14] MACH SAMSUNG/S3C: Parts of the SDHC driver can be shared in the S3C CPU family Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management Juergen Beisert
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
This LCD driver is for the LCD controller in the S3C2410/S3C2440 CPUs only.
Change its name to reflect its usage and free the way to add LCD controller
drivers for more recent Samsung CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/include/mach/fb.h | 59 ---
arch/arm/mach-samsung/include/mach/s3c24xx-fb.h | 59 +++
drivers/video/Kconfig | 2 +-
drivers/video/Makefile | 2 +-
drivers/video/s3c.c | 431 -----------------------
drivers/video/s3c24xx.c | 431 +++++++++++++++++++++++
7 files changed, 493 insertions(+), 493 deletions(-)
delete mode 100644 arch/arm/mach-samsung/include/mach/fb.h
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
delete mode 100644 drivers/video/s3c.c
create mode 100644 drivers/video/s3c24xx.c
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 233f337..0186465 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -42,7 +42,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
-#include <mach/fb.h>
+#include <mach/s3c24xx-fb.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
diff --git a/arch/arm/mach-samsung/include/mach/fb.h b/arch/arm/mach-samsung/include/mach/fb.h
deleted file mode 100644
index 05e013a..0000000
--- a/arch/arm/mach-samsung/include/mach/fb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __MACH_FB_H_
-# define __MACH_FB_H_
-
-#include <fb.h>
-
-/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
-
-/** ! INVVDEN - DE active high */
-#define FB_SYNC_DE_HIGH_ACT (1 << 23)
-/** INVVCLK - invert CLK signal */
-#define FB_SYNC_CLK_INVERT (1 << 24)
-/** INVVD - invert data */
-#define FB_SYNC_DATA_INVERT (1 << 25)
-/** INVPWREN - use PWREN signal */
-#define FB_SYNC_INVERT_PWREN (1 << 26)
-/** INVLEND - use LEND signal */
-#define FB_SYNC_INVERT_LEND (1 << 27)
-/** PWREN - use PWREN signal */
-#define FB_SYNC_USE_PWREN (1 << 28)
-/** ENLEND - use LEND signal */
-#define FB_SYNC_USE_LEND (1 << 29)
-/** BSWP - swap bytes */
-#define FB_SYNC_SWAP_BYTES (1 << 30)
-/** HWSWP - swap half words */
-#define FB_SYNC_SWAP_HW (1 << 31)
-
-struct s3c_fb_platform_data {
- struct fb_videomode *mode_list;
- unsigned mode_cnt;
-
- unsigned bits_per_pixel;
- int passive_display; /**< enable support for STN or CSTN displays */
-
- /** hook to enable backlight and stuff */
- void (*enable)(int enable);
-};
-
-#endif /* __MACH_FB_H_ */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
new file mode 100644
index 0000000..05e013a
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-fb.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ * Copyright (C) 2011 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MACH_FB_H_
+# define __MACH_FB_H_
+
+#include <fb.h>
+
+/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
+
+/** ! INVVDEN - DE active high */
+#define FB_SYNC_DE_HIGH_ACT (1 << 23)
+/** INVVCLK - invert CLK signal */
+#define FB_SYNC_CLK_INVERT (1 << 24)
+/** INVVD - invert data */
+#define FB_SYNC_DATA_INVERT (1 << 25)
+/** INVPWREN - use PWREN signal */
+#define FB_SYNC_INVERT_PWREN (1 << 26)
+/** INVLEND - use LEND signal */
+#define FB_SYNC_INVERT_LEND (1 << 27)
+/** PWREN - use PWREN signal */
+#define FB_SYNC_USE_PWREN (1 << 28)
+/** ENLEND - use LEND signal */
+#define FB_SYNC_USE_LEND (1 << 29)
+/** BSWP - swap bytes */
+#define FB_SYNC_SWAP_BYTES (1 << 30)
+/** HWSWP - swap half words */
+#define FB_SYNC_SWAP_HW (1 << 31)
+
+struct s3c_fb_platform_data {
+ struct fb_videomode *mode_list;
+ unsigned mode_cnt;
+
+ unsigned bits_per_pixel;
+ int passive_display; /**< enable support for STN or CSTN displays */
+
+ /** hook to enable backlight and stuff */
+ void (*enable)(int enable);
+};
+
+#endif /* __MACH_FB_H_ */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index df2157e..4a05af9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -27,7 +27,7 @@ config DRIVER_VIDEO_STM
Say 'Y' here to enable framebuffer and splash screen support for
i.MX23 and i.MX28 based systems.
-config DRIVER_VIDEO_S3C
+config DRIVER_VIDEO_S3C24XX
bool "S3C244x framebuffer driver"
depends on ARCH_S3C24xx
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 123c46f..913c78d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -3,5 +3,5 @@ obj-$(CONFIG_VIDEO) += fb.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += stm.o
obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
-obj-$(CONFIG_DRIVER_VIDEO_S3C) += s3c.o
+obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c
deleted file mode 100644
index a03ec3d..0000000
--- a/drivers/video/s3c.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * Copyright (C) 2010 Juergen Beisert
- * Copyright (C) 2011 Alexey Galakhov
- *
- * This driver is based on a patch found in the web:
- * (C) Copyright 2006 by OpenMoko, Inc.
- * Author: Harald Welte <laforge at openmoko.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <init.h>
-#include <fb.h>
-#include <driver.h>
-#include <malloc.h>
-#include <errno.h>
-#include <io.h>
-#include <mach/gpio.h>
-#include <mach/s3c-generic.h>
-#include <mach/fb.h>
-
-#define LCDCON1 0x00
-# define PNRMODE(x) (((x) & 3) << 5)
-# define BPPMODE(x) (((x) & 0xf) << 1)
-# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
-# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
-# define ENVID (1 << 0)
-
-#define LCDCON2 0x04
-# define SET_VBPD(x) (((x) & 0xff) << 24)
-# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
-# define SET_VFPD(x) (((x) & 0xff) << 6)
-# define SET_VSPW(x) ((x) & 0x3f)
-
-#define LCDCON3 0x08
-# define SET_HBPD(x) (((x) & 0x7f) << 19)
-# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
-# define SET_HFPD(x) ((x) & 0xff)
-
-#define LCDCON4 0x0c
-# define SET_HSPW(x) ((x) & 0xff)
-
-#define LCDCON5 0x10
-# define BPP24BL (1 << 12)
-# define FRM565 (1 << 11)
-# define INV_CLK (1 << 10)
-# define INV_HS (1 << 9)
-# define INV_VS (1 << 8)
-# define INV_DTA (1 << 7)
-# define INV_DE (1 << 6)
-# define INV_PWREN (1 << 5)
-# define INV_LEND (1 << 4)
-# define ENA_PWREN (1 << 3)
-# define ENA_LEND (1 << 2)
-# define BSWP (1 << 1)
-# define HWSWP (1 << 0)
-
-#define LCDSADDR1 0x14
-# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
-# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
-# define SET_LCDBASEU(x) ((x) & 0x1fffff)
-# define GET_LCDBASEU(x) ((x) & 0x1fffff)
-
-#define LCDSADDR2 0x18
-# define SET_LCDBASEL(x) ((x) & 0x1fffff)
-# define GET_LCDBASEL(x) ((x) & 0x1fffff)
-
-#define LCDSADDR3 0x1c
-# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
-# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
-# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
-# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
-
-#define RED_LUT 0x20
-#define GREEN_LUT 0x24
-#define BLUE_LUT 0x28
-
-#define DITHMODE 0x4c
-
-#define TPAL 0x50
-
-#define LCDINTPND 0x54
-#define LCDSRCPND 0x58
-#define LCDINTMSK 0x5c
-# define FIWSEL (1 << 2)
-# define INT_FrSyn (1 << 1)
-# define INT_FiCnt (1 << 0)
-
-#define TCONSEL 0x60
-
-#define RED 0
-#define GREEN 1
-#define BLUE 2
-#define TRANSP 3
-
-struct s3cfb_info {
- void __iomem *base;
- unsigned memory_size;
- struct fb_info info;
- struct device_d *hw_dev;
- int passive_display;
- void (*enable)(int enable);
-};
-
-/* the RGB565 true colour mode */
-static const struct fb_bitfield def_rgb565[] = {
- [RED] = {
- .offset = 11,
- .length = 5,
- },
- [GREEN] = {
- .offset = 5,
- .length = 6,
- },
- [BLUE] = {
- .offset = 0,
- .length = 5,
- },
- [TRANSP] = { /* no support for transparency */
- .length = 0,
- }
-};
-
-/* the RGB888 true colour mode */
-static const struct fb_bitfield def_rgb888[] = {
- [RED] = {
- .offset = 16,
- .length = 8,
- },
- [GREEN] = {
- .offset = 8,
- .length = 8,
- },
- [BLUE] = {
- .offset = 0,
- .length = 8,
- },
- [TRANSP] = { /* no support for transparency */
- .length = 0,
- }
-};
-
-/**
- * @param fb_info Framebuffer information
- */
-static void s3cfb_enable_controller(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- uint32_t con1;
-
- con1 = readl(fbi->base + LCDCON1);
-
- con1 |= ENVID;
-
- writel(con1, fbi->base + LCDCON1);
-
- if (fbi->enable)
- fbi->enable(1);
-}
-
-/**
- * @param fb_info Framebuffer information
- */
-static void s3cfb_disable_controller(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- uint32_t con1;
-
- if (fbi->enable)
- fbi->enable(0);
-
- con1 = readl(fbi->base + LCDCON1);
-
- con1 &= ~ENVID;
-
- writel(con1, fbi->base + LCDCON1);
-}
-
-/**
- * Prepare the video hardware for a specified video mode
- * @param fb_info Framebuffer information
- * @param mode The video mode description to initialize
- * @return 0 on success
- */
-static int s3cfb_activate_var(struct fb_info *fb_info)
-{
- struct s3cfb_info *fbi = fb_info->priv;
- struct fb_videomode *mode = fb_info->mode;
- unsigned size, hclk, div;
- uint32_t con1, con2, con3, con4, con5 = 0;
-
- if (fbi->passive_display != 0) {
- dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
- return -EINVAL;
- }
-
- /*
- * we need at least this amount of memory for the framebuffer
- */
- size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
- if (fbi->memory_size != size || fb_info->screen_base == NULL) {
- if (fb_info->screen_base)
- free(fb_info->screen_base);
- fbi->memory_size = 0;
- fb_info->screen_base = malloc(size);
- if (! fb_info->screen_base)
- return -ENOMEM;
- memset(fb_info->screen_base, 0, size);
- fbi->memory_size = size;
- }
-
- /* ensure video output is _off_ */
- writel(0x00000000, fbi->base + LCDCON1);
-
- hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
- div = hclk / PICOS2KHZ(mode->pixclock);
- if (div < 3)
- div = 3;
- /* pixel clock is: (hclk) / ((div + 1) * 2) */
- div += 1;
- div >>= 1;
- div -= 1;
-
- con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
-
- switch (fb_info->bits_per_pixel) {
- case 16:
- con1 |= BPPMODE(12);
- con5 |= FRM565;
- con5 |= HWSWP;
- fb_info->red = def_rgb565[RED];
- fb_info->green = def_rgb565[GREEN];
- fb_info->blue = def_rgb565[BLUE];
- fb_info->transp = def_rgb565[TRANSP];
- break;
- case 24:
- con1 |= BPPMODE(13);
- /* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
- fb_info->red = def_rgb888[RED];
- fb_info->green = def_rgb888[GREEN];
- fb_info->blue = def_rgb888[BLUE];
- fb_info->transp = def_rgb888[TRANSP];
- break;
- default:
- dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
- return -EINVAL;
- }
-
- /* 'normal' in register description means positive logic */
- if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
- con5 |= INV_HS;
- if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
- con5 |= INV_VS;
- if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
- con5 |= INV_DE;
- if (mode->sync & FB_SYNC_CLK_INVERT)
- con5 |= INV_CLK; /* display should latch at the rising edge */
- if (mode->sync & FB_SYNC_DATA_INVERT)
- con5 |= INV_DTA;
- if (mode->sync & FB_SYNC_INVERT_PWREN)
- con5 |= INV_PWREN;
- if (mode->sync & FB_SYNC_INVERT_LEND)
- con5 |= INV_LEND;
- if (mode->sync & FB_SYNC_USE_PWREN)
- con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
- if (mode->sync & FB_SYNC_USE_LEND)
- con5 |= ENA_LEND;
- if (mode->sync & FB_SYNC_SWAP_BYTES)
- con5 ^= BSWP;
- if (mode->sync & FB_SYNC_SWAP_HW)
- con5 ^= HWSWP;
-
- /* vertical timing */
- con2 = SET_VBPD(mode->upper_margin - 1) |
- SET_LINEVAL(mode->yres - 1) |
- SET_VFPD(mode->lower_margin - 1) |
- SET_VSPW(mode->vsync_len - 1);
-
- /* horizontal timing */
- con3 = SET_HBPD(mode->left_margin - 1) |
- SET_HOZVAL(mode->xres - 1) |
- SET_HFPD(mode->right_margin - 1);
- con4 = SET_HSPW(mode->hsync_len - 1);
-
- /* basic timing setup */
- writel(con1, fbi->base + LCDCON1);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
- writel(con2, fbi->base + LCDCON2);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
- writel(con3, fbi->base + LCDCON3);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
- writel(con4, fbi->base + LCDCON4);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
- writel(con5, fbi->base + LCDCON5);
- dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
-
- dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
-
- /* framebuffer memory setup */
- writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
- size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
- writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
- writel(SET_OFFSIZE(0) |
- SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
- fbi->base + LCDSADDR3);
- writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
-
- return 0;
-}
-
-/**
- * Print some information about the current hardware state
- * @param hw_dev S3C video device
- */
-#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
-static void s3cfb_info(struct device_d *hw_dev)
-{
- uint32_t con1, addr1, addr2, addr3;
- struct s3cfb_info *fbi = hw_dev->priv;
-
- con1 = readl(fbi->base + LCDCON1);
- addr1 = readl(fbi->base + LCDSADDR1);
- addr2 = readl(fbi->base + LCDSADDR2);
- addr3 = readl(fbi->base + LCDSADDR3);
-
- printf(" Video hardware info:\n");
- printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
- printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
- printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
- printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
- printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
- printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
-}
-#endif
-
-/*
- * There is only one video hardware instance available.
- * It makes no sense to dynamically allocate this data
- */
-static struct fb_ops s3cfb_ops = {
- .fb_activate_var = s3cfb_activate_var,
- .fb_enable = s3cfb_enable_controller,
- .fb_disable = s3cfb_disable_controller,
-};
-
-static struct s3cfb_info fbi = {
- .info = {
- .fbops = &s3cfb_ops,
- },
-};
-
-static int s3cfb_probe(struct device_d *hw_dev)
-{
- struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
- int ret;
-
- if (! pdata)
- return -ENODEV;
-
- fbi.base = dev_request_mem_region(hw_dev, 0);
- writel(0, fbi.base + LCDCON1);
- writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
-
- /* just init */
- fbi.info.priv = &fbi;
-
- /* add runtime hardware info */
- fbi.hw_dev = hw_dev;
- hw_dev->priv = &fbi;
-
- /* add runtime video info */
- fbi.info.mode_list = pdata->mode_list;
- fbi.info.num_modes = pdata->mode_cnt;
- fbi.info.mode = &fbi.info.mode_list[1];
- fbi.info.xres = fbi.info.mode->xres;
- fbi.info.yres = fbi.info.mode->yres;
- if (pdata->bits_per_pixel)
- fbi.info.bits_per_pixel = pdata->bits_per_pixel;
- else
- fbi.info.bits_per_pixel = 16;
- fbi.passive_display = pdata->passive_display;
- fbi.enable = pdata->enable;
-
- ret = register_framebuffer(&fbi.info);
- if (ret != 0) {
- dev_err(hw_dev, "Failed to register framebuffer\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct driver_d s3cfb_driver = {
- .name = "s3c_fb",
- .probe = s3cfb_probe,
-#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
- .info = s3cfb_info,
-#endif
-};
-
-static int s3cfb_init(void)
-{
- return register_driver(&s3cfb_driver);
-}
-
-device_initcall(s3cfb_init);
-
-/**
- * The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
- *
- * The driver itself currently supports only active TFT LC displays in the follwing manner:
- *
- * * True colours
- * - 16 bpp
- * - 24 bpp (untested)
- */
diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c
new file mode 100644
index 0000000..75677c3
--- /dev/null
+++ b/drivers/video/s3c24xx.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ * Copyright (C) 2011 Alexey Galakhov
+ *
+ * This driver is based on a patch found in the web:
+ * (C) Copyright 2006 by OpenMoko, Inc.
+ * Author: Harald Welte <laforge at openmoko.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <fb.h>
+#include <driver.h>
+#include <malloc.h>
+#include <errno.h>
+#include <io.h>
+#include <mach/s3c-gpio.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c24xx-fb.h>
+
+#define LCDCON1 0x00
+# define PNRMODE(x) (((x) & 3) << 5)
+# define BPPMODE(x) (((x) & 0xf) << 1)
+# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
+# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
+# define ENVID (1 << 0)
+
+#define LCDCON2 0x04
+# define SET_VBPD(x) (((x) & 0xff) << 24)
+# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
+# define SET_VFPD(x) (((x) & 0xff) << 6)
+# define SET_VSPW(x) ((x) & 0x3f)
+
+#define LCDCON3 0x08
+# define SET_HBPD(x) (((x) & 0x7f) << 19)
+# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
+# define SET_HFPD(x) ((x) & 0xff)
+
+#define LCDCON4 0x0c
+# define SET_HSPW(x) ((x) & 0xff)
+
+#define LCDCON5 0x10
+# define BPP24BL (1 << 12)
+# define FRM565 (1 << 11)
+# define INV_CLK (1 << 10)
+# define INV_HS (1 << 9)
+# define INV_VS (1 << 8)
+# define INV_DTA (1 << 7)
+# define INV_DE (1 << 6)
+# define INV_PWREN (1 << 5)
+# define INV_LEND (1 << 4)
+# define ENA_PWREN (1 << 3)
+# define ENA_LEND (1 << 2)
+# define BSWP (1 << 1)
+# define HWSWP (1 << 0)
+
+#define LCDSADDR1 0x14
+# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
+# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
+# define SET_LCDBASEU(x) ((x) & 0x1fffff)
+# define GET_LCDBASEU(x) ((x) & 0x1fffff)
+
+#define LCDSADDR2 0x18
+# define SET_LCDBASEL(x) ((x) & 0x1fffff)
+# define GET_LCDBASEL(x) ((x) & 0x1fffff)
+
+#define LCDSADDR3 0x1c
+# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
+# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
+# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
+# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
+
+#define RED_LUT 0x20
+#define GREEN_LUT 0x24
+#define BLUE_LUT 0x28
+
+#define DITHMODE 0x4c
+
+#define TPAL 0x50
+
+#define LCDINTPND 0x54
+#define LCDSRCPND 0x58
+#define LCDINTMSK 0x5c
+# define FIWSEL (1 << 2)
+# define INT_FrSyn (1 << 1)
+# define INT_FiCnt (1 << 0)
+
+#define TCONSEL 0x60
+
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define TRANSP 3
+
+struct s3cfb_info {
+ void __iomem *base;
+ unsigned memory_size;
+ struct fb_info info;
+ struct device_d *hw_dev;
+ int passive_display;
+ void (*enable)(int enable);
+};
+
+/* the RGB565 true colour mode */
+static const struct fb_bitfield def_rgb565[] = {
+ [RED] = {
+ .offset = 11,
+ .length = 5,
+ },
+ [GREEN] = {
+ .offset = 5,
+ .length = 6,
+ },
+ [BLUE] = {
+ .offset = 0,
+ .length = 5,
+ },
+ [TRANSP] = { /* no support for transparency */
+ .length = 0,
+ }
+};
+
+/* the RGB888 true colour mode */
+static const struct fb_bitfield def_rgb888[] = {
+ [RED] = {
+ .offset = 16,
+ .length = 8,
+ },
+ [GREEN] = {
+ .offset = 8,
+ .length = 8,
+ },
+ [BLUE] = {
+ .offset = 0,
+ .length = 8,
+ },
+ [TRANSP] = { /* no support for transparency */
+ .length = 0,
+ }
+};
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void s3cfb_enable_controller(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ uint32_t con1;
+
+ con1 = readl(fbi->base + LCDCON1);
+
+ con1 |= ENVID;
+
+ writel(con1, fbi->base + LCDCON1);
+
+ if (fbi->enable)
+ fbi->enable(1);
+}
+
+/**
+ * @param fb_info Framebuffer information
+ */
+static void s3cfb_disable_controller(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ uint32_t con1;
+
+ if (fbi->enable)
+ fbi->enable(0);
+
+ con1 = readl(fbi->base + LCDCON1);
+
+ con1 &= ~ENVID;
+
+ writel(con1, fbi->base + LCDCON1);
+}
+
+/**
+ * Prepare the video hardware for a specified video mode
+ * @param fb_info Framebuffer information
+ * @param mode The video mode description to initialize
+ * @return 0 on success
+ */
+static int s3cfb_activate_var(struct fb_info *fb_info)
+{
+ struct s3cfb_info *fbi = fb_info->priv;
+ struct fb_videomode *mode = fb_info->mode;
+ unsigned size, hclk, div;
+ uint32_t con1, con2, con3, con4, con5 = 0;
+
+ if (fbi->passive_display != 0) {
+ dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+ * we need at least this amount of memory for the framebuffer
+ */
+ size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
+ if (fbi->memory_size != size || fb_info->screen_base == NULL) {
+ if (fb_info->screen_base)
+ free(fb_info->screen_base);
+ fbi->memory_size = 0;
+ fb_info->screen_base = malloc(size);
+ if (! fb_info->screen_base)
+ return -ENOMEM;
+ memset(fb_info->screen_base, 0, size);
+ fbi->memory_size = size;
+ }
+
+ /* ensure video output is _off_ */
+ writel(0x00000000, fbi->base + LCDCON1);
+
+ hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
+ div = hclk / PICOS2KHZ(mode->pixclock);
+ if (div < 3)
+ div = 3;
+ /* pixel clock is: (hclk) / ((div + 1) * 2) */
+ div += 1;
+ div >>= 1;
+ div -= 1;
+
+ con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
+
+ switch (fb_info->bits_per_pixel) {
+ case 16:
+ con1 |= BPPMODE(12);
+ con5 |= FRM565;
+ con5 |= HWSWP;
+ fb_info->red = def_rgb565[RED];
+ fb_info->green = def_rgb565[GREEN];
+ fb_info->blue = def_rgb565[BLUE];
+ fb_info->transp = def_rgb565[TRANSP];
+ break;
+ case 24:
+ con1 |= BPPMODE(13);
+ /* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
+ fb_info->red = def_rgb888[RED];
+ fb_info->green = def_rgb888[GREEN];
+ fb_info->blue = def_rgb888[BLUE];
+ fb_info->transp = def_rgb888[TRANSP];
+ break;
+ default:
+ dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ /* 'normal' in register description means positive logic */
+ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+ con5 |= INV_HS;
+ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+ con5 |= INV_VS;
+ if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
+ con5 |= INV_DE;
+ if (mode->sync & FB_SYNC_CLK_INVERT)
+ con5 |= INV_CLK; /* display should latch at the rising edge */
+ if (mode->sync & FB_SYNC_DATA_INVERT)
+ con5 |= INV_DTA;
+ if (mode->sync & FB_SYNC_INVERT_PWREN)
+ con5 |= INV_PWREN;
+ if (mode->sync & FB_SYNC_INVERT_LEND)
+ con5 |= INV_LEND;
+ if (mode->sync & FB_SYNC_USE_PWREN)
+ con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
+ if (mode->sync & FB_SYNC_USE_LEND)
+ con5 |= ENA_LEND;
+ if (mode->sync & FB_SYNC_SWAP_BYTES)
+ con5 ^= BSWP;
+ if (mode->sync & FB_SYNC_SWAP_HW)
+ con5 ^= HWSWP;
+
+ /* vertical timing */
+ con2 = SET_VBPD(mode->upper_margin - 1) |
+ SET_LINEVAL(mode->yres - 1) |
+ SET_VFPD(mode->lower_margin - 1) |
+ SET_VSPW(mode->vsync_len - 1);
+
+ /* horizontal timing */
+ con3 = SET_HBPD(mode->left_margin - 1) |
+ SET_HOZVAL(mode->xres - 1) |
+ SET_HFPD(mode->right_margin - 1);
+ con4 = SET_HSPW(mode->hsync_len - 1);
+
+ /* basic timing setup */
+ writel(con1, fbi->base + LCDCON1);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
+ writel(con2, fbi->base + LCDCON2);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
+ writel(con3, fbi->base + LCDCON3);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
+ writel(con4, fbi->base + LCDCON4);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
+ writel(con5, fbi->base + LCDCON5);
+ dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
+
+ dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
+
+ /* framebuffer memory setup */
+ writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
+ size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
+ writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
+ writel(SET_OFFSIZE(0) |
+ SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
+ fbi->base + LCDSADDR3);
+ writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
+
+ return 0;
+}
+
+/**
+ * Print some information about the current hardware state
+ * @param hw_dev S3C video device
+ */
+#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
+static void s3cfb_info(struct device_d *hw_dev)
+{
+ uint32_t con1, addr1, addr2, addr3;
+ struct s3cfb_info *fbi = hw_dev->priv;
+
+ con1 = readl(fbi->base + LCDCON1);
+ addr1 = readl(fbi->base + LCDSADDR1);
+ addr2 = readl(fbi->base + LCDSADDR2);
+ addr3 = readl(fbi->base + LCDSADDR3);
+
+ printf(" Video hardware info:\n");
+ printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
+ printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
+ printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
+ printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
+ printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
+ printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
+}
+#endif
+
+/*
+ * There is only one video hardware instance available.
+ * It makes no sense to dynamically allocate this data
+ */
+static struct fb_ops s3cfb_ops = {
+ .fb_activate_var = s3cfb_activate_var,
+ .fb_enable = s3cfb_enable_controller,
+ .fb_disable = s3cfb_disable_controller,
+};
+
+static struct s3cfb_info fbi = {
+ .info = {
+ .fbops = &s3cfb_ops,
+ },
+};
+
+static int s3cfb_probe(struct device_d *hw_dev)
+{
+ struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
+ int ret;
+
+ if (! pdata)
+ return -ENODEV;
+
+ fbi.base = dev_request_mem_region(hw_dev, 0);
+ writel(0, fbi.base + LCDCON1);
+ writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
+
+ /* just init */
+ fbi.info.priv = &fbi;
+
+ /* add runtime hardware info */
+ fbi.hw_dev = hw_dev;
+ hw_dev->priv = &fbi;
+
+ /* add runtime video info */
+ fbi.info.mode_list = pdata->mode_list;
+ fbi.info.num_modes = pdata->mode_cnt;
+ fbi.info.mode = &fbi.info.mode_list[1];
+ fbi.info.xres = fbi.info.mode->xres;
+ fbi.info.yres = fbi.info.mode->yres;
+ if (pdata->bits_per_pixel)
+ fbi.info.bits_per_pixel = pdata->bits_per_pixel;
+ else
+ fbi.info.bits_per_pixel = 16;
+ fbi.passive_display = pdata->passive_display;
+ fbi.enable = pdata->enable;
+
+ ret = register_framebuffer(&fbi.info);
+ if (ret != 0) {
+ dev_err(hw_dev, "Failed to register framebuffer\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct driver_d s3cfb_driver = {
+ .name = "s3c_fb",
+ .probe = s3cfb_probe,
+#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
+ .info = s3cfb_info,
+#endif
+};
+
+static int s3cfb_init(void)
+{
+ return register_driver(&s3cfb_driver);
+}
+
+device_initcall(s3cfb_init);
+
+/**
+ * The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
+ *
+ * The driver itself currently supports only active TFT LC displays in the follwing manner:
+ *
+ * * True colours
+ * - 16 bpp
+ * - 24 bpp (untested)
+ */
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (5 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 06/14] MACH SAMSUNG/S3C: Reflect the CPU name the LCD driver is for Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family Juergen Beisert
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
There are major differences in the clock tree of the S3C24xx family and the
more recent CPUs of the S3C family. Keep the S3C24XX clock routines separate to
avoid an ifdef hell. But also use generic function names to be able to
share drivers among the S3C family.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 2 +-
arch/arm/mach-samsung/generic.c | 117 +------------------
arch/arm/mach-samsung/include/mach/s3c-clocks.h | 31 +++++
arch/arm/mach-samsung/include/mach/s3c-generic.h | 12 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 11 +--
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
arch/arm/mach-samsung/s3c24xx-clocks.c | 137 ++++++++++++++++++++++
drivers/mci/s3c.c | 10 +-
drivers/serial/serial_s3c24x0.c | 2 +-
drivers/video/s3c24xx.c | 4 +-
10 files changed, 187 insertions(+), 141 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-clocks.h
create mode 100644 arch/arm/mach-samsung/s3c24xx-clocks.c
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index f329cdb..c590180 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,3 +1,3 @@
obj-y += generic.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 3c24b1a..3f6e801 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -28,100 +28,7 @@
#include <clock.h>
#include <io.h>
#include <mach/s3c-iomap.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_mpllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(MPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
- return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_upllclk(void)
-{
- uint32_t m, p, s, reg_val;
-
- reg_val = readl(UPLLCON);
- m = ((reg_val & 0xFF000) >> 12) + 8;
- p = ((reg_val & 0x003F0) >> 4) + 2;
- s = reg_val & 0x3;
-
- return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_fclk(void)
-{
- return s3c24xx_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_hclk(void)
-{
- uint32_t f_clk;
-
- f_clk = s3c24xx_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
- if (readl(CLKDIVN) & 0x02)
- return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
- switch(readl(CLKDIVN) & 0x06) {
- case 2:
- return f_clk >> 1;
- case 4:
- return f_clk >> 2; /* TODO consider CAMDIVN */
- case 6:
- return f_clk / 3; /* TODO consider CAMDIVN */
- }
-#endif
- return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_pclk(void)
-{
- uint32_t p_clk;
-
- p_clk = s3c24xx_get_hclk();
- if (readl(CLKDIVN) & 0x01)
- return p_clk >> 1;
- return p_clk;
-}
-
-/**
- * Calculate the UCLK frequency used by the USB host device
- * @return Current frequency in Hz
- */
-uint32_t s3c24xx_get_uclk(void)
-{
- return s3c24xx_get_upllclk();
-}
+#include <mach/s3c-generic.h>
/**
* Calculate the amount of connected and available memory
@@ -169,26 +76,6 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
-/**
- * Show the user the current clock settings
- */
-int s3c24xx_dump_clocks(void)
-{
- printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
- printf("mpll: %7d kHz\n", s3c24xx_get_mpllclk() / 1000);
- printf("upll: %7d kHz\n", s3c24xx_get_upllclk() / 1000);
- printf("fclk: %7d kHz\n", s3c24xx_get_fclk() / 1000);
- printf("hclk: %7d kHz\n", s3c24xx_get_hclk() / 1000);
- printf("pclk: %7d kHz\n", s3c24xx_get_pclk() / 1000);
- printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
- s3c24xx_get_hclk() / 1000000);
- return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
-
static uint64_t s3c24xx_clocksource_read(void)
{
/* note: its a down counter */
@@ -203,7 +90,7 @@ static struct clocksource cs = {
static int clocksource_init (void)
{
- uint32_t p_clk = s3c24xx_get_pclk();
+ uint32_t p_clk = s3c_get_pclk();
writel(0x00000000, TCON); /* stop all timers */
writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
new file mode 100644
index 0000000..44b2a6c
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C_CLOCKS_H
+# define __MACH_S3C_CLOCKS_H
+
+#ifdef CONFIG_ARCH_S3C24xx
+# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
+# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
+# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
+# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
+# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
+# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
+
+# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
+# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
+# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
+#endif
+
+#endif /* __MACH_S3C_CLOCKS_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index b8abcf1..33f025d 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -24,10 +24,10 @@
* MA 02111-1307 USA
*/
-uint32_t s3c24xx_get_mpllclk(void);
-uint32_t s3c24xx_get_upllclk(void);
-uint32_t s3c24xx_get_fclk(void);
-uint32_t s3c24xx_get_hclk(void);
-uint32_t s3c24xx_get_pclk(void);
-uint32_t s3c24xx_get_uclk(void);
+uint32_t s3c_get_mpllclk(void);
+uint32_t s3c_get_upllclk(void);
+uint32_t s3c_get_fclk(void);
+uint32_t s3c_get_hclk(void);
+uint32_t s3c_get_pclk(void);
+uint32_t s3c_get_uclk(void);
uint32_t s3c24x0_get_memory_size(void);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index a990d80..7cedf6a 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -25,7 +25,7 @@
#define S3C2410_USB_HOST_BASE 0x49000000
#define S3C2410_INTERRUPT_BASE 0x4A000000
#define S3C2410_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C_CLOCK_POWER_BASE 0x4C000000
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
@@ -40,15 +40,6 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
-/* Clock control (direct access) */
-
-#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
-#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
-#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
-#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
-#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
-#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
-
/* Timer (direct access) */
#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index 8529283..e2e3fc0 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -77,7 +77,7 @@ routine very early in your board_init_lowlevel routine.
.globl s3c24x0_pll_init
s3c24x0_pll_init:
- mov r0, #S3C24X0_CLOCK_POWER_BASE
+ mov r0, #S3C_CLOCK_POWER_BASE
/* configure internal clock ratio */
mov r1, #BOARD_SPECIFIC_CLKDIVN
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
new file mode 100644
index 0000000..beacc76
--- /dev/null
+++ b/arch/arm/mach-samsung/s3c24xx-clocks.c
@@ -0,0 +1,137 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-clocks.h>
+
+/**
+ * Calculate the current M-PLL clock.
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_mpllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(S3C_MPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+#ifdef CONFIG_CPU_S3C2410
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
+#endif
+}
+
+/**
+ * Calculate the current U-PLL clock
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_upllclk(void)
+{
+ uint32_t m, p, s, reg_val;
+
+ reg_val = readl(S3C_UPLLCON);
+ m = ((reg_val & 0xFF000) >> 12) + 8;
+ p = ((reg_val & 0x003F0) >> 4) + 2;
+ s = reg_val & 0x3;
+
+ return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+/**
+ * Calculate the FCLK frequency used for the ARM CPU core
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_fclk(void)
+{
+ return s3c_get_mpllclk();
+}
+
+/**
+ * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_hclk(void)
+{
+ uint32_t f_clk;
+
+ f_clk = s3c_get_fclk();
+#ifdef CONFIG_CPU_S3C2410
+ if (readl(S3C_CLKDIVN) & 0x02)
+ return f_clk >> 1;
+#endif
+#ifdef CONFIG_CPU_S3C2440
+ switch(readl(S3C_CLKDIVN) & 0x06) {
+ case 2:
+ return f_clk >> 1;
+ case 4:
+ return f_clk >> 2; /* TODO consider CAMDIVN */
+ case 6:
+ return f_clk / 3; /* TODO consider CAMDIVN */
+ }
+#endif
+ return f_clk;
+}
+
+/**
+ * Calculate the PCLK frequency used for the slower peripherals
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_pclk(void)
+{
+ uint32_t p_clk;
+
+ p_clk = s3c_get_hclk();
+ if (readl(S3C_CLKDIVN) & 0x01)
+ return p_clk >> 1;
+ return p_clk;
+}
+
+/**
+ * Calculate the UCLK frequency used by the USB host device
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24_get_uclk(void)
+{
+ return s3c_get_upllclk();
+}
+
+/**
+ * Show the user the current clock settings
+ */
+int s3c24xx_dump_clocks(void)
+{
+ printf("refclk: %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
+ printf("mpll: %7d kHz\n", s3c_get_mpllclk() / 1000);
+ printf("upll: %7d kHz\n", s3c_get_upllclk() / 1000);
+ printf("fclk: %7d kHz\n", s3c_get_fclk() / 1000);
+ printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
+ printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
+ printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000);
+ if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ s3c_get_hclk() / 1000000);
+ return 0;
+}
+
+late_initcall(s3c24xx_dump_clocks);
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index 12d2c03..7babab4 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -191,7 +191,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
if (nc == 0)
return 0;
- clock = s3c24xx_get_pclk();
+ clock = s3c_get_pclk();
/* Calculate the required prescaler value to get the requested frequency */
mci_psc = (clock + (nc >> 2)) / nc;
@@ -760,8 +760,8 @@ static int s3c_mci_probe(struct device_d *hw_dev)
struct s3c_mci_platform_data *pd = hw_dev->platform_data;
/* TODO replace by the global func: enable the SDI unit clock */
- writel(readl(S3C24X0_CLOCK_POWER_BASE + 0x0c) | 0x200,
- S3C24X0_CLOCK_POWER_BASE + 0x0c);
+ writel(readl(S3C_CLOCK_POWER_BASE + 0x0c) | 0x200,
+ S3C_CLOCK_POWER_BASE + 0x0c);
if (pd == NULL) {
pr_err("Missing platform data\n");
@@ -775,8 +775,8 @@ static int s3c_mci_probe(struct device_d *hw_dev)
/* feed forward the platform specific values */
mci_pdata.voltages = pd->voltages;
mci_pdata.host_caps = pd->caps;
- mci_pdata.f_min = pd->f_min == 0 ? s3c24xx_get_pclk() / 256 : pd->f_min;
- mci_pdata.f_max = pd->f_max == 0 ? s3c24xx_get_pclk() / 2 : pd->f_max;
+ mci_pdata.f_min = pd->f_min == 0 ? s3c_get_pclk() / 256 : pd->f_min;
+ mci_pdata.f_max = pd->f_max == 0 ? s3c_get_pclk() / 2 : pd->f_max;
/*
* Start the clock to let the engine and the card finishes its startup
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 4e95e5c..4191a49 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -48,7 +48,7 @@ static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
unsigned val;
/* value is calculated so : PCLK / (16 * baudrate) -1 */
- val = s3c24xx_get_pclk() / (16 * baudrate) - 1;
+ val = s3c_get_pclk() / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
return 0;
diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c
index 75677c3..f6af773 100644
--- a/drivers/video/s3c24xx.c
+++ b/drivers/video/s3c24xx.c
@@ -227,7 +227,7 @@ static int s3cfb_activate_var(struct fb_info *fb_info)
/* ensure video output is _off_ */
writel(0x00000000, fbi->base + LCDCON1);
- hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
+ hclk = s3c_get_hclk() / 1000U; /* hclk in kHz */
div = hclk / PICOS2KHZ(mode->pixclock);
if (div < 3)
div = 3;
@@ -339,7 +339,7 @@ static void s3cfb_info(struct device_d *hw_dev)
addr3 = readl(fbi->base + LCDSADDR3);
printf(" Video hardware info:\n");
- printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
+ printf(" Video clock is running at %u Hz\n", s3c_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (6 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 07/14] MACH SAMSUNG/S3C: Separate S3C24XX clock management Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for Juergen Beisert
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
This patch just move the clocksource functions out of the generic.c source file
to handle it on a per CPU base later on.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/Makefile | 2 +-
arch/arm/mach-samsung/generic.c | 33 ----------------------
arch/arm/mach-samsung/s3c-timer.c | 55 +++++++++++++++++++++++++++++++++++++
3 files changed, 56 insertions(+), 34 deletions(-)
create mode 100644 arch/arm/mach-samsung/s3c-timer.c
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index c590180..2ba5c3f 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,3 +1,3 @@
-obj-y += generic.o
+obj-y += s3c-timer.o generic.o
obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 3f6e801..83222e1 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -76,39 +76,6 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
-static uint64_t s3c24xx_clocksource_read(void)
-{
- /* note: its a down counter */
- return 0xFFFF - readw(TCNTO4);
-}
-
-static struct clocksource cs = {
- .read = s3c24xx_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 10,
-};
-
-static int clocksource_init (void)
-{
- uint32_t p_clk = s3c_get_pclk();
-
- writel(0x00000000, TCON); /* stop all timers */
- writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, TCFG1); /* /16 */
-
- writew(0xffff, TCNTB4); /* reload value is TOP */
-
- writel(0x00600000, TCON); /* force a first reload */
- writel(0x00400000, TCON);
- writel(0x00500000, TCON); /* enable timer 4 with auto reload */
-
- cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
- init_clock(&cs);
-
- return 0;
-}
-core_initcall(clocksource_init);
-
void __noreturn reset_cpu(unsigned long addr)
{
/* Disable watchdog */
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
new file mode 100644
index 0000000..2b0b38a
--- /dev/null
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -0,0 +1,55 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+
+static uint64_t s3c24xx_clocksource_read(void)
+{
+ /* note: its a down counter */
+ return 0xFFFF - readw(TCNTO4);
+}
+
+static struct clocksource cs = {
+ .read = s3c24xx_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(16),
+ .shift = 10,
+};
+
+static int clocksource_init(void)
+{
+ uint32_t p_clk = s3c_get_pclk();
+
+ writel(0x00000000, TCON); /* stop all timers */
+ writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
+ writel(0x00030000, TCFG1); /* /16 */
+
+ writew(0xffff, TCNTB4); /* reload value is TOP */
+
+ writel(0x00600000, TCON); /* force a first reload */
+ writel(0x00400000, TCON);
+ writel(0x00500000, TCON); /* enable timer 4 with auto reload */
+
+ cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
+ init_clock(&cs);
+
+ return 0;
+}
+core_initcall(clocksource_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (7 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 08/14] MACH SAMSUNG/S3C: Separate the clocksource for the S3C family Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver Juergen Beisert
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Most members of the S3Cxxxx family share similar timer units. But they are
not really register compatible. To reflect this, use a separate name space for
the S3C family.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 20 +-------------
arch/arm/mach-samsung/s3c-timer.c | 33 ++++++++++++++++++------
2 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 7cedf6a..807660a 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -29,7 +29,7 @@
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
#define S3C24X0_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
@@ -40,24 +40,6 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
-/* Timer (direct access) */
-#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
-#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
-#define TCON (S3C24X0_TIMER_BASE + 0x08)
-#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
-#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
-#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
-#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
-#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
-#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
-#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
-#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
-#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
-#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
-#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
-#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
-#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
-#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
/* Watchdog (direct access) */
#define WTCON (S3C24X0_WATCHDOG_BASE)
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
index 2b0b38a..d9dae55 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -21,10 +21,27 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
+#define S3C_TCFG0 (S3C_TIMER_BASE + 0x00)
+# define S3C_TCFG0_T4MASK 0xff00
+# define S3C_TCFG0_SET_PSCL234(x) ((x) << 8)
+# define S3C_TCFG0_GET_PSCL234(x) (((x) >> 8) & 0xff)
+#define S3C_TCFG1 (S3C_TIMER_BASE + 0x04)
+# define S3C_TCFG1_T4MASK 0xf0000
+# define S3C_TCFG1_SET_T4MUX(x) ((x) << 16)
+# define S3C_TCFG1_GET_T4MUX(x) (((x) >> 16) & 0xf)
+#define S3C_TCON (S3C_TIMER_BASE + 0x08)
+# define S3C_TCON_T4MASK (7 << 20)
+# define S3C_TCON_T4START (1 << 20)
+# define S3C_TCON_T4MANUALUPD (1 << 21)
+# define S3C_TCON_T4RELOAD (1 <<22)
+#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
+#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
+
+
static uint64_t s3c24xx_clocksource_read(void)
{
/* note: its a down counter */
- return 0xFFFF - readw(TCNTO4);
+ return 0xFFFF - readw(S3C_TCNTO4);
}
static struct clocksource cs = {
@@ -37,15 +54,15 @@ static int clocksource_init(void)
{
uint32_t p_clk = s3c_get_pclk();
- writel(0x00000000, TCON); /* stop all timers */
- writel(0x00ffffff, TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, TCFG1); /* /16 */
+ writel(0x00000000, S3C_TCON); /* stop all timers */
+ writel(0x00ffffff, S3C_TCFG0); /* PCLK / (255 + 1) for timer 4 */
+ writel(0x00030000, S3C_TCFG1); /* /16 */
- writew(0xffff, TCNTB4); /* reload value is TOP */
+ writew(0xffff, S3C_TCNTB4); /* reload value is TOP */
- writel(0x00600000, TCON); /* force a first reload */
- writel(0x00400000, TCON);
- writel(0x00500000, TCON); /* enable timer 4 with auto reload */
+ writel(0x00600000, S3C_TCON); /* force a first reload */
+ writel(0x00400000, S3C_TCON);
+ writel(0x00500000, S3C_TCON); /* enable timer 4 with auto reload */
cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
init_clock(&cs);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (8 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 09/14] MACH SAMSUNG/S3C: Rename register macros to reflect the MACH they are valid for Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family Juergen Beisert
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
After separation and after all S3C macros are now present, change the driver
to be more generic for future additions.
The timer registers in the S3C24XX family are only 16 bit wide. But these
registers can be read and written in a 32 bit manner. This is important to share
code with more recent CPUs which comes with 32 bit registers.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/s3c-timer.c | 78 ++++++++++++++++++++++++++++--------
1 files changed, 60 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
index d9dae55..6665c8c 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -37,36 +37,78 @@
#define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
#define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
+#define TIMER_WIDTH 16
+#define TIMER_SHIFT 10
+#define PRE_MUX 3
+#define PRE_MUX_ADD 1
+static const uint32_t max = 0x0000ffff;
-static uint64_t s3c24xx_clocksource_read(void)
+static void s3c_init_t4_clk_source(void)
+{
+ unsigned reg;
+
+ reg = readl(S3C_TCON) & ~S3C_TCON_T4MASK; /* stop timer 4 */
+ writel(reg, S3C_TCON);
+ reg = readl(S3C_TCFG0) & ~S3C_TCFG0_T4MASK;
+ reg |= S3C_TCFG0_SET_PSCL234(0); /* 0 means pre scaler is '256' */
+ writel(reg, S3C_TCFG0);
+ reg = readl(S3C_TCFG1) & ~S3C_TCFG1_T4MASK;
+ reg |= S3C_TCFG1_SET_T4MUX(PRE_MUX); /* / 16 */
+ writel(reg, S3C_TCFG1);
+}
+
+static unsigned s3c_get_t4_clk(void)
+{
+ unsigned clk = s3c_get_pclk();
+ unsigned pre = S3C_TCFG0_GET_PSCL234(readl(S3C_TCFG0)) + 1;
+ unsigned div = S3C_TCFG1_GET_T4MUX(readl(S3C_TCFG1)) + PRE_MUX_ADD;
+
+ return clk / pre / (1 << div);
+}
+
+static void s3c_timer_init(void)
+{
+ unsigned tcon;
+
+ tcon = readl(S3C_TCON) & ~S3C_TCON_T4MASK;
+
+ writel(max, S3C_TCNTB4); /* reload value */
+ /* force a manual counter update */
+ writel(tcon | S3C_TCON_T4MANUALUPD, S3C_TCON);
+}
+
+static void s3c_timer_start(void)
+{
+ unsigned tcon;
+
+ tcon = readl(S3C_TCON) & ~S3C_TCON_T4MANUALUPD;
+ tcon |= S3C_TCON_T4START | S3C_TCON_T4RELOAD;
+ writel(tcon, S3C_TCON);
+}
+
+static uint64_t s3c_clocksource_read(void)
{
/* note: its a down counter */
- return 0xFFFF - readw(S3C_TCNTO4);
+ return max - readl(S3C_TCNTO4);
}
static struct clocksource cs = {
- .read = s3c24xx_clocksource_read,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 10,
+ .read = s3c_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(TIMER_WIDTH),
+ .shift = TIMER_SHIFT,
};
-static int clocksource_init(void)
+static int s3c_clk_src_init(void)
{
- uint32_t p_clk = s3c_get_pclk();
-
- writel(0x00000000, S3C_TCON); /* stop all timers */
- writel(0x00ffffff, S3C_TCFG0); /* PCLK / (255 + 1) for timer 4 */
- writel(0x00030000, S3C_TCFG1); /* /16 */
-
- writew(0xffff, S3C_TCNTB4); /* reload value is TOP */
+ /* select its clock source first */
+ s3c_init_t4_clk_source();
- writel(0x00600000, S3C_TCON); /* force a first reload */
- writel(0x00400000, S3C_TCON);
- writel(0x00500000, S3C_TCON); /* enable timer 4 with auto reload */
+ s3c_timer_init();
+ s3c_timer_start();
- cs.mult = clocksource_hz2mult(p_clk / ((255 + 1) * 16), cs.shift);
+ cs.mult = clocksource_hz2mult(s3c_get_t4_clk(), cs.shift);
init_clock(&cs);
return 0;
}
-core_initcall(clocksource_init);
+core_initcall(s3c_clk_src_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (9 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 10/14] MACH SAMSUNG/S3C: Re-work the S3C family timer driver Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs Juergen Beisert
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/mach-samsung/generic.c | 10 +++++++---
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 7 +------
arch/arm/mach-samsung/lowlevel-init.S | 2 +-
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 83222e1..4a0c87b 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -76,16 +76,20 @@ uint32_t s3c24x0_get_memory_size(void)
return size;
}
+#define S3C_WTCON (S3C_WATCHDOG_BASE)
+#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
+#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
+
void __noreturn reset_cpu(unsigned long addr)
{
/* Disable watchdog */
- writew(0x0000, WTCON);
+ writew(0x0000, S3C_WTCON);
/* Initialize watchdog timer count register */
- writew(0x0001, WTCNT);
+ writew(0x0001, S3C_WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- writew(0x0021, WTCON);
+ writew(0x0021, S3C_WTCON);
/* loop forever and wait for reset to happen */
while(1)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 807660a..9677803 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -31,7 +31,7 @@
#define S3C24X0_UART_BASE 0x50000000
#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
#define S3C2410_I2S_BASE 0x55000000
#define S3C24X0_GPIO_BASE 0x56000000
@@ -41,11 +41,6 @@
#define S3C2410_SDI_BASE 0x5A000000
-/* Watchdog (direct access) */
-#define WTCON (S3C24X0_WATCHDOG_BASE)
-#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
-#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
-
/*
* if we are booting from NAND, its internal SRAM occures at
* a different address than without this feature
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index e2e3fc0..93ea3ce 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -29,7 +29,7 @@
.globl s3c24x0_disable_wd
s3c24x0_disable_wd:
- ldr r0, =S3C24X0_WATCHDOG_BASE
+ ldr r0, =S3C_WATCHDOG_BASE
mov r1, #0x0
str r1, [r0]
mov pc, lr
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (10 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 11/14] MACH SAMSUNG/S3C: Prepare watchdog unit to be shared in the S3C family Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling Juergen Beisert
2011-12-25 20:38 ` [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
The UART is one of the units which differs only slightly inside the S3C family.
Prepare this driver to share it with more recent CPUs.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 2 +-
arch/arm/boards/a9m2440/a9m2440.c | 2 +-
arch/arm/boards/mini2440/mini2440.c | 2 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 15 +-
drivers/serial/Kconfig | 10 +-
drivers/serial/Makefile | 2 +-
drivers/serial/serial_s3c.c | 188 ++++++++++++++++++++++++
drivers/serial/serial_s3c24x0.c | 172 ----------------------
8 files changed, 204 insertions(+), 189 deletions(-)
create mode 100644 drivers/serial/serial_s3c.c
delete mode 100644 drivers/serial/serial_s3c24x0.c
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 989dcf7..a66afb9 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -167,7 +167,7 @@ void __bare_init nand_boot(void)
static int a9m2410_console_init(void)
{
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 1986efb..077d726 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -168,7 +168,7 @@ void __bare_init nand_boot(void)
static int a9m2440_console_init(void)
{
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 0186465..ec4eb05 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -342,7 +342,7 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
- add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+ add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE, S3C_UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 9677803..7c45c53 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -28,7 +28,7 @@
#define S3C_CLOCK_POWER_BASE 0x4C000000
#define S3C2410_LCD_BASE 0x4D000000
#define S3C24X0_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
+#define S3C_UART_BASE 0x50000000
#define S3C_TIMER_BASE 0x51000000
#define S3C2410_USB_DEVICE_BASE 0x52000140
#define S3C_WATCHDOG_BASE 0x53000000
@@ -52,13 +52,12 @@
#endif
#define NFC_RAM_SIZE 4096
-/* internal UARTs (driver based) */
-#define UART1_BASE (S3C24X0_UART_BASE)
-#define UART1_SIZE 0x4000
-#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
-#define UART2_SIZE 0x4000
-#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
-#define UART3_SIZE 0x4000
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x4000
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
+#define S3C_UART2_SIZE 0x4000
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
+#define S3C_UART3_SIZE 0x4000
/* CS configuration (direct access) */
#define BWSCON (S3C24X0_MEMCTL_BASE)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 592d543..186b596 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -78,16 +78,16 @@ config DRIVER_SERIAL_PL010
help
Enable this to get support for AMBA PL010 based serial devices
-config DRIVER_SERIAL_S3C24X0
- bool "Samsung S3C24X0 serial driver"
+config DRIVER_SERIAL_S3C
+ bool "Samsung S3C serial driver"
depends on ARCH_S3C24xx
default y
help
- Say Y here if you want to use the CONS on a S3C24X0 CPU
+ Say Y here if you want to use the CONS on a Samsung S3C CPU
-config DRIVER_SERIAL_S3C24X0_AUTOSYNC
+config DRIVER_SERIAL_S3C_AUTOSYNC
bool "Enable auto flow"
- depends on DRIVER_SERIAL_S3C24X0
+ depends on DRIVER_SERIAL_S3C
help
Say Y here if you want to use the auto flow feature of this
UART. RTS and CTS will be handled by the hardware when enabled.
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index a702125..e2d56b9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX) += serial_mpc5xxx.o
obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN) += serial_blackfin.o
obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial_ns16550.o
obj-$(CONFIG_DRIVER_SERIAL_PL010) += serial_pl010.o
-obj-$(CONFIG_DRIVER_SERIAL_S3C24X0) += serial_s3c24x0.o
+obj-$(CONFIG_DRIVER_SERIAL_S3C) += serial_s3c.o
obj-$(CONFIG_DRIVER_SERIAL_ALTERA) += serial_altera.o
obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG) += serial_altera_jtag.o
obj-$(CONFIG_DRIVER_SERIAL_PXA) += serial_pxa.o
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
new file mode 100644
index 0000000..b7e0987
--- /dev/null
+++ b/drivers/serial/serial_s3c.c
@@ -0,0 +1,188 @@
+/*
+ * (c) 2009...2011 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * Based on code from:
+ * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <malloc.h>
+#include <io.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-iomap.h>
+
+/* Note: Offsets are for little endian access */
+#define ULCON 0x00 /* line control */
+#define UCON 0x04 /* UART control */
+#define UFCON 0x08 /* FIFO control */
+#define UMCON 0x0c /* modem control */
+#define UTRSTAT 0x10 /* Rx/Tx status */
+#define UERSTAT 0x14 /* error status */
+#define UFSTAT 0x18 /* FIFO status */
+#define UMSTAT 0x1c /* modem status */
+#define UTXH 0x20 /* transmitt */
+#define URXH 0x24 /* receive */
+#define UBRDIV 0x28 /* baudrate generator */
+
+static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
+{
+ unsigned reg = readw(base + UCON);
+
+ switch (reg & 0xc00) {
+ case 0x000:
+ case 0x800:
+ return s3c_get_pclk();
+ case 0x400:
+ break; /* TODO UEXTCLK */
+ case 0xc00:
+ break; /* TODO FCLK/n */
+ }
+
+ return 0; /* not nice, but we can't emit an error message! */
+}
+
+static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+ unsigned val;
+
+ val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
+ writew(val, base + UBRDIV);
+
+ return 0;
+}
+
+static int s3c_serial_init_port(struct console_device *cdev)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+
+ /* FIFO enable, Tx/Rx FIFO clear */
+ writeb(0x07, base + UFCON);
+ writeb(0x00, base + UMCON);
+
+ /* Normal,No parity,1 stop,8 bit */
+ writeb(0x03, base + ULCON);
+ /*
+ * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+ * normal,interrupt or polling
+ */
+ writew(0x0245, base + UCON);
+
+#ifdef CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC
+ writeb(0x10, base + UMCON); /* enable auto flow control */
+#else
+ writeb(0x01, base + UMCON); /* RTS up */
+#endif
+
+ return 0;
+}
+
+static void s3c_serial_putc(struct console_device *cdev, char c)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+
+ /* Wait for Tx FIFO not full */
+ while (!(readb(base + UTRSTAT) & 0x2))
+ ;
+
+ writeb(c, base + UTXH);
+}
+
+static int s3c_serial_tstc(struct console_device *cdev)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+
+ /* If receive fifo is empty, return false */
+ if (readb(base + UTRSTAT) & 0x1)
+ return 1;
+
+ return 0;
+}
+
+static int s3c_serial_getc(struct console_device *cdev)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+
+ /* wait for a character */
+ while (!(readb(base + UTRSTAT) & 0x1))
+ ;
+
+ return readb(base + URXH);
+}
+
+static void s3c_serial_flush(struct console_device *cdev)
+{
+ struct device_d *dev = cdev->dev;
+ void __iomem *base = dev->priv;
+
+ while (!(readb(base + UTRSTAT) & 0x4))
+ ;
+}
+
+static int s3c_serial_probe(struct device_d *dev)
+{
+ struct console_device *cdev;
+
+ cdev = xzalloc(sizeof(struct console_device));
+ dev->type_data = cdev;
+ dev->priv = dev_request_mem_region(dev, 0);
+ cdev->dev = dev;
+ cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
+ cdev->tstc = s3c_serial_tstc;
+ cdev->putc = s3c_serial_putc;
+ cdev->getc = s3c_serial_getc;
+ cdev->flush = s3c_serial_flush;
+ cdev->setbrg = s3c_serial_setbaudrate;
+
+ s3c_serial_init_port(cdev);
+
+ /* Enable UART */
+ console_register(cdev);
+
+ return 0;
+}
+
+static void s3c_serial_remove(struct device_d *dev)
+{
+ struct console_device *cdev = dev->type_data;
+
+ s3c_serial_flush(cdev);
+ free(cdev);
+ dev->type_data = NULL;
+}
+
+static struct driver_d s3c_serial_driver = {
+ .name = "s3c_serial",
+ .probe = s3c_serial_probe,
+ .remove = s3c_serial_remove,
+};
+
+static int s3c_serial_init(void)
+{
+ register_driver(&s3c_serial_driver);
+ return 0;
+}
+
+console_initcall(s3c_serial_init);
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
deleted file mode 100644
index 4191a49..0000000
--- a/drivers/serial/serial_s3c24x0.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * (c) 2009 Juergen Beisert <j.beisert@saschahauer.de>
- *
- * Based on code from:
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <malloc.h>
-#include <io.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-iomap.h>
-
-/* Note: Offsets are for little endian access */
-#define ULCON 0x00 /* line control */
-#define UCON 0x04 /* UART control */
-#define UFCON 0x08 /* FIFO control */
-#define UMCON 0x0c /* modem control */
-#define UTRSTAT 0x10 /* Rx/Tx status */
-#define UERSTAT 0x14 /* error status */
-#define UFSTAT 0x18 /* FIFO status */
-#define UMSTAT 0x1c /* modem status */
-#define UTXH 0x20 /* transmitt */
-#define URXH 0x24 /* receive */
-#define UBRDIV 0x28 /* baudrate generator */
-
-static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
- unsigned val;
-
- /* value is calculated so : PCLK / (16 * baudrate) -1 */
- val = s3c_get_pclk() / (16 * baudrate) - 1;
- writew(val, base + UBRDIV);
-
- return 0;
-}
-
-static int s3c24x0_serial_init_port(struct console_device *cdev)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
-
- /* FIFO enable, Tx/Rx FIFO clear */
- writeb(0x07, base + UFCON);
- writeb(0x00, base + UMCON);
-
- /* Normal,No parity,1 stop,8 bit */
- writeb(0x03, base + ULCON);
- /*
- * tx=level,rx=edge,disable timeout int.,enable rx error int.,
- * normal,interrupt or polling
- */
- writew(0x0245, base + UCON);
-
-#ifdef CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC
- writeb(0x10, base + UMCON); /* enable auto flow control */
-#else
- writeb(0x01, base + UMCON); /* RTS up */
-#endif
-
- return 0;
-}
-
-static void s3c24x0_serial_putc(struct console_device *cdev, char c)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
-
- /* Wait for Tx FIFO not full */
- while (!(readb(base + UTRSTAT) & 0x2))
- ;
-
- writeb(c, base + UTXH);
-}
-
-static int s3c24x0_serial_tstc(struct console_device *cdev)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
-
- /* If receive fifo is empty, return false */
- if (readb(base + UTRSTAT) & 0x1)
- return 1;
-
- return 0;
-}
-
-static int s3c24x0_serial_getc(struct console_device *cdev)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
-
- /* wait for a character */
- while (!(readb(base + UTRSTAT) & 0x1))
- ;
-
- return readb(base + URXH);
-}
-
-static void s3c24x0_serial_flush(struct console_device *cdev)
-{
- struct device_d *dev = cdev->dev;
- void __iomem *base = dev->priv;
-
- while (!(readb(base + UTRSTAT) & 0x4))
- ;
-}
-
-static int s3c24x0_serial_probe(struct device_d *dev)
-{
- struct console_device *cdev;
-
- cdev = xzalloc(sizeof(struct console_device));
- dev->type_data = cdev;
- dev->priv = dev_request_mem_region(dev, 0);
- cdev->dev = dev;
- cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
- cdev->tstc = s3c24x0_serial_tstc;
- cdev->putc = s3c24x0_serial_putc;
- cdev->getc = s3c24x0_serial_getc;
- cdev->flush = s3c24x0_serial_flush;
- cdev->setbrg = s3c24x0_serial_setbaudrate;
-
- s3c24x0_serial_init_port(cdev);
-
- /* Enable UART */
- console_register(cdev);
-
- return 0;
-}
-
-static void s3c24x0_serial_remove(struct device_d *dev)
-{
- struct console_device *cdev = dev->type_data;
-
- s3c24x0_serial_flush(cdev);
- free(cdev);
- dev->type_data = NULL;
-}
-
-static struct driver_d s3c24x0_serial_driver = {
- .name = "s3c24x0_serial",
- .probe = s3c24x0_serial_probe,
- .remove = s3c24x0_serial_remove,
-};
-
-static int s3c24x0_serial_init(void)
-{
- register_driver(&s3c24x0_serial_driver);
- return 0;
-}
-
-console_initcall(s3c24x0_serial_init);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (11 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 12/14] MACH SAMSUNG/S3C: Unify the UART driver for the S3C family of CPUs Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
2011-12-25 20:38 ` [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
Keep common code in the MACH instead of re-inventing it in each platform.
Also use S3C* macros for all memory related register.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 47 ++++++----------------
arch/arm/boards/a9m2410/lowlevel_init.S | 4 +-
arch/arm/boards/a9m2440/a9m2410dev.c | 9 ++--
arch/arm/boards/a9m2440/a9m2440.c | 37 +++++++----------
arch/arm/boards/a9m2440/lowlevel_init.S | 6 +-
arch/arm/boards/mini2440/lowlevel_init.S | 4 +-
arch/arm/boards/mini2440/mini2440.c | 13 +++---
arch/arm/mach-samsung/generic.c | 28 ++++++++-----
arch/arm/mach-samsung/include/mach/s3c-busctl.h | 32 +++++++++++++++
arch/arm/mach-samsung/include/mach/s3c-generic.h | 3 +-
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 39 ++++++------------
arch/arm/mach-samsung/lowlevel-init.S | 4 +-
arch/arm/mach-samsung/s3c24xx-clocks.c | 9 +++-
13 files changed, 119 insertions(+), 116 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c-busctl.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index a66afb9..daaa5c1 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -34,6 +34,8 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
@@ -42,38 +44,13 @@ static struct s3c24x0_nand_platform_data nand_info = {
static int a9m2410_mem_init(void)
{
- resource_size_t size = 0;
- uint32_t reg;
+ resource_size_t size;
/*
- * detect the current memory size
* Note: On this card the second SDRAM page is not used
*/
- reg = readl(BANKSIZE);
-
- switch (reg &= 0x7) {
- case 0:
- size = 32 * 1024 * 1024;
- break;
- case 1:
- size = 64 * 1024 * 1024;
- break;
- case 2:
- size = 128 * 1024 * 1024;
- break;
- case 4:
- size = 2 * 1024 * 1024;
- break;
- case 5:
- size = 4 * 1024 * 1024;
- break;
- case 6:
- size = 8 * 1024 * 1024;
- break;
- case 7:
- size = 16 * 1024 * 1024;
- break;
- }
+ s3c24xx_disable_second_sdram_bank();
+ size = s3c24xx_get_memory_size();
/* ---------- configure the GPIOs ------------- */
writel(0x007FFFFF, GPACON);
@@ -100,7 +77,7 @@ static int a9m2410_mem_init(void)
*/
writel(0x40140, MISCCR);
- arm_add_mem_device("ram0", CS6_BASE, size);
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
return 0;
}
@@ -111,19 +88,19 @@ static int a9m2410_devices_init(void)
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#1 to access the network controller */
reg &= ~0xf0;
reg |= 0xe0;
- writel(0x1350, BANKCON1);
+ writel(0x1350, S3C_BANKCON1);
/* CS#2 to the dual 16550 UART */
reg &= ~0xf00;
reg |= 0x400;
- writel(0x0d50, BANKCON2);
+ writel(0x0d50, S3C_BANKCON2);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
reg = readl(MISCCR);
@@ -138,7 +115,7 @@ static int a9m2410_devices_init(void)
* connected to CS line 1 and interrupt line
* GPIO3, data width is 32 bit
*/
- add_generic_device("smc91c111", -1, NULL, CS1_BASE + 0x300, 16,
+ add_generic_device("smc91c111", -1, NULL, S3C_CS1_BASE + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
@@ -150,7 +127,7 @@ static int a9m2410_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
#endif
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2410);
return 0;
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
index 752c668..a106d53 100644
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ b/arch/arm/boards/a9m2410/lowlevel_init.S
@@ -15,9 +15,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index aa5da88..1da69eb 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -29,6 +29,7 @@
#include <init.h>
#include <io.h>
#include <mach/s3c-iomap.h>
+#include <mach/s3c-busctl.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
@@ -72,19 +73,19 @@ int a9m2410dev_devices_init(void)
writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR);
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#1 to access the network controller */
reg &= ~0xf0;
reg |= 0xe0;
- writel(0x1350, BANKCON1);
+ writel(0x1350, S3C_BANKCON1);
/* CS#2 to the dual 16550 UART */
reg &= ~0xf00;
reg |= 0x400;
- writel(0x0d50, BANKCON2);
+ writel(0x0d50, S3C_BANKCON2);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
reg = readl(MISCCR);
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 077d726..56ae914 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -35,6 +35,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
#include "baseboards.h"
@@ -66,12 +67,6 @@ static int a9m2440_check_for_ram(uint32_t addr)
return rc;
}
-static void a9m2440_disable_second_sdram_bank(void)
-{
- writel(readl(BANKCON7) & ~(0x3 << 15),BANKCON7);
- writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable clock */
-}
-
static int a9m2440_mem_init(void)
{
/*
@@ -80,30 +75,30 @@ static int a9m2440_mem_init(void)
* So we must check here, if the second bank is populated to get the
* correct RAM size.
*/
- switch (readl(BANKSIZE) & 0x7) {
+ switch (readl(S3C_BANKSIZE) & 0x7) {
case 0:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 32 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 1:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 64 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 2:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 128 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
case 4:
case 5:
case 6: /* not supported on this machine */
break;
default:
- if (a9m2440_check_for_ram(S3C24X0_SDRAM_BASE + 16 * 1024 * 1024))
- a9m2440_disable_second_sdram_bank();
+ if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024))
+ s3c24xx_disable_second_sdram_bank();
break;
}
- arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
return 0;
}
@@ -114,14 +109,14 @@ static int a9m2440_devices_init(void)
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#5 to access the network controller */
reg &= ~0x00f00000;
reg |= 0x00d00000; /* 16 bit */
- writel(0x1f4c, BANKCON5);
+ writel(0x1f4c, S3C_BANKCON5);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
#ifdef CONFIG_MACH_A9M2410DEV
a9m2410dev_devices_init();
@@ -140,7 +135,7 @@ static int a9m2440_devices_init(void)
* Connected to CS line 5 + A24 and interrupt line EINT9,
* data width is 16 bit
*/
- add_generic_device("cs8900", -1, NULL, CS5_BASE + (1 << 24) + 0x300, 16,
+ add_generic_device("cs8900", -1, NULL, S3C_CS5_BASE + (1 << 24) + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
@@ -151,7 +146,7 @@ static int a9m2440_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2440);
return 0;
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index bfdd7f0..57ebe3f 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -37,7 +37,7 @@ sdram_init:
ldr r4, [r1]
and r4, r4, #0x3
- ldr r1, =S3C24X0_MEMCTL_BASE
+ ldr r1, =S3C_MEMCTL_BASE
/* configure both SDRAM areas with 32 bit data bus width */
ldr r0, =((0x2 << 24) + (0x2 << 28))
str r0, [r1], #0x1c /* post add register offset for bank6 */
@@ -218,9 +218,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S b/arch/arm/boards/mini2440/lowlevel_init.S
index f114bb7..1c8860a 100644
--- a/arch/arm/boards/mini2440/lowlevel_init.S
+++ b/arch/arm/boards/mini2440/lowlevel_init.S
@@ -17,9 +17,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index ec4eb05..29fd5a8 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -43,6 +43,7 @@
#include <mach/s3c-generic.h>
#include <mach/s3c-mci.h>
#include <mach/s3c24xx-fb.h>
+#include <mach/s3c-busctl.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
@@ -266,7 +267,7 @@ static const unsigned pin_usage[] = {
static int mini2440_mem_init(void)
{
- arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+ arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
return 0;
}
@@ -281,14 +282,14 @@ static int mini2440_devices_init(void)
for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
s3c_gpio_mode(pin_usage[i]);
- reg = readl(BWSCON);
+ reg = readl(S3C_BWSCON);
/* CS#4 to access the network controller */
reg &= ~0x000f0000;
reg |= 0x000d0000; /* 16 bit */
- writel(0x1f4c, BANKCON4);
+ writel(0x1f4c, S3C_BANKCON4);
- writel(reg, BWSCON);
+ writel(reg, S3C_BWSCON);
/* release the reset signal to external devices */
reg = readl(MISCCR);
@@ -298,7 +299,7 @@ static int mini2440_devices_init(void)
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
- add_dm9000_device(0, CS4_BASE + 0x300, CS4_BASE + 0x304,
+ add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
IORESOURCE_MEM_16BIT, &dm9000_data);
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
@@ -316,7 +317,7 @@ static int mini2440_devices_init(void)
IORESOURCE_MEM, &s3c24x0_fb_data);
add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
IORESOURCE_MEM, NULL);
- armlinux_set_bootparams((void*)CS6_BASE + 0x100);
+ armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
return 0;
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 4a0c87b..cbe0321 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -27,55 +27,63 @@
#include <init.h>
#include <clock.h>
#include <io.h>
+#include <sizes.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
/**
* Calculate the amount of connected and available memory
* @return Memory size in bytes
*/
-uint32_t s3c24x0_get_memory_size(void)
+uint32_t s3c24xx_get_memory_size(void)
{
uint32_t reg, size;
/*
* detect the current memory size
*/
- reg = readl(BANKSIZE);
+ reg = readl(S3C_BANKSIZE);
switch (reg & 0x7) {
case 0:
- size = 32 * 1024 * 1024;
+ size = SZ_32M;
break;
case 1:
- size = 64 * 1024 * 1024;
+ size = SZ_64M;
break;
case 2:
- size = 128 * 1024 * 1024;
+ size = SZ_128M;
break;
case 4:
- size = 2 * 1024 * 1024;
+ size = SZ_2M;
break;
case 5:
- size = 4 * 1024 * 1024;
+ size = SZ_4M;
break;
case 6:
- size = 8 * 1024 * 1024;
+ size = SZ_8M;
break;
default:
- size = 16 * 1024 * 1024;
+ size = SZ_16M;
break;
}
/*
* Is bank7 also configured for SDRAM usage?
*/
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
size <<= 1; /* also count this bank */
return size;
}
+void s3c24xx_disable_second_sdram_bank(void)
+{
+ writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
+ writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */
+}
+
#define S3C_WTCON (S3C_WATCHDOG_BASE)
#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-busctl.h b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
new file mode 100644
index 0000000..4bcf0a7
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c-busctl.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C_BUSCTL_H
+# define __MACH_S3C_BUSCTL_H
+
+#define S3C_BWSCON (S3C_MEMCTL_BASE)
+#define S3C_BANKCON0 (S3C_MEMCTL_BASE + 0x04)
+#define S3C_BANKCON1 (S3C_MEMCTL_BASE + 0x08)
+#define S3C_BANKCON2 (S3C_MEMCTL_BASE + 0x0c)
+#define S3C_BANKCON3 (S3C_MEMCTL_BASE + 0x10)
+#define S3C_BANKCON4 (S3C_MEMCTL_BASE + 0x14)
+#define S3C_BANKCON5 (S3C_MEMCTL_BASE + 0x18)
+#define S3C_BANKCON6 (S3C_MEMCTL_BASE + 0x1c)
+#define S3C_BANKCON7 (S3C_MEMCTL_BASE + 0x20)
+#define S3C_REFRESH (S3C_MEMCTL_BASE + 0x24)
+#define S3C_BANKSIZE (S3C_MEMCTL_BASE + 0x28)
+#define S3C_MRSRB6 (S3C_MEMCTL_BASE + 0x2c)
+#define S3C_MRSRB7 (S3C_MEMCTL_BASE + 0x30)
+
+#endif /* __MACH_S3C_BUSCTL_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 33f025d..4ea3dd7 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -30,4 +30,5 @@ uint32_t s3c_get_fclk(void);
uint32_t s3c_get_hclk(void);
uint32_t s3c_get_pclk(void);
uint32_t s3c_get_uclk(void);
-uint32_t s3c24x0_get_memory_size(void);
+uint32_t s3c24xx_get_memory_size(void);
+void s3c24xx_disable_second_sdram_bank(void);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 7c45c53..4f713be 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -19,9 +19,7 @@
*/
/* S3C2410 device base addresses */
-#define S3C24X0_SDRAM_BASE 0x30000000
-#define S3C24X0_SDRAM_END 0x40000000
-#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C_MEMCTL_BASE 0x48000000
#define S3C2410_USB_HOST_BASE 0x49000000
#define S3C2410_INTERRUPT_BASE 0x4A000000
#define S3C2410_DMA_BASE 0x4B000000
@@ -40,6 +38,17 @@
#define S3C2410_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
+/* external IO space */
+#define S3C_CS0_BASE 0x00000000
+#define S3C_CS1_BASE 0x08000000
+#define S3C_CS2_BASE 0x10000000
+#define S3C_CS3_BASE 0x18000000
+#define S3C_CS4_BASE 0x20000000
+#define S3C_CS5_BASE 0x28000000
+#define S3C_CS6_BASE 0x30000000
+
+#define S3C_SDRAM_BASE S3C_CS6_BASE
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
/*
* if we are booting from NAND, its internal SRAM occures at
@@ -59,21 +68,6 @@
#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
#define S3C_UART3_SIZE 0x4000
-/* CS configuration (direct access) */
-#define BWSCON (S3C24X0_MEMCTL_BASE)
-#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
-#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
-#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
-#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
-#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
-#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
-#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
-#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
-#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
-#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
-#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
-#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
-
/* GPIO registers (direct access) */
#define GPACON (S3C24X0_GPIO_BASE)
#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
@@ -133,12 +127,3 @@
# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
#endif
-
-/* external IO space */
-#define CS0_BASE 0x00000000
-#define CS1_BASE 0x08000000
-#define CS2_BASE 0x10000000
-#define CS3_BASE 0x18000000
-#define CS4_BASE 0x20000000
-#define CS5_BASE 0x28000000
-#define CS6_BASE 0x30000000
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S
index 93ea3ce..31c6196 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-init.S
@@ -192,7 +192,7 @@ With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
s3c24x0_sdram_init:
adr r0, SDRAMDATA /* get the current relative address of the table */
- mov r1, #S3C24X0_MEMCTL_BASE
+ mov r1, #S3C_MEMCTL_BASE
mov r2, #6 /* we *know* it contains 6 entries */
ldr r3, [r0], #4 /* write BSWCON first */
@@ -255,7 +255,7 @@ s3c24x0_nand_boot:
* In the case of NOR boot we are running from the same address space.
* Detect this case to handle it correctly.
*/
- mov r1, #S3C24X0_MEMCTL_BASE
+ mov r1, #S3C_MEMCTL_BASE
ldr r3, [r1]
and r3, r3, #0x6
cmp r3, #0x0 /* check for NAND case */
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
index beacc76..a99d1b9 100644
--- a/arch/arm/mach-samsung/s3c24xx-clocks.c
+++ b/arch/arm/mach-samsung/s3c24xx-clocks.c
@@ -21,6 +21,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-clocks.h>
+#include <mach/s3c-busctl.h>
/**
* Calculate the current M-PLL clock.
@@ -127,9 +128,11 @@ int s3c24xx_dump_clocks(void)
printf("fclk: %7d kHz\n", s3c_get_fclk() / 1000);
printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
- printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000);
- if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ printf("SDRAM1: CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
+ s3c_get_hclk() / 1000000);
+ if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n",
+ ((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
s3c_get_hclk() / 1000000);
return 0;
}
--
1.7.7.3
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 14/14] MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs
2011-12-25 20:38 [PATCH] Prepare to add more Samsung S3C CPUs to barebox Juergen Beisert
` (12 preceding siblings ...)
2011-12-25 20:38 ` [PATCH 13/14] MACH SAMSUNG/S3C: Re-work the memory detection and handling Juergen Beisert
@ 2011-12-25 20:38 ` Juergen Beisert
13 siblings, 0 replies; 17+ messages in thread
From: Juergen Beisert @ 2011-12-25 20:38 UTC (permalink / raw)
To: barebox
a) use the more CPU specific S3C* macro names
b) move the register description out of the way, as more recent CPUs using a
different layout and more features
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
arch/arm/boards/a9m2410/a9m2410.c | 41 ++++++------
arch/arm/boards/a9m2440/a9m2410dev.c | 53 +++++++-------
arch/arm/boards/a9m2440/a9m2440.c | 5 +-
arch/arm/boards/a9m2440/lowlevel_init.S | 3 +-
arch/arm/boards/mini2440/mini2440.c | 5 +-
arch/arm/mach-samsung/generic.c | 3 +-
arch/arm/mach-samsung/gpio-s3c24x0.c | 31 ++++----
arch/arm/mach-samsung/include/mach/s3c-iomap.h | 62 +----------------
arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h | 77 +++++++++++++++++++++
9 files changed, 152 insertions(+), 128 deletions(-)
create mode 100644 arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index daaa5c1..adeaacc 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -36,6 +36,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
@@ -53,29 +54,29 @@ static int a9m2410_mem_init(void)
size = s3c24xx_get_memory_size();
/* ---------- configure the GPIOs ------------- */
- writel(0x007FFFFF, GPACON);
- writel(0x00000000, GPCCON);
- writel(0x00000000, GPCUP);
- writel(0x00000000, GPDCON);
- writel(0x00000000, GPDUP);
- writel(0xAAAAAAAA, GPECON);
- writel(0x0000E03F, GPEUP);
- writel(0x00000000, GPBCON); /* all inputs */
- writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
- writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
- writel(0x000000FF, GPFUP);
- writel(readl(GPGDAT) | 0x0010, GPGDAT); /* switch off LCD backlight */
- writel(0xFF00A938, GPGCON); /* switch off USB device */
- writel(0x0000F000, GPGUP);
- writel(readl(GPHDAT) | 0x100, GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
- writel(0x000007FF, GPHUP);
- writel(0x0029FAAA, GPHCON);
+ writel(0x007FFFFF, S3C_GPACON);
+ writel(0x00000000, S3C_GPCCON);
+ writel(0x00000000, S3C_GPCUP);
+ writel(0x00000000, S3C_GPDCON);
+ writel(0x00000000, S3C_GPDUP);
+ writel(0xAAAAAAAA, S3C_GPECON);
+ writel(0x0000E03F, S3C_GPEUP);
+ writel(0x00000000, S3C_GPBCON); /* all inputs */
+ writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
+ writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
+ writel(0x000000FF, S3C_GPFUP);
+ writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT); /* switch off LCD backlight */
+ writel(0xFF00A938, S3C_GPGCON); /* switch off USB device */
+ writel(0x0000F000, S3C_GPGUP);
+ writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
+ writel(0x000007FF, S3C_GPHUP);
+ writel(0x0029FAAA, S3C_GPHCON);
/*
* USB port1 normal, USB port0 normal, USB1 pads for device
* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
* 2nd SDRAM bank off (only bank 1 is used)
*/
- writel(0x40140, MISCCR);
+ writel(0x40140, S3C_MISCCR);
arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
@@ -103,9 +104,9 @@ static int a9m2410_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c
index 1da69eb..bedb0f7 100644
--- a/arch/arm/boards/a9m2440/a9m2410dev.c
+++ b/arch/arm/boards/a9m2440/a9m2410dev.c
@@ -30,6 +30,7 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
/**
* Initialize the CPU to be able to work with the a9m2410dev evaluation board
@@ -39,38 +40,38 @@ int a9m2410dev_devices_init(void)
unsigned int reg;
/* ---------- configure the GPIOs ------------- */
- writel(0x007FFFFF, GPACON);
- writel(0x00000000, GPCCON);
- writel(0x00000000, GPCUP);
- writel(0x00000000, GPDCON);
- writel(0x00000000, GPDUP);
- writel(0xAAAAAAAA, GPECON);
- writel(0x0000E03F, GPEUP);
- writel(0x00000000, GPBCON); /* all inputs */
- writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
- writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
- writel(0x000000FF, GPFUP);
- writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
- writel(0x0100A93A, GPGCON); /* switch on USB device */
- writel(0x0000F000, GPGUP);
- writel(0x0029FAAA, GPHCON);
+ writel(0x007FFFFF, S3C_GPACON);
+ writel(0x00000000, S3C_GPCCON);
+ writel(0x00000000, S3C_GPCUP);
+ writel(0x00000000, S3C_GPDCON);
+ writel(0x00000000, S3C_GPDUP);
+ writel(0xAAAAAAAA, S3C_GPECON);
+ writel(0x0000E03F, S3C_GPEUP);
+ writel(0x00000000, S3C_GPBCON); /* all inputs */
+ writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
+ writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
+ writel(0x000000FF, S3C_GPFUP);
+ writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
+ writel(0x0100A93A, S3C_GPGCON); /* switch on USB device */
+ writel(0x0000F000, S3C_GPGUP);
+ writel(0x0029FAAA, S3C_GPHCON);
- writel((1 << 12) | (0 << 11), GPJDAT);
- writel(0x0016aaaa, GPJCON);
- writel(~((0<<12)| (1<<11)), GPJUP);
+ writel((1 << 12) | (0 << 11), S3C_GPJDAT);
+ writel(0x0016aaaa, S3C_GPJCON);
+ writel(~((0<<12)| (1<<11)), S3C_GPJUP);
- writel((0 << 12) | (0 << 11), GPJDAT);
- writel(0x0016aaaa, GPJCON);
- writel(0x00001fff, GPJUP);
+ writel((0 << 12) | (0 << 11), S3C_GPJDAT);
+ writel(0x0016aaaa, S3C_GPJCON);
+ writel(0x00001fff, S3C_GPJUP);
- writel(0x00000000, DSC0);
- writel(0x00000000, DSC1);
+ writel(0x00000000, S3C_DSC0);
+ writel(0x00000000, S3C_DSC1);
/*
* USB port1 normal, USB port0 normal, USB1 pads for device
* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
*/
- writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR);
+ writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR);
/* ----------- configure the access to the outer space ---------- */
reg = readl(S3C_BWSCON);
@@ -88,9 +89,9 @@ int a9m2410dev_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to the network and UART device */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
return 0;
}
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 56ae914..6c6ccdb 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -36,6 +36,7 @@
#include <mach/s3c24xx-nand.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
#include "baseboards.h"
@@ -123,9 +124,9 @@ static int a9m2440_devices_init(void)
#endif
/* release the reset signal to external devices */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
/* ----------- the devices the boot loader should work with -------- */
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index 57ebe3f..e915a16 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -4,6 +4,7 @@
#include <config.h>
#include <mach/s3c-iomap.h>
+#include <mach/s3c24xx-gpio.h>
.section ".text_bare_init.board_init_lowlevel","ax"
@@ -33,7 +34,7 @@ sdram_init:
* configured yet, these pins show external settings, to detect
* the SDRAM size.
*/
- ldr r1, =GPBDAT
+ ldr r1, =S3C_GPBDAT
ldr r4, [r1]
and r4, r4, #0x3
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 29fd5a8..97e56db 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -44,6 +44,7 @@
#include <mach/s3c-mci.h>
#include <mach/s3c24xx-fb.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
@@ -292,9 +293,9 @@ static int mini2440_devices_init(void)
writel(reg, S3C_BWSCON);
/* release the reset signal to external devices */
- reg = readl(MISCCR);
+ reg = readl(S3C_MISCCR);
reg |= 0x10000;
- writel(reg, MISCCR);
+ writel(reg, S3C_MISCCR);
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index cbe0321..7706be2 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -31,6 +31,7 @@
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
/**
* Calculate the amount of connected and available memory
@@ -81,7 +82,7 @@ uint32_t s3c24xx_get_memory_size(void)
void s3c24xx_disable_second_sdram_bank(void)
{
writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
- writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */
+ writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
}
#define S3C_WTCON (S3C_WATCHDOG_BASE)
diff --git a/arch/arm/mach-samsung/gpio-s3c24x0.c b/arch/arm/mach-samsung/gpio-s3c24x0.c
index 23b2609..4f1c5cc 100644
--- a/arch/arm/mach-samsung/gpio-s3c24x0.c
+++ b/arch/arm/mach-samsung/gpio-s3c24x0.c
@@ -20,6 +20,7 @@
#include <io.h>
#include <mach/s3c-iomap.h>
#include <mach/gpio.h>
+#include <mach/s3c24xx-gpio.h>
static const unsigned char group_offset[] =
{
@@ -45,10 +46,10 @@ void gpio_set_value(unsigned gpio, int value)
offset = group_offset[group];
- reg = readl(GPADAT + offset);
+ reg = readl(S3C_GPADAT + offset);
reg &= ~(1 << bit);
reg |= (!!value) << bit;
- writel(reg, GPADAT + offset);
+ writel(reg, S3C_GPADAT + offset);
}
int gpio_direction_input(unsigned gpio)
@@ -60,9 +61,9 @@ int gpio_direction_input(unsigned gpio)
offset = group_offset[group];
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
return 0;
}
@@ -81,14 +82,14 @@ int gpio_direction_output(unsigned gpio, int value)
gpio_set_value(gpio,value);
/* direction */
if (group == 0) { /* GPA is special */
- reg = readl(GPACON);
+ reg = readl(S3C_GPACON);
reg &= ~(1 << bit);
- writel(reg, GPACON);
+ writel(reg, S3C_GPACON);
} else {
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
reg |= 0x1 << (bit << 1);
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
}
return 0;
@@ -107,7 +108,7 @@ int gpio_get_value(unsigned gpio)
offset = group_offset[group];
/* value */
- reg = readl(GPADAT + offset);
+ reg = readl(S3C_GPADAT + offset);
return !!(reg & (1 << bit));
}
@@ -132,9 +133,9 @@ void s3c_gpio_mode(unsigned gpio_mode)
gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
break;
default:
- reg = readl(GPACON);
+ reg = readl(S3C_GPACON);
reg |= 1 << bit;
- writel(reg, GPACON);
+ writel(reg, S3C_GPACON);
break;
}
return;
@@ -143,12 +144,12 @@ void s3c_gpio_mode(unsigned gpio_mode)
offset = group_offset[group];
if (PU_PRESENT(gpio_mode)) {
- reg = readl(GPACON + offset + 8);
+ reg = readl(S3C_GPACON + offset + 8);
if (GET_PU(gpio_mode))
reg |= (1 << bit); /* set means _disabled_ */
else
reg &= ~(1 << bit);
- writel(reg, GPACON + offset + 8);
+ writel(reg, S3C_GPACON + offset + 8);
}
switch (func) {
@@ -160,10 +161,10 @@ void s3c_gpio_mode(unsigned gpio_mode)
break;
case 2: /* function one */
case 3: /* function two */
- reg = readl(GPACON + offset);
+ reg = readl(S3C_GPACON + offset);
reg &= ~(0x3 << (bit << 1));
reg |= func << (bit << 1);
- writel(reg, GPACON + offset);
+ writel(reg, S3C_GPACON + offset);
break;
}
}
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 4f713be..9e867f8 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -32,7 +32,7 @@
#define S3C_WATCHDOG_BASE 0x53000000
#define S3C2410_I2C_BASE 0x54000000
#define S3C2410_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C_GPIO_BASE 0x56000000
#define S3C2410_RTC_BASE 0x57000000
#define S3C2410_ADC_BASE 0x58000000
#define S3C2410_SPI_BASE 0x59000000
@@ -67,63 +67,3 @@
#define S3C_UART2_SIZE 0x4000
#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
#define S3C_UART3_SIZE 0x4000
-
-/* GPIO registers (direct access) */
-#define GPACON (S3C24X0_GPIO_BASE)
-#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
-
-#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
-#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
-#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
-
-#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
-#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
-#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
-
-#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
-#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
-#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
-
-#define GPECON (S3C24X0_GPIO_BASE + 0x40)
-#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
-#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
-
-#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
-#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
-#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
-
-#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
-#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
-#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
-
-#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
-#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
-#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
-
-#ifdef CONFIG_CPU_S3C2440
-# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
-# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
-# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
-#endif
-
-#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
-#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
-#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
-#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
-#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
-#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
-#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
-#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
-#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
-#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
-#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
-#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
-#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
-#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
-#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
-#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
-
-#ifdef CONFIG_CPU_S3C2440
-# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
-# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
-#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
new file mode 100644
index 0000000..c835974
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_S3C24XX_GPIO_H
+# define __MACH_S3C24XX_GPIO_H
+
+#define S3C_GPACON (S3C_GPIO_BASE)
+#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
+
+#define S3C_GPBCON (S3C_GPIO_BASE + 0x10)
+#define S3C_GPBDAT (S3C_GPIO_BASE + 0x14)
+#define S3C_GPBUP (S3C_GPIO_BASE + 0x18)
+
+#define S3C_GPCCON (S3C_GPIO_BASE + 0x20)
+#define S3C_GPCDAT (S3C_GPIO_BASE + 0x24)
+#define S3C_GPCUP (S3C_GPIO_BASE + 0x28)
+
+#define S3C_GPDCON (S3C_GPIO_BASE + 0x30)
+#define S3C_GPDDAT (S3C_GPIO_BASE + 0x34)
+#define S3C_GPDUP (S3C_GPIO_BASE + 0x38)
+
+#define S3C_GPECON (S3C_GPIO_BASE + 0x40)
+#define S3C_GPEDAT (S3C_GPIO_BASE + 0x44)
+#define S3C_GPEUP (S3C_GPIO_BASE + 0x48)
+
+#define S3C_GPFCON (S3C_GPIO_BASE + 0x50)
+#define S3C_GPFDAT (S3C_GPIO_BASE + 0x54)
+#define S3C_GPFUP (S3C_GPIO_BASE + 0x58)
+
+#define S3C_GPGCON (S3C_GPIO_BASE + 0x60)
+#define S3C_GPGDAT (S3C_GPIO_BASE + 0x64)
+#define S3C_GPGUP (S3C_GPIO_BASE + 0x68)
+
+#define S3C_GPHCON (S3C_GPIO_BASE + 0x70)
+#define S3C_GPHDAT (S3C_GPIO_BASE + 0x74)
+#define S3C_GPHUP (S3C_GPIO_BASE + 0x78)
+
+#ifdef CONFIG_CPU_S3C2440
+# define S3C_GPJCON (S3C_GPIO_BASE + 0xd0)
+# define S3C_GPJDAT (S3C_GPIO_BASE + 0xd4)
+# define S3C_GPJUP (S3C_GPIO_BASE + 0xd8)
+#endif
+
+#define S3C_MISCCR (S3C_GPIO_BASE + 0x80)
+#define S3C_DCLKCON (S3C_GPIO_BASE + 0x84)
+#define S3C_EXTINT0 (S3C_GPIO_BASE + 0x88)
+#define S3C_EXTINT1 (S3C_GPIO_BASE + 0x8c)
+#define S3C_EXTINT2 (S3C_GPIO_BASE + 0x90)
+#define S3C_EINTFLT0 (S3C_GPIO_BASE + 0x94)
+#define S3C_EINTFLT1 (S3C_GPIO_BASE + 0x98)
+#define S3C_EINTFLT2 (S3C_GPIO_BASE + 0x9c)
+#define S3C_EINTFLT3 (S3C_GPIO_BASE + 0xa0)
+#define S3C_EINTMASK (S3C_GPIO_BASE + 0xa4)
+#define S3C_EINTPEND (S3C_GPIO_BASE + 0xa8)
+#define S3C_GSTATUS0 (S3C_GPIO_BASE + 0xac)
+#define S3C_GSTATUS1 (S3C_GPIO_BASE + 0xb0)
+#define S3C_GSTATUS2 (S3C_GPIO_BASE + 0xb4)
+#define S3C_GSTATUS3 (S3C_GPIO_BASE + 0xb8)
+#define S3C_GSTATUS4 (S3C_GPIO_BASE + 0xbc)
+
+#ifdef CONFIG_CPU_S3C2440
+# define S3C_DSC0 (S3C_GPIO_BASE + 0xc4)
+# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
+#endif
+
+#endif /* __MACH_S3C24XX_GPIO_H */
--
1.7.7.3
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