From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 1/3] ARM i.MX51 clk: select uart clk parent based on hardware setting
Date: Fri, 23 Mar 2012 11:36:17 +0100 [thread overview]
Message-ID: <1332498979-13742-2-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1332498979-13742-1-git-send-email-s.hauer@pengutronix.de>
The previous code assumed pll2 which is correct when we set the
uart parent to pll2 beforehand. The reset default is different
though, so calculate uart parent based on hardware setting.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/speed-imx51.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c
index 643ad8f..84f4892 100644
--- a/arch/arm/mach-imx/speed-imx51.c
+++ b/arch/arm/mach-imx/speed-imx51.c
@@ -115,7 +115,15 @@ unsigned long imx_get_uartclk(void)
u32 reg, prediv, podf;
unsigned long parent_rate;
- parent_rate = pll2_sw_get_rate();
+ reg = ccm_readl(MX5_CCM_CSCMR1);
+ reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
+ reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+
+ parent_rate = get_rate_select(reg,
+ pll1_main_get_rate,
+ pll2_sw_get_rate,
+ pll3_sw_get_rate,
+ NULL);
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
--
1.7.9.1
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next prev parent reply other threads:[~2012-03-23 10:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-23 10:36 ARM i.MX51: lowlevel code work Sascha Hauer
2012-03-23 10:36 ` Sascha Hauer [this message]
2012-03-23 10:36 ` [PATCH 2/3] ARM i.MX51 babbage: move lowlevel setup after power init Sascha Hauer
2012-03-23 10:36 ` [PATCH 3/3] ARM i.MX51 lowlevel: setup full cpu speed unconditionally Sascha Hauer
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