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From: Antony Pavlov <antonynpavlov@gmail.com>
To: barebox@lists.infradead.org
Subject: [RFC 3/3] MIPS: cpuinfo: import CPU message from Linux
Date: Mon, 21 May 2012 12:07:11 +0400	[thread overview]
Message-ID: <1337587631-16650-4-git-send-email-antonynpavlov@gmail.com> (raw)
In-Reply-To: <1337587631-16650-1-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/lib/cpuinfo.c |   27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c
index fc8fb00..71477a8 100644
--- a/arch/mips/lib/cpuinfo.c
+++ b/arch/mips/lib/cpuinfo.c
@@ -23,11 +23,34 @@
 #include <common.h>
 #include <command.h>
 #include <asm/mipsregs.h>
+#include <asm/cpu-info.h>
+
+static char *way_string[] /* __cpuinitdata */= { NULL, "direct mapped", "2-way",
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+};
 
 static int do_cpuinfo(int argc, char *argv[])
 {
-	printf("CP0_PRID = 0x%08x\n", read_c0_prid());
-	printf("CP0_CONFIG = 0x%08x\n", read_c0_config());
+	unsigned int icache_size, dcache_size;
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	printk(KERN_INFO "CPU revision is: %08x (%s)\n",
+		current_cpu_data.processor_id, __cpu_name);
+
+	icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+	dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+
+	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+	       icache_size >> 10,
+	       c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
+	       way_string[c->icache.ways], c->icache.linesz);
+
+	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+	       dcache_size >> 10, way_string[c->dcache.ways],
+	       (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+			"cache aliases" : "no aliases",
+	       c->dcache.linesz);
 
 	return 0;
 }
-- 
1.7.10


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  parent reply	other threads:[~2012-05-21  8:07 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-05-21  8:07 [RFC 0/3] MIPS: import CPU and cache detection code " Antony Pavlov
2012-05-21  8:07 ` [RFC 1/3] MIPS: introduce C architecture-specific low-level init Antony Pavlov
2012-05-22  9:29   ` Jean-Christophe PLAGNIOL-VILLARD
2012-05-21  8:07 ` [RFC 2/3] MIPS: import CPU and cache detection code from Linux Antony Pavlov
2012-05-21  8:07 ` Antony Pavlov [this message]
2012-05-21 19:46 ` [RFC 0/3] " Sascha Hauer
2012-05-22  9:31 ` Jean-Christophe PLAGNIOL-VILLARD

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