[RFC] Inclusion of the Samsung S3C6410 SoC

[RFC] Inclusion of the Samsung S3C6410 SoC

[Juergen Beisert]

This patch series tries to include the Samsung S3C6410 processor into Barebox.
This SoC is used on the popular FriendlyARM Mini6410 platform and an
implementation for this platfrom is part of this series. This series is WIP,
so please comment if the changes are ready for mainline or not.

Patches 1..3 prepare the current Samsung part of Barebox to simplify the
changes later on.
Patches 4..10 just change the Samsung UART driver to make it more generic for
all current Samsung SoCs.
Patches 11..17 add the new Samsung S3C6410 SoC support.
Patch 18 adds the Mini6410 platform to make use of all the previous changes.

At least these changes should be tested on the S5Pxx SoCs, as I'm not sure if
the UART driver still works for them.

Regards,
Juergen


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[PATCH 01/18] ARM/Samsung: be able to include the nand header multiple times

[Juergen Beisert]

This is required in preparation for the following patches.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/include/mach/s3c24xx-nand.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
index acd78b8..fa88da1 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -18,6 +18,9 @@
  *
  */
 
+#ifndef MACH_S3C24XX_NAND_H
+# define MACH_S3C24XX_NAND_H
+
 #ifdef CONFIG_S3C_NAND_BOOT
 extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
@@ -52,3 +55,5 @@ struct s3c24x0_nand_platform_data {
  * @file
  * @brief Basic declaration to use the s3c24x0 NAND driver
  */
+
+#endif /* MACH_S3C24XX_NAND_H */
-- 
1.7.10.4


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[PATCH 02/18] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Juergen Beisert]

Barebox crashes since it has trouble with a resource size of 0. Most of the
S3C24XX based platforms crashes at runtime and can't use devices with resource
sizes of 0 anymore. This patch fix it by unifying the device registration for
all current Barebox's S3C24XX based platforms.

- A9M2410 and A9M2440 compile time tested only.
- Mini2440 also runtime tested.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/boards/a9m2410/a9m2410.c                  |    6 +--
 arch/arm/boards/a9m2440/a9m2440.c                  |    7 ++-
 arch/arm/boards/mini2440/mini2440.c                |   16 +++---
 .../mach-samsung/include/mach/devices-s3c24xx.h    |   54 ++++++++++++++++++++
 4 files changed, 65 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h

diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index eaafdbd..c2d4b87 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,6 +32,7 @@
 #include <partition.h>
 #include <nand.h>
 #include <io.h>
+#include <mach/devices-s3c24xx.h>
 #include <mach/s3c-iomap.h>
 #include <mach/s3c24xx-nand.h>
 #include <mach/s3c-generic.h>
@@ -109,8 +110,7 @@ static int a9m2410_devices_init(void)
 	writel(reg, S3C_MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
-			0, IORESOURCE_MEM, &nand_info);
+	s3c24xx_add_nand(&nand_info);
 	/*
 	 * SMSC 91C111 network controller on the baseboard
 	 * connected to CS line 1 and interrupt line
@@ -145,8 +145,6 @@ void __bare_init nand_boot(void)
 
 static int a9m2410_console_init(void)
 {
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 1d20248..8975c15 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,6 +32,7 @@
 #include <partition.h>
 #include <nand.h>
 #include <io.h>
+#include <mach/devices-s3c24xx.h>
 #include <mach/s3c-iomap.h>
 #include <mach/s3c24xx-nand.h>
 #include <mach/s3c-generic.h>
@@ -129,8 +130,7 @@ static int a9m2440_devices_init(void)
 	writel(reg, S3C_MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, 0,
-			   IORESOURCE_MEM, &nand_info);
+	s3c24xx_add_nand(&nand_info);
 	/*
 	 * cs8900 network controller onboard
 	 * Connected to CS line 5 + A24 and interrupt line EINT9,
@@ -164,8 +164,7 @@ void __bare_init nand_boot(void)
 
 static int a9m2440_console_init(void)
 {
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+	s3c24xx_add_uart1();
 	return 0;
 }
 
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 3d3b820..3523949 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,6 +39,7 @@
 #include <io.h>
 #include <mach/gpio.h>
 #include <mach/s3c-iomap.h>
+#include <mach/devices-s3c24xx.h>
 #include <mach/s3c24xx-nand.h>
 #include <mach/s3c-generic.h>
 #include <mach/s3c-mci.h>
@@ -297,8 +298,7 @@ static int mini2440_devices_init(void)
 	reg |= 0x10000;
 	writel(reg, S3C_MISCCR);
 
-	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
-			0, IORESOURCE_MEM, &nand_info);
+	s3c24xx_add_nand(&nand_info);
 
 	add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
 			  IORESOURCE_MEM_16BIT, &dm9000_data);
@@ -312,12 +312,9 @@ static int mini2440_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 #endif
-	add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
-			   IORESOURCE_MEM, &mci_data);
-	add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
-			   IORESOURCE_MEM, &s3c24x0_fb_data);
-	add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
-			   IORESOURCE_MEM, NULL);
+	s3c24xx_add_mci(&mci_data);
+	s3c24xx_add_fb(&s3c24x0_fb_data);
+	s3c24xx_add_ohci();
 	armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_MINI2440);
 
@@ -344,8 +341,7 @@ static int mini2440_console_init(void)
 	s3c_gpio_mode(GPH2_TXD0);
 	s3c_gpio_mode(GPH3_RXD0);
 
-	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
-			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+	s3c24xx_add_uart1();
 	return 0;
 }
 
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
new file mode 100644
index 0000000..d099732
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H
+# define INCLUDE_MACH_DEVICES_S3C24XX_H
+
+#include <mach/s3c24xx-iomap.h>
+#include <mach/s3c24xx-nand.h>
+#include <mach/s3c-mci.h>
+#include <mach/s3c24xx-fb.h>
+
+static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d)
+{
+	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL,
+				S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d)
+{
+	add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL,
+				S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d)
+{
+	add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL,
+				S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d);
+}
+
+static inline void s3c24xx_add_ohci(void)
+{
+	add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL,
+			S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c24xx_add_uart1(void)
+{
+	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
+			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+}
+
+#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */
-- 
1.7.10.4


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[PATCH 03/18] ARM/Samsung: follow the name style of the other source files in this directory

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/Makefile         |    2 +-
 arch/arm/mach-samsung/clocks-s3c24xx.c |  157 ++++++++++++++++++++++++++++++++
 arch/arm/mach-samsung/s3c24xx-clocks.c |  157 --------------------------------
 3 files changed, 158 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/mach-samsung/clocks-s3c24xx.c
 delete mode 100644 arch/arm/mach-samsung/s3c24xx-clocks.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 6020587..091b600 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,6 +1,6 @@
 obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/clocks-s3c24xx.c b/arch/arm/mach-samsung/clocks-s3c24xx.c
new file mode 100644
index 0000000..13e6867
--- /dev/null
+++ b/arch/arm/mach-samsung/clocks-s3c24xx.c
@@ -0,0 +1,157 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-clocks.h>
+#include <mach/s3c-busctl.h>
+
+/**
+ * Calculate the current M-PLL clock.
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_mpllclk(void)
+{
+	uint32_t m, p, s, reg_val;
+
+	reg_val = readl(S3C_MPLLCON);
+	m = ((reg_val & 0xFF000) >> 12) + 8;
+	p = ((reg_val & 0x003F0) >> 4) + 2;
+	s = reg_val & 0x3;
+#ifdef CONFIG_CPU_S3C2410
+	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+	return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
+#endif
+}
+
+/**
+ * Calculate the current U-PLL clock
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_upllclk(void)
+{
+	uint32_t m, p, s, reg_val;
+
+	reg_val = readl(S3C_UPLLCON);
+	m = ((reg_val & 0xFF000) >> 12) + 8;
+	p = ((reg_val & 0x003F0) >> 4) + 2;
+	s = reg_val & 0x3;
+
+	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+/**
+ * Calculate the FCLK frequency used for the ARM CPU core
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_fclk(void)
+{
+	return s3c_get_mpllclk();
+}
+
+/**
+ * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_hclk(void)
+{
+	uint32_t f_clk;
+
+	f_clk = s3c_get_fclk();
+#ifdef CONFIG_CPU_S3C2410
+	if (readl(S3C_CLKDIVN) & 0x02)
+		return f_clk >> 1;
+#endif
+#ifdef CONFIG_CPU_S3C2440
+	switch(readl(S3C_CLKDIVN) & 0x06) {
+	case 2:
+		return f_clk >> 1;
+	case 4:
+		return f_clk >> 2;	/* TODO consider CAMDIVN */
+	case 6:
+		return f_clk / 3;	/* TODO consider CAMDIVN */
+	}
+#endif
+	return f_clk;
+}
+
+/**
+ * Calculate the PCLK frequency used for the slower peripherals
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_pclk(void)
+{
+	uint32_t p_clk;
+
+	p_clk = s3c_get_hclk();
+	if (readl(S3C_CLKDIVN) & 0x01)
+		return p_clk >> 1;
+	return p_clk;
+}
+
+/**
+ * Calculate the UCLK frequency used by the USB host device
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24_get_uclk(void)
+{
+	return s3c_get_upllclk();
+}
+
+/**
+ * Return correct UART frequency based on the UCON register
+ */
+unsigned s3c_get_uart_clk(unsigned src)
+{
+	switch (src & 3) {
+	case 0:
+	case 2:
+		return s3c_get_pclk();
+	case 1:
+		return 0; /* TODO UEXTCLK */
+	case 3:
+		return 0; /* TODO FCLK/n */
+	}
+	return 0; /* not reached, to make compiler happy */
+}
+
+/**
+ * Show the user the current clock settings
+ */
+int s3c24xx_dump_clocks(void)
+{
+	printf("refclk:  %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
+	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
+	printf("upll:    %7d kHz\n", s3c_get_upllclk() / 1000);
+	printf("fclk:    %7d kHz\n", s3c_get_fclk() / 1000);
+	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
+	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
+	printf("SDRAM1:   CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
+						s3c_get_hclk() / 1000000);
+	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+		printf("SDRAM2:   CL%d@%dMHz\n",
+			((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
+			s3c_get_hclk() / 1000000);
+	return 0;
+}
+
+late_initcall(s3c24xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
deleted file mode 100644
index 13e6867..0000000
--- a/arch/arm/mach-samsung/s3c24xx-clocks.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <clock.h>
-#include <io.h>
-#include <mach/s3c-iomap.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-clocks.h>
-#include <mach/s3c-busctl.h>
-
-/**
- * Calculate the current M-PLL clock.
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_mpllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_MPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-#ifdef CONFIG_CPU_S3C2410
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p << s));
-#endif
-}
-
-/**
- * Calculate the current U-PLL clock
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_upllclk(void)
-{
-	uint32_t m, p, s, reg_val;
-
-	reg_val = readl(S3C_UPLLCON);
-	m = ((reg_val & 0xFF000) >> 12) + 8;
-	p = ((reg_val & 0x003F0) >> 4) + 2;
-	s = reg_val & 0x3;
-
-	return (S3C24XX_CLOCK_REFERENCE * m) / (p << s);
-}
-
-/**
- * Calculate the FCLK frequency used for the ARM CPU core
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_fclk(void)
-{
-	return s3c_get_mpllclk();
-}
-
-/**
- * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_hclk(void)
-{
-	uint32_t f_clk;
-
-	f_clk = s3c_get_fclk();
-#ifdef CONFIG_CPU_S3C2410
-	if (readl(S3C_CLKDIVN) & 0x02)
-		return f_clk >> 1;
-#endif
-#ifdef CONFIG_CPU_S3C2440
-	switch(readl(S3C_CLKDIVN) & 0x06) {
-	case 2:
-		return f_clk >> 1;
-	case 4:
-		return f_clk >> 2;	/* TODO consider CAMDIVN */
-	case 6:
-		return f_clk / 3;	/* TODO consider CAMDIVN */
-	}
-#endif
-	return f_clk;
-}
-
-/**
- * Calculate the PCLK frequency used for the slower peripherals
- * @return Current frequency in Hz
- */
-uint32_t s3c_get_pclk(void)
-{
-	uint32_t p_clk;
-
-	p_clk = s3c_get_hclk();
-	if (readl(S3C_CLKDIVN) & 0x01)
-		return p_clk >> 1;
-	return p_clk;
-}
-
-/**
- * Calculate the UCLK frequency used by the USB host device
- * @return Current frequency in Hz
- */
-uint32_t s3c24_get_uclk(void)
-{
-	return s3c_get_upllclk();
-}
-
-/**
- * Return correct UART frequency based on the UCON register
- */
-unsigned s3c_get_uart_clk(unsigned src)
-{
-	switch (src & 3) {
-	case 0:
-	case 2:
-		return s3c_get_pclk();
-	case 1:
-		return 0; /* TODO UEXTCLK */
-	case 3:
-		return 0; /* TODO FCLK/n */
-	}
-	return 0; /* not reached, to make compiler happy */
-}
-
-/**
- * Show the user the current clock settings
- */
-int s3c24xx_dump_clocks(void)
-{
-	printf("refclk:  %7d kHz\n", S3C24XX_CLOCK_REFERENCE / 1000);
-	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
-	printf("upll:    %7d kHz\n", s3c_get_upllclk() / 1000);
-	printf("fclk:    %7d kHz\n", s3c_get_fclk() / 1000);
-	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
-	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
-	printf("SDRAM1:   CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2,
-						s3c_get_hclk() / 1000000);
-	if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
-		printf("SDRAM2:   CL%d@%dMHz\n",
-			((readl(S3C_BANKCON7) & 0xc) >> 2) + 2,
-			s3c_get_hclk() / 1000000);
-	return 0;
-}
-
-late_initcall(s3c24xx_dump_clocks);
-- 
1.7.10.4


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[PATCH 04/18] Samsung/serial: remove more ugly ifdef lines

[Juergen Beisert]

More or less just cosmetic. Easier to read, and lets the compiler remove unused
code.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/serial_s3c.c |    9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 7a9b355..ff3792b 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -115,11 +115,10 @@ static int s3c_serial_init_port(struct console_device *cdev)
 	writeb(0xf, base + UINTM);
 #endif
 
-#ifdef CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC
-	writeb(0x10, base + UMCON); /* enable auto flow control */
-#else
-	writeb(0x01, base + UMCON); /* RTS up */
-#endif
+	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
+		writeb(0x10, base + UMCON); /* enable auto flow control */
+	else
+		writeb(0x01, base + UMCON); /* RTS up */
 
 	return 0;
 }
-- 
1.7.10.4


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[PATCH 05/18] Samsung/serial: make the clock source configureable

[Juergen Beisert]

Instead of taking the value from somewhere, use the menu to select one. Also
provide sane default values for known SoCs.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/Kconfig      |   12 ++++++++++++
 drivers/serial/serial_s3c.c |    7 +------
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a9383da..a118aaf 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -85,6 +85,18 @@ config DRIVER_SERIAL_S3C
 	help
 	  Say Y here if you want to use the CONS on a Samsung S3C CPU
 
+config DRIVER_SERIAL_S3C_CLK
+	int
+	prompt "input clock reference"
+	depends on DRIVER_SERIAL_S3C
+	default 0 if ARCH_S3C24xx
+	default 3 if ARCH_S5PCxx
+	help
+	  Select one of up to four available clock sources for the UART:
+	   0+1: PCLK, 2: UCLK0, 3: UCLK1
+	  Note: not all values are possible on all Samsung SoCs. Read the
+	  manual if unsure.
+
 config DRIVER_SERIAL_S3C_AUTOSYNC
 	bool "Enable auto flow"
 	depends on DRIVER_SERIAL_S3C
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index ff3792b..5c05ba8 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -47,11 +47,6 @@
 # define UINTM 0x38		/* interrupt mask register */
 #endif
 
-#ifndef S3C_UART_CLKSEL
-/* Use pclk */
-# define S3C_UART_CLKSEL 0
-#endif
-
 struct s3c_uart {
 	void __iomem *regs;
 	struct console_device cdev;
@@ -108,7 +103,7 @@ static int s3c_serial_init_port(struct console_device *cdev)
 
 	/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal, interrupt or polling, no pre-divider */
-	writew(0x0245 | ((S3C_UART_CLKSEL) << 10), base + UCON);
+	writew(0x0245 | ((CONFIG_DRIVER_SERIAL_S3C_CLK) << 10), base + UCON);
 
 #ifdef S3C_UART_HAS_UINTM
 	/* 'interrupt or polling mode' for both directions */
-- 
1.7.10.4


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[PATCH 06/18] Samsung/serial: make the code more readable

[Juergen Beisert]

This bit magic is just setting and reading the UART's selected clock source.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/serial_s3c.c |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 5c05ba8..a4c1f68 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -31,6 +31,8 @@
 /* Note: Offsets are for little endian access */
 #define ULCON 0x00		/* line control */
 #define UCON 0x04		/* UART control */
+# define UCON_SET_CLK_SRC(x) (((x) & 0x03) << 10)
+# define UCON_GET_CLK_SRC(x) (((x) >> 10) & 0x03)
 #define UFCON 0x08		/* FIFO control */
 #define UMCON 0x0c		/* modem control */
 #define UTRSTAT 0x10		/* Rx/Tx status */
@@ -57,8 +59,7 @@ struct s3c_uart {
 static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
 {
 	unsigned reg = readw(base + UCON);
-	reg = (reg >> 10) & 0x3;
-	return s3c_get_uart_clk(reg);
+	return s3c_get_uart_clk(UCON_GET_CLK_SRC(reg));
 }
 
 #ifdef S3C_UART_HAS_UBRDIVSLOT
@@ -103,7 +104,8 @@ static int s3c_serial_init_port(struct console_device *cdev)
 
 	/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal, interrupt or polling, no pre-divider */
-	writew(0x0245 | ((CONFIG_DRIVER_SERIAL_S3C_CLK) << 10), base + UCON);
+	writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
+						base + UCON);
 
 #ifdef S3C_UART_HAS_UINTM
 	/* 'interrupt or polling mode' for both directions */
-- 
1.7.10.4


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[PATCH 07/18] Samsung/serial: there is no need to ifdef these register defines

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/serial_s3c.c |    8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index a4c1f68..125c06b 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -42,12 +42,8 @@
 #define UTXH 0x20		/* transmitt */
 #define URXH 0x24		/* receive */
 #define UBRDIV 0x28		/* baudrate generator */
-#ifdef S3C_UART_HAS_UBRDIVSLOT
-# define UBRDIVSLOT 0x2c	/* baudrate slot generator */
-#endif
-#ifdef S3C_UART_HAS_UINTM
-# define UINTM 0x38		/* interrupt mask register */
-#endif
+#define UBRDIVSLOT 0x2c		/* baudrate slot generator */
+#define UINTM 0x38		/* interrupt mask register */
 
 struct s3c_uart {
 	void __iomem *regs;
-- 
1.7.10.4


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[PATCH 08/18] Samsung/serial: there is no need to ifdef the slot table

[Juergen Beisert]

The '__maybe_unused' attribute prevents the compiler from warning about an
unused variable and the 'static' will remove it entirely if it's not used.
This patch is only cosmetic.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/serial_s3c.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 125c06b..a2b8e56 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -58,7 +58,6 @@ static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
 	return s3c_get_uart_clk(UCON_GET_CLK_SRC(reg));
 }
 
-#ifdef S3C_UART_HAS_UBRDIVSLOT
 /*
  * This table takes the fractional value of the baud divisor and gives
  * the recommended setting for the UDIVSLOT register. Refer the datasheet
@@ -68,7 +67,6 @@ static const uint16_t udivslot_table[] __maybe_unused = {
 	0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4A52, 0x54AA,
 	0x5555, 0xD555, 0xD5D5, 0xDDD5, 0xDDDD, 0xDFDD, 0xDFDF, 0xFFDF,
 };
-#endif
 
 static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
 {
-- 
1.7.10.4


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[PATCH 09/18] Samsung/serial: move the decision about an improved UART into Kconfig

[Juergen Beisert]

More or less just cosmetic (removing ifdefs!).

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/Kconfig                     |    5 +++++
 arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h |    2 --
 drivers/serial/serial_s3c.c                       |   16 ++++++++--------
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 90cda30..28bbc97 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -20,6 +20,9 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
 	hex
 	default 0x1ff0 if ARCH_S5PCxx
 
+config SAMSUNG_IMPROVED_UART
+	bool
+
 if ARCH_S3C24xx
 
 config CPU_S3C2410
@@ -89,9 +92,11 @@ endif
 if ARCH_S5PCxx
 
 config CPU_S5PC110
+	select SAMSUNG_IMPROVED_UART
 	bool
 
 config CPU_S5PV210
+	select SAMSUNG_IMPROVED_UART
 	bool
 
 choice
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
index 248f868..448e3b8 100644
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
@@ -45,8 +45,6 @@
 #define S3C_UART2_SIZE 0x400
 #define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
 #define S3C_UART3_SIZE 0x400
-#define S3C_UART_HAS_UBRDIVSLOT
-#define S3C_UART_HAS_UINTM
 
 #define S5P_DMC0_BASE 0xF0000000
 #define S5P_DMC1_BASE 0xF1400000
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index a2b8e56..8736f0b 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -74,10 +74,11 @@ static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
 	void __iomem *base = priv->regs;
 	unsigned val;
 
-#ifdef S3C_UART_HAS_UBRDIVSLOT
-	val = s3c_get_arch_uart_input_clock(base) / baudrate;
-	writew(udivslot_table[val & 15], base + UBRDIVSLOT);
-#endif
+	if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART)) {
+		val = s3c_get_arch_uart_input_clock(base) / baudrate;
+		writew(udivslot_table[val & 15], base + UBRDIVSLOT);
+	}
+
 	val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
 	writew(val, base + UBRDIV);
 
@@ -101,10 +102,9 @@ static int s3c_serial_init_port(struct console_device *cdev)
 	writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
 						base + UCON);
 
-#ifdef S3C_UART_HAS_UINTM
-	/* 'interrupt or polling mode' for both directions */
-	writeb(0xf, base + UINTM);
-#endif
+	if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
+		/* 'interrupt or polling mode' for both directions */
+		writeb(0xf, base + UINTM);
 
 	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
 		writeb(0x10, base + UMCON); /* enable auto flow control */
-- 
1.7.10.4


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[PATCH 10/18] Samsung/serial: unify UCON register settings

[Juergen Beisert]

This should work on S3C24XX and S3C64XX SoCs.

Tested at runtime on a Mini2440 and Mini6410.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 drivers/serial/serial_s3c.c |   10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 8736f0b..dc28dd6 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -97,9 +97,13 @@ static int s3c_serial_init_port(struct console_device *cdev)
 	/* Normal,No parity,1 stop,8 bit */
 	writeb(0x03, base + ULCON);
 
-	/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal, interrupt or polling, no pre-divider */
-	writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
+	/*
+	 * S3C2440 SoC:
+	 *  - no clock divider
+	 * all SoCs:
+	 *  - enable receive and transmit mode
+	 */
+	writew(0x0005 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
 						base + UCON);
 
 	if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
-- 
1.7.10.4


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[PATCH 11/18] ARM/Samsung: add generic lowlevel init

[Juergen Beisert]

Just a placeholder for some required low level routines
---
 arch/arm/mach-samsung/Makefile           |    1 +
 arch/arm/mach-samsung/lowlevel-s3c64xx.c |   14 ++++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 arch/arm/mach-samsung/lowlevel-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 091b600..ac34d86 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,5 +1,6 @@
 obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
+obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
diff --git a/arch/arm/mach-samsung/lowlevel-s3c64xx.c b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
new file mode 100644
index 0000000..b1ba719
--- /dev/null
+++ b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
-- 
1.7.10.4


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[PATCH 12/18] ARM/Samsung: add S3C6410 SoC iomap

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/include/mach/s3c-iomap.h     |    3 ++
 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h |   44 ++++++++++++++++++++
 2 files changed, 47 insertions(+)
 create mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h

diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index d34ace4..09a6891 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -22,6 +22,9 @@
 #ifdef CONFIG_ARCH_S3C24xx
 # include <mach/s3c24xx-iomap.h>
 #endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include <mach/s3c64xx-iomap.h>
+#endif
 #ifdef CONFIG_ARCH_S5PCxx
 # include <mach/s5pcxx-iomap.h>
 #endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
new file mode 100644
index 0000000..267cd4f
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* S3C64xx device base addresses */
+# define S3C_SROM_SFR			0x70000000
+# define S3C_DRAMC			0x7e001000
+# define S3C_WATCHDOG_BASE		0x7e004000
+# define S3C_CLOCK_POWER_BASE		0x7e00f000
+# define S3C_UART_BASE			0x7f005000
+# define S3C_TIMER_BASE			0x7f006000
+# define S3C_GPIO_BASE			0x7f008000
+
+# define S3C_UART1_BASE (S3C_UART_BASE)
+# define S3C_UART1_SIZE 0x400
+# define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
+# define S3C_UART2_SIZE 0x400
+# define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
+# define S3C_UART3_SIZE 0x400
+# define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
+# define S3C_UART4_SIZE 0x400
+
+# define S3C_SDRAM_BASE 0x50000000
+# define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
+
+# define S3C_SROM_BW (S3C_SROM_SFR)
+# define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
+
+# define S3C_CS0_BASE 0x10000000
+# define S3C_CS1_BASE 0x18000000
+# define S3C_CS2_BASE 0x20000000
+# define S3C_CS3_BASE 0x28000000
+# define S3C_CS4_BASE 0x30000000
+# define S3C_CS5_BASE 0x38000000
-- 
1.7.10.4


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[PATCH 13/18] ARM/Samsung: adapt the generic timer driver to support the S3C6410 SoC

[Juergen Beisert]

The S3C64XX SoC has a real 32 bit counter, but almost the same style of
registers. It's enough to change the parameters, to get the routines work on
this SoC.

TODO: what about the S5P SoCs?

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/s3c-timer.c |   17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-samsung/s3c-timer.c b/arch/arm/mach-samsung/s3c-timer.c
index 6665c8c..271f97d 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -37,11 +37,20 @@
 #define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
 #define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
 
-#define TIMER_WIDTH 16
-#define TIMER_SHIFT 10
-#define PRE_MUX 3
-#define PRE_MUX_ADD 1
+#ifdef CONFIG_ARCH_S3C24xx
+# define TIMER_WIDTH 16
+# define TIMER_SHIFT 10
+# define PRE_MUX 3
+# define PRE_MUX_ADD 1
 static const uint32_t max = 0x0000ffff;
+#endif
+#ifdef CONFIG_ARCH_S3C64xx
+# define TIMER_WIDTH 32
+# define TIMER_SHIFT 10
+# define PRE_MUX 4
+# define PRE_MUX_ADD 0
+static const uint32_t max = ~0;
+#endif
 
 static void s3c_init_t4_clk_source(void)
 {
-- 
1.7.10.4


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[PATCH 14/18] ARM/Samsung: add the clock tree support for the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/Makefile                     |    1 +
 arch/arm/mach-samsung/clocks-s3c64xx.c             |  186 ++++++++++++++++++++
 arch/arm/mach-samsung/include/mach/s3c-clocks.h    |    3 +
 .../arm/mach-samsung/include/mach/s3c64xx-clocks.h |   49 ++++++
 4 files changed, 239 insertions(+)
 create mode 100644 arch/arm/mach-samsung/clocks-s3c64xx.c
 create mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index ac34d86..d27496d 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -3,5 +3,6 @@ obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C64xx) += clocks-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/clocks-s3c64xx.c b/arch/arm/mach-samsung/clocks-s3c64xx.c
new file mode 100644
index 0000000..1e11cdf
--- /dev/null
+++ b/arch/arm/mach-samsung/clocks-s3c64xx.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-clocks.h>
+
+static unsigned s3c_get_apllclk(void)
+{
+	uint32_t m, p, s, reg_val;
+
+	reg_val = readl(S3C_APLLCON);
+	m = S3C_APLLCON_GET_MDIV(reg_val);
+	p = S3C_APLLCON_GET_PDIV(reg_val);
+	s = S3C_APLLCON_GET_SDIV(reg_val);
+
+	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+static unsigned s3c_get_apll_out(void)
+{
+	if (readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTAPLL)
+		return s3c_get_apllclk();
+
+	return S3C64XX_CLOCK_REFERENCE;
+}
+
+uint32_t s3c_get_mpllclk(void)
+{
+	uint32_t m, p, s, reg_val;
+
+	reg_val = readl(S3C_MPLLCON);
+	m = S3C_MPLLCON_GET_MDIV(reg_val);
+	p = S3C_MPLLCON_GET_PDIV(reg_val);
+	s = S3C_MPLLCON_GET_SDIV(reg_val);
+
+	return (S3C64XX_CLOCK_REFERENCE * m) / (p << s);
+}
+
+static unsigned s3c_get_epllclk(void)
+{
+	return 0;	 /* TODO */
+}
+
+static unsigned s3c_get_mpll_out(void)
+{
+	if (readl(S3C_CLK_SRC) & S3C_CLK_SRC_FOUTMPLL)
+		return s3c_get_mpllclk();
+
+	return S3C64XX_CLOCK_REFERENCE;
+}
+
+uint32_t s3c_get_fclk(void)
+{
+	unsigned clk;
+
+	clk = s3c_get_apll_out();
+	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
+		clk /= 2;
+
+	return clk / (S3C_CLK_DIV0_GET_ADIV(readl(S3C_CLK_DIV0)) + 1);
+}
+
+static unsigned s3c_get_hclk_in(void)
+{
+	unsigned clk;
+
+	if (readl(S3C_OTHERS) & S3C_OTHERS_CLK_SELECT)
+		clk = s3c_get_apll_out();
+	else
+		clk = s3c_get_mpll_out();
+
+	if (readl(S3C_MISC_CON) & S3C_MISC_CON_SYN667)
+		clk /= 5;
+
+	return clk;
+}
+
+static unsigned s3c_get_hclkx2(void)
+{
+	return s3c_get_hclk_in() /
+			(S3C_CLK_DIV0_GET_HCLK2(readl(S3C_CLK_DIV0)) + 1);
+}
+
+uint32_t s3c_get_hclk(void)
+{
+	return s3c_get_hclkx2() /
+			(S3C_CLK_DIV0_GET_HCLK(readl(S3C_CLK_DIV0)) + 1);
+}
+
+uint32_t s3c_get_pclk(void)
+{
+	return s3c_get_hclkx2() /
+			(S3C_CLK_DIV0_GET_PCLK(readl(S3C_CLK_DIV0)) + 1);
+}
+
+static void s3c_init_mpll_dout(void)
+{
+	unsigned reg;
+
+	/* keep it at the same frequency as HCLKx2 */
+	reg = readl(S3C_CLK_DIV0) | S3C_CLK_DIV0_SET_MPLL_DIV(1); /* e.g. / 2 */
+	writel(reg, S3C_CLK_DIV0);
+}
+
+/* configure and enable UCLK1 */
+static int s3c_init_uart_clock(void)
+{
+	unsigned reg;
+
+	s3c_init_mpll_dout();	/* to have a reliable clock source */
+
+	/* source the UART clock from the MPLL, currently *not* from EPLL */
+	reg = readl(S3C_CLK_SRC) | S3C_CLK_SRC_UARTMPLL;
+	writel(reg, S3C_CLK_SRC);
+
+	/* keep UART clock at the same frequency than the PCLK */
+	reg = readl(S3C_CLK_DIV2) & ~S3C_CLK_DIV2_UART_MASK;
+	reg |= S3C_CLK_DIV2_SET_UART(0x3);	/* / 4 */
+	writel(reg, S3C_CLK_DIV2);
+
+	/* ensure this very special clock is running */
+	reg = readl(S3C_SCLK_GATE) | S3C_SCLK_GATE_UART;
+	writel(reg, S3C_SCLK_GATE);
+
+	return 0;
+}
+core_initcall(s3c_init_uart_clock);
+
+unsigned s3c_get_uart_clk(unsigned source)
+{
+	u32 reg;
+	unsigned clk, pdiv, uartpdiv;
+
+	switch (source) {
+	default: /* PCLK */
+		clk = s3c_get_pclk();
+		pdiv = uartpdiv = 1;
+		break;
+	case 1: /* UCLK0 */
+		clk = 0;
+		pdiv = uartpdiv = 1;	/* TODO */
+		break;
+	case 3: /* UCLK1 */
+		reg = readl(S3C_CLK_SRC);
+		if (reg & S3C_CLK_SRC_UARTMPLL)
+			clk = s3c_get_mpllclk();
+		else
+			clk = s3c_get_epllclk();
+		pdiv = S3C_CLK_DIV0_GET_MPLL_DIV(readl(S3C_CLK_DIV0)) + 1;
+		uartpdiv = S3C_CLK_DIV2_GET_UART(readl(S3C_CLK_DIV2)) + 1;
+		break;
+	}
+
+	return clk / pdiv / uartpdiv;
+}
+
+int s3c64xx_dump_clocks(void)
+{
+	printf("refclk:  %7d kHz\n", S3C64XX_CLOCK_REFERENCE / 1000);
+	printf("apll:    %7d kHz\n", s3c_get_apllclk() / 1000);
+	printf("mpll:    %7d kHz\n", s3c_get_mpllclk() / 1000);
+	printf("CPU:     %7d kHz\n", s3c_get_fclk() / 1000);
+	printf("hclkx2:  %7d kHz\n", s3c_get_hclkx2() / 1000);
+	printf("hclk:    %7d kHz\n", s3c_get_hclk() / 1000);
+	printf("pclk:    %7d kHz\n", s3c_get_pclk() / 1000);
+	return 0;
+}
+
+late_initcall(s3c64xx_dump_clocks);
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
index f577306..6920ca9 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-clocks.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
@@ -25,6 +25,9 @@
 #ifdef CONFIG_ARCH_S3C24xx
 # include <mach/s3c24xx-clocks.h>
 #endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include <mach/s3c64xx-clocks.h>
+#endif
 #ifdef CONFIG_ARCH_S5PCxx
 # include <mach/s5pcxx-clocks.h>
 #endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
new file mode 100644
index 0000000..a972cf4
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+# define S3C_APLLCON (S3C_CLOCK_POWER_BASE + 0x0c)
+#  define S3C_APLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
+#  define S3C_APLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
+#  define S3C_APLLCON_GET_SDIV(x) ((x) & 0x7)
+# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x10)
+#  define S3C_MPLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
+#  define S3C_MPLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
+#  define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x7)
+# define S3C_EPLLCON0 (S3C_CLOCK_POWER_BASE + 0x14)
+# define S3C_EPLLCON1 (S3C_CLOCK_POWER_BASE + 0x18)
+# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
+# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
+# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
+# define S3C_CLK_SRC (S3C_CLOCK_POWER_BASE + 0x01c)
+#  define S3C_CLK_SRC_UARTMPLL (1 << 13)
+#  define S3C_CLK_SRC_FOUTEPLL (1 << 2)
+#  define S3C_CLK_SRC_FOUTMPLL (1 << 1)
+#  define S3C_CLK_SRC_FOUTAPLL (1 << 0)
+# define S3C_CLK_DIV0 (S3C_CLOCK_POWER_BASE + 0x020)
+#  define S3C_CLK_DIV0_GET_ADIV(x) ((x) & 0xf)
+#  define S3C_CLK_DIV0_GET_HCLK2(x) (((x) >> 9) & 0x7)
+#  define S3C_CLK_DIV0_GET_HCLK(x) (((x) >> 8) & 0x1)
+#  define S3C_CLK_DIV0_GET_PCLK(x) (((x) >> 12) & 0xf)
+#  define S3C_CLK_DIV0_SET_MPLL_DIV(x) (((x) & 0x1) << 4)
+#  define S3C_CLK_DIV0_GET_MPLL_DIV(x) (((x) >> 4) & 0x1)
+# define S3C_CLK_DIV2 (S3C_CLOCK_POWER_BASE + 0x028)
+#  define S3C_CLK_DIV2_UART_MASK (0xf << 16)
+#  define S3C_CLK_DIV2_SET_UART(x) ((x) << 16)
+#  define S3C_CLK_DIV2_GET_UART(x) (((x) >> 16) & 0xf)
+# define S3C_SCLK_GATE (S3C_CLOCK_POWER_BASE + 0x038)
+#  define S3C_SCLK_GATE_UART (1 << 5)
+# define S3C_MISC_CON (S3C_CLOCK_POWER_BASE + 0x838)
+#  define S3C_MISC_CON_SYN667 (1 << 19)
+# define S3C_OTHERS (S3C_CLOCK_POWER_BASE + 0x900)
+#  define S3C_OTHERS_CLK_SELECT (1 << 6)
-- 
1.7.10.4


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[PATCH 15/18] ARM/Samsung: add GPIO handling support for the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/Makefile                     |    2 +-
 arch/arm/mach-samsung/gpio-s3c64xx.c               |  301 ++++++++++++
 arch/arm/mach-samsung/include/mach/gpio.h          |    3 +
 arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h |  497 ++++++++++++++++++++
 4 files changed, 802 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/gpio-s3c64xx.c
 create mode 100644 arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index d27496d..5187170 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -3,6 +3,6 @@ obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/gpio-s3c64xx.c b/arch/arm/mach-samsung/gpio-s3c64xx.c
new file mode 100644
index 0000000..bb3ac52
--- /dev/null
+++ b/arch/arm/mach-samsung/gpio-s3c64xx.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This codes bases partially on code from the Linux kernel:
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *	http://armlinux.simtec.co.uk/
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <io.h>
+#include <gpio.h>
+#include <mach/s3c-iomap.h>
+
+#define S3C_GPACON (S3C_GPIO_BASE)
+#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
+#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
+
+static const unsigned short group_offset[] = {
+	0x000,	/* GPA */ /* 8 pins, 4 bit each */
+	0x020,	/* GPB */ /* 7 pins, 4 bit each */
+	0x040,	/* GPC */ /* 8 pins, 4 bit each */
+	0x060,	/* GPD */ /* 5 pins, 4 bit each */
+	0x080,	/* GPE */ /* 5 pins, 4 bit each */
+	0x0a0,	/* GPF */ /* 16 pins, 2 bit each */
+	0x0c0,	/* GPG */ /* 7 pins, 4 bit each */
+	0x0e0,	/* GPH */ /* two registers, 8 + 2 pins, 4 bit each */
+	0x100,	/* GPI */ /* 16 pins, 2 bit each */
+	0x120,	/* GPJ */ /* 12 pins, 2 bit each */
+	0x800,	/* GPK */ /* two registers, 8 + 8 pins, 4 bit each */
+	0x810,	/* GPL */ /* two registers, 8 + 8 pins, 4 bit each */
+	0x820,	/* GPM */ /* 6 pins, 4 bit each */
+	0x830,	/* GPN */ /* 16 pins, 2 bit each */
+	0x140,	/* GPO */ /* 16 pins, 2 bit each */
+	0x160,	/* GPP */ /* 15 pins, 2 bit each */
+	0x180,	/* GPQ */ /* 9 pins, 2 bit each */
+};
+
+void gpio_set_value(unsigned gpio, int value)
+{
+	unsigned group = GET_GROUP(gpio);
+	unsigned bit = GET_BIT(gpio);
+	unsigned offset;
+	uint32_t reg;
+
+	offset = group_offset[group];
+
+	switch (group) {
+	case 7:		/* GPH */
+	case 10:	/* GPK */
+	case 11:	/* GPL */
+		offset += 4;
+		break;
+	}
+
+	reg = readl(S3C_GPADAT + offset);
+	reg &= ~(1 << bit);
+	reg |= (!!value) << bit;
+	writel(reg, S3C_GPADAT + offset);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	unsigned group = GET_GROUP(gpio);
+	unsigned bit = GET_BIT(gpio);
+	unsigned offset;
+	uint32_t reg;
+
+	offset = group_offset[group];
+
+	switch (group) {
+	case 7:		/* GPH */
+	case 10:	/* GPK */
+	case 11:	/* GPL */
+		offset += 4;
+		break;
+	}
+
+	/* value */
+	reg = readl(S3C_GPADAT + offset);
+
+	return !!(reg & (1 << bit));
+}
+
+static void gpio_direction_input_4b(unsigned offset, unsigned bit)
+{
+	uint32_t reg;
+
+	if (bit > 31) {
+		offset += 4;
+		bit -= 32;
+	}
+
+	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+	writel(reg, S3C_GPACON + offset); /* b0000 means 'GPIO input' */
+}
+
+static void gpio_direction_input_2b(unsigned offset, unsigned bit)
+{
+	uint32_t reg;
+
+	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
+	writel(reg, S3C_GPACON + offset); /* b00 means 'GPIO input' */
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	unsigned group = GET_GROUP(gpio);
+	unsigned bit = GET_BIT(gpio);
+	unsigned offset;
+
+	offset = group_offset[group];
+
+	switch (group) {
+	case 5:		/* GPF */
+	case 8:		/* GPI */
+	case 9:		/* GPJ */
+	case 13:	/* GPN */
+	case 14:	/* GPO */
+	case 15:	/* GPP */
+	case 16:	/* GPQ */
+		gpio_direction_input_2b(offset, bit << 1);
+		break;
+	default:
+		gpio_direction_input_4b(offset, bit << 2);
+	}
+
+	return 0;
+}
+
+static void gpio_direction_output_4b(unsigned offset, unsigned bit)
+{
+	uint32_t reg;
+
+	if (bit > 31) {
+		offset += 4;
+		bit -= 32;
+	}
+
+	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+	reg |= 0x1 << bit;
+	writel(reg, S3C_GPACON + offset); /* b0001 means 'GPIO output' */
+}
+
+static void gpio_direction_output_2b(unsigned offset, unsigned bit)
+{
+	uint32_t reg;
+
+	/* direction */
+	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
+	reg |= 0x1 << bit;
+	writel(reg, S3C_GPACON + offset);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	unsigned group = GET_GROUP(gpio);
+	unsigned bit = GET_BIT(gpio);
+	unsigned offset;
+
+	gpio_set_value(gpio, value);
+
+	offset = group_offset[group];
+	switch (group) {
+	case 5:		/* GPF */
+	case 8:		/* GPI */
+	case 9:		/* GPJ */
+	case 13:	/* GPN */
+	case 14:	/* GPO */
+	case 15:	/* GPP */
+	case 16:	/* GPQ */
+		gpio_direction_output_2b(offset, bit << 1);
+		break;
+	default:
+		gpio_direction_output_4b(offset, bit << 2);
+	}
+
+	return 0;
+}
+
+/* one register, 2 bits per function -> GPF, GPI, GPJ, GPN, GPO, GPP, GPQ */
+static void s3c_d2pins(unsigned offset, unsigned pin_mode)
+{
+	unsigned bit = GET_BIT(pin_mode);
+	unsigned func = GET_FUNC(pin_mode);
+	unsigned reg;
+
+	if (PUD_PRESENT(pin_mode)) {
+		reg = readl(S3C_GPAPUD + offset);
+		reg &= ~(PUD_MASK << bit);
+		reg |= GET_PUD(pin_mode) << bit;
+		writel(reg, S3C_GPAPUD + offset);
+	}
+
+	/* in the case of pin's function is GPIO it also sets up the direction */
+	reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
+	writel(reg | (func << bit), S3C_GPACON + offset);
+
+	if (func == 1) { /* output? if yes, also set the initial value */
+		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 1));
+		reg |= GET_GPIOVAL(pin_mode) << (bit >> 1);
+		writel(reg, S3C_GPADAT + offset);
+	}
+}
+
+/* one register, 4 bits per function -> GPA, GPB, GPC, GPD, GPE, GPG, GPM */
+static void s3c_d4pins(unsigned offset, unsigned pin_mode)
+{
+	unsigned bit = GET_BIT(pin_mode);
+	unsigned func = GET_FUNC(pin_mode);
+	unsigned reg;
+
+	if (PUD_PRESENT(pin_mode)) {
+		reg = readl(S3C_GPAPUD + offset);
+		reg &= ~(PUD_MASK << (bit >> 1));
+		reg |= GET_PUD(pin_mode) << (bit >> 1);
+		writel(reg, S3C_GPAPUD + offset);
+	}
+
+	/* in the case of pin's function is GPIO it also sets up the direction */
+	reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+	writel(reg | (func << bit), S3C_GPACON + offset);
+
+	if (func == 1) { /* output? if yes, also set the initial value */
+		reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
+		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
+		writel(reg, S3C_GPADAT + offset);
+	}
+}
+
+/* two registers, 4 bits per pin -> GPH, GPK, GPL */
+static void s3c_d42pins(unsigned offset, unsigned pin_mode)
+{
+	unsigned bit = GET_BIT(pin_mode);
+	unsigned func = GET_FUNC(pin_mode);
+	uint32_t reg;
+	unsigned reg_offs = 0;
+
+	if (PUD_PRESENT(pin_mode)) {
+		reg = readl(S3C_GPAPUD + 4 + offset);
+		reg &= ~(PUD_MASK << (bit >> 1));
+		reg |= GET_PUD(pin_mode) << (bit >> 1);
+		writel(reg, S3C_GPACON + 4 + offset);
+	}
+
+	if (bit > 31) {
+		reg_offs = 4;
+		bit -= 32;
+	}
+
+	/* in the case of pin's function is GPIO it also sets up the direction */
+	reg = readl(S3C_GPACON + offset + reg_offs) & ~(0xf << bit);
+	writel(reg | (func << bit), S3C_GPACON + offset + reg_offs);
+
+	if (func == 1) { /* output? if yes, also set the initial value */
+		reg = readl(S3C_GPADAT + 4 + offset) & ~(1 << (bit >> 2));
+		reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
+		writel(reg, S3C_GPADAT + 4 + offset);
+	}
+}
+
+/* 'gpio_mode' must be one of the 'GP?_*' macros */
+void s3c_gpio_mode(unsigned gpio_mode)
+{
+	unsigned group, offset;
+
+	group = GET_GROUP(gpio_mode);
+	offset = group_offset[group];
+
+	switch (group) {
+	case 5:		/* GPF */
+	case 8:		/* GPI */
+	case 9:		/* GPJ */
+	case 13:	/* GPN */
+	case 14:	/* GPO */
+	case 15:	/* GPP */
+	case 16:	/* GPQ */
+		s3c_d2pins(offset, gpio_mode);
+		break;
+	case 7:		/* GPH */
+	case 10:	/* GPK */
+	case 11:	/* GPL */
+		s3c_d42pins(offset, gpio_mode);
+		break;
+	default:
+		s3c_d4pins(offset, gpio_mode);
+	}
+}
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
index 4d7d217..2b45695 100644
--- a/arch/arm/mach-samsung/include/mach/gpio.h
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -16,6 +16,9 @@
 #ifdef CONFIG_ARCH_S3C24xx
 # include <mach/iomux-s3c24x0.h>
 #endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include <mach/iomux-s3c64xx.h>
+#endif
 #ifdef CONFIG_ARCH_S5PCxx
 # include <mach/iomux-s5pcxx.h>
 #endif
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h b/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
new file mode 100644
index 0000000..7932740
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h
@@ -0,0 +1,497 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IOMUX_S3C64XX_H
+# define __MACH_IOMUX_S3C64XX_H
+
+/* 3322222222221111111111
+ * 10987654321098765432109876543210
+ *                           ^^^^^^_ Bit offset
+ *                      ^^^^^_______ Group Number
+ *                  ^^^^____________ Function
+ *                 ^________________ initial GPIO out value
+ *                ^_________________ Pull up/down feature present
+ *              ^^__________________ initial pull up/down setting
+ */
+
+#define PIN(group,bit) ((group << 6) + bit)
+#define FUNC(x) (((x) & 0xf) << 11)
+#define GET_FUNC(x) (((x) >> 11) & 0xf)
+#define GET_GROUP(x) (((x) >> 6) & 0x1f)
+#define GET_BIT(x) ((x) & 0x3f)
+#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
+#define GPIO_OUT (1 << 11)
+#define GPIO_IN (0 << 11)
+#define GPIO_VAL(x) ((!!(x)) << 15)
+#define PUD_MASK 0x3
+#define PUD (1 << 16)
+#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
+#define DISABLE_PUD (0 << 17)
+#define ENABLE_PU (2 << 17)
+#define ENABLE_PD (1 << 17)
+#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
+
+/*
+ * To have a chance for simple GPIO manipulation routines
+ * define the GPIO numbers with a real simple scheme.
+ *
+ * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
+ * routines and *not* for the multiplexer routines!
+ */
+#define GPIO_2_NO(x,y) (PIN(x,y))
+
+/*
+ * Group A: GPIO 0...7
+ * Used GPIO: 0...7
+ * These pins can also act as GPIO outputs
+ */
+#define GPA0		(PIN(0,0) | PUD)
+#define GPA0_GPIO	(GPA0 | FUNC(0))
+#define GPA0_RXD0	(GPA0 | FUNC(2))
+#define GPA1		(PIN(0,4) | PUD)
+#define GPA1_GPIO	(GPA1 | FUNC(0))
+#define GPA1_TXD0	(GPA1 | FUNC(2))
+#define GPA2		(PIN(0,8) | PUD)
+#define GPA2_GPIO	(GPA2 | FUNC(0))
+#define GPA2_NCTS0	(GPA2 | FUNC(2))
+#define GPA3		(PIN(0,12) | PUD)
+#define GPA3_GPIO	(GPA3 | FUNC(0))
+#define GPA3_NRTS0	(GPA3 | FUNC(2))
+#define GPA4		(PIN(0,16) | PUD)
+#define GPA4_GPIO	(GPA4 | FUNC(0))
+#define GPA4_RXD1	(GPA4 | FUNC(2))
+#define GPA5		(PIN(0,20) | PUD)
+#define GPA5_GPIO	(GPA5 | FUNC(0))
+#define GPA5_TXD1	(GPA5 | FUNC(2))
+#define GPA6		(PIN(0,24) | PUD)
+#define GPA6_GPIO	(GPA6 | FUNC(0))
+#define GPA6_NCTS1	(GPA6 | FUNC(2))
+#define GPA7		(PIN(0,28) | PUD)
+#define GPA7_GPIO	(GPA7 | FUNC(0))
+#define GPA7_NRTS1	(GPA7 | FUNC(2))
+
+/*
+ * Group B: GPIO 0...7
+ * Used GPIO: 8...15
+ * These pins can also act as GPIO outputs
+ */
+#define GPB0		(PIN(1,0) | PUD)
+#define GPB0_GPIO	(GPB0 | FUNC(0))
+#define GPB0_RXD2	(GPB0 | FUNC(2))
+#define GPB0_DMAREQ	(GPB0 | FUNC(3))
+#define GPB0_IRDA_RXD	(GPB0 | FUNC(4))
+#define GPB0_ADDR_CF0	(GPB0 | FUNC(5))
+#define GPB1		(PIN(1,4) | PUD)
+#define GPB1_GPIO	(GPB1 | FUNC(0))
+#define GPB1_TXD2	(GPB1 | FUNC(2))
+#define GPB1_DMAREQ	(GPB1 | FUNC(3))
+#define GPB1_IRDA_TXD	(GPB1 | FUNC(4))
+#define GPB1_ADDR_CF1	(GPB1 | FUNC(5))
+#define GPB2		(PIN(1,8) | PUD)
+#define GPB2_GPIO	(GPB2 | FUNC(0))
+#define GPB2_RXD3	(GPB2 | FUNC(2))
+#define GPB2_IRDA_RXD	(GPB2 | FUNC(3))
+#define GPB2_DMAREQ	(GPB2 | FUNC(4))
+#define GPB2_ADDR_CF2	(GPB2 | FUNC(5))
+#define GPB2_IIC1_SCL	(GPB2 | FUNC(6))
+#define GPB3		(PIN(1,12) | PUD)
+#define GPB3_GPIO	(GPB3 | FUNC(0))
+#define GPB3_TXD3	(GPB3 | FUNC(2))
+#define GPB3_IRDA_TXD	(GPB3 | FUNC(3))
+#define GPB3_DMAREQ	(GPB3 | FUNC(4))
+#define GPB3_IIC1_SDA	(GPB3 | FUNC(6))
+#define GPB4		(PIN(1,16) | PUD)
+#define GPB4_GPIO	(GPB4 | FUNC(0))
+#define GPB4_SDBW	(GPB4 | FUNC(2))
+#define GPB4_CAM_FLD	(GPB4 | FUNC(3))
+#define GPB4_CF_DIR	(GPB4 | FUNC(4))
+#define GPB5		(PIN(1,20) | PUD)
+#define GPB5_GPIO	(GPB5 | FUNC(0))
+#define GPB5_IIC0_SCL	(GPB5 | FUNC(2))
+#define GPB6		(PIN(1,24) | PUD)
+#define GPB6_GPIO	(GPB6 | FUNC(0))
+#define GPB6_IIC0_SDA	(GPB6 | FUNC(2))
+
+#define GPC0		(PIN(2,0) | PUD)
+#define GPC0_SPI0_MISO	(GPC0 | FUNC(2))
+#define GPC1		(PIN(2,4) | PUD)
+#define GPC1_SPI0_CLK	(GPC1 | FUNC(2))
+#define GPC2		(PIN(2,8) | PUD)
+#define GPC2_SPI0_MOSI	(GPC2 | FUNC(2))
+#define GPC3		(PIN(2,12) | PUD)
+#define GPC3_SPI0_NCS	(GPC3 | FUNC(2))
+#define GPC4		(PIN(2,16) | PUD)
+#define GPC4_SPI1_MISO	(GPC4 | FUNC(2))
+#define GPC5		(PIN(2,20) | PUD)
+#define GPC5_SPI1_CLK	(GPC5 | FUNC(2))
+#define GPC6		(PIN(2,24) | PUD)
+#define GPC6_SPI1_MOSI	(GPC6 | FUNC(2))
+#define GPC7		(PIN(2,28) | PUD)
+#define GPC7_SPI1_NCS	(GPC7 | FUNC(2))
+
+#define GPD0		(PIN(3,0) | PUD)
+#define GPD0_AC97_BITCLK (GPD0 | FUNC(4))
+#define GPD1		(PIN(3,4) | PUD)
+#define GPD1_AC97_NRST	(GPD1 | FUNC(4))
+#define GPD2		(PIN(3,8) | PUD)
+#define GPD2_AC97_SYNC	(GPD2 | FUNC(4))
+#define GPD3		(PIN(3,12) | PUD)
+#define GPD3_AC97_SDI	(GPD3 | FUNC(4))
+#define GPD4		(PIN(3,16) | PUD)
+#define GPD4_AC97_SDO	(GPD4 | FUNC(4))
+
+#define GPE0		(PIN(4,0) | PUD)
+#define GPE0_GPIO	(GPE0 | FUNC(0))
+#define GPE1		(PIN(4,4) | PUD)
+#define GPE1_GPIO	(GPE1 | FUNC(0))
+#define GPE2		(PIN(4,8) | PUD)
+#define GPE2_GPIO	(GPE2 | FUNC(0))
+#define GPE3		(PIN(4,12) | PUD)
+#define GPE3_GPIO	(GPE3 | FUNC(0))
+#define GPE4		(PIN(4,16) | PUD)
+#define GPE4_GPIO	(GPE4 | FUNC(0))
+
+#define GPF0		(PIN(5,0) | PUD)
+#define GPF0_GPIO	(GPF0 | FUNC(0))
+#define GPF1		(PIN(5,2) | PUD)
+#define GPF1_GPIO	(GPF1 | FUNC(0))
+#define GPF2		(PIN(5,4) | PUD)
+#define GPF2_GPIO	(GPF2 | FUNC(0))
+#define GPF3		(PIN(5,6) | PUD)
+#define GPF3_GPIO	(GPF3 | FUNC(0))
+#define GPF4		(PIN(5,8) | PUD)
+#define GPF4_GPIO	(GPF4 | FUNC(0))
+#define GPF5		(PIN(5,10) | PUD)
+#define GPF5_GPIO	(GPF5 | FUNC(0))
+#define GPF6		(PIN(5,12) | PUD)
+#define GPF6_GPIO	(GPF6 | FUNC(0))
+#define GPF7		(PIN(5,14) | PUD)
+#define GPF7_GPIO	(GPF7 | FUNC(0))
+#define GPF8		(PIN(5,16) | PUD)
+#define GPF8_GPIO	(GPF8 | FUNC(0))
+#define GPF9		(PIN(5,18) | PUD)
+#define GPF9_GPIO	(GPF9 | FUNC(0))
+#define GPF10		(PIN(5,20) | PUD)
+#define GPF10_GPIO	(GPF10 | FUNC(0))
+#define GPF11		(PIN(5,22) | PUD)
+#define GPF11_GPIO	(GPF11 | FUNC(0))
+#define GPF12		(PIN(5,24) | PUD)
+#define GPF12_GPIO	(GPF12 | FUNC(0))
+#define GPF13		(PIN(5,26) | PUD)
+#define GPF13_GPIO	(GPF13 | FUNC(0))
+#define GPF14		(PIN(5,28) | PUD)
+#define GPF14_GPIO	(GPF14 | FUNC(0))
+#define GPF14_PWM0	(GPF14 | FUNC(2))
+#define GPF15		(PIN(5,30) | PUD)
+#define GPF15_GPIO	(GPF15 | FUNC(0))
+#define GPF15_PWM1	(GPF15 | FUNC(2))
+
+#define GPG0		(PIN(6,0) | PUD)
+#define GPG0_MMC0_CLK	(GPG0 | FUNC(2))
+#define GPG1		(PIN(6,4) | PUD)
+#define GPG1_MMC0_CMD	(GPG1 | FUNC(2))
+#define GPG2		(PIN(6,8) | PUD)
+#define GPG2_MMC0_DAT0	(GPG2 | FUNC(2))
+#define GPG3		(PIN(6,12) | PUD)
+#define GPG3_MMC0_DAT1	(GPG3 | FUNC(2))
+#define GPG4		(PIN(6,16) | PUD)
+#define GPG4_MMC0_DAT2	(GPG4 | FUNC(2))
+#define GPG5		(PIN(6,20) | PUD)
+#define GPG5_MMC0_DAT3	(GPG5 | FUNC(2))
+#define GPG6		(PIN(6,24) | PUD)
+#define GPG6_MMC0_NCD	(GPG6 | FUNC(2))
+
+#define GPH0		(PIN(7,0) | PUD)
+#define GPH0_GPIO	(GPH0 | FUNC(0))
+#define GPH1		(PIN(7,4) | PUD)
+#define GPH1_GPIO	(GPH1 | FUNC(0))
+#define GPH2		(PIN(7,8) | PUD)
+#define GPH2_GPIO	(GPH2 | FUNC(0))
+#define GPH3		(PIN(7,12) | PUD)
+#define GPH3_GPIO	(GPH3 | FUNC(0))
+#define GPH4		(PIN(7,16) | PUD)
+#define GPH4_GPIO	(GPH4 | FUNC(0))
+#define GPH5		(PIN(7,20) | PUD)
+#define GPH5_GPIO	(GPH5 | FUNC(0))
+#define GPH6		(PIN(7,24) | PUD)
+#define GPH6_GPIO	(GPH6 | FUNC(0))
+#define GPH7		(PIN(7,28) | PUD)
+#define GPH7_GPIO	(GPH7 | FUNC(0))
+#define GPH8		(PIN(7,32) | PUD)
+#define GPH8_GPIO	(GPH8 | FUNC(0))
+#define GPH9		(PIN(7,36) | PUD)
+#define GPH9_GPIO	(GPH9 | FUNC(0))
+
+#define GPI0		(PIN(8,0) | PUD)
+#define GPI0_GPIO	(GPI0 | FUNC(0))
+#define GPI1		(PIN(8,2) | PUD)
+#define GPI1_GPIO	(GPI1 | FUNC(0))
+#define GPI2		(PIN(8,4) | PUD)
+#define GPI2_GPIO	(GPI2 | FUNC(0))
+#define GPI3		(PIN(8,6) | PUD)
+#define GPI3_GPIO	(GPI3 | FUNC(0))
+#define GPI4		(PIN(8,8) | PUD)
+#define GPI4_GPIO	(GPI4 | FUNC(0))
+#define GPI5		(PIN(8,10) | PUD)
+#define GPI5_GPIO	(GPI5 | FUNC(0))
+#define GPI6		(PIN(8,12) | PUD)
+#define GPI6_GPIO	(GPI6 | FUNC(0))
+#define GPI7		(PIN(8,14) | PUD)
+#define GPI7_GPIO	(GPI7 | FUNC(0))
+#define GPI8		(PIN(8,16) | PUD)
+#define GPI8_GPIO	(GPI8 | FUNC(0))
+#define GPI9		(PIN(8,18) | PUD)
+#define GPI9_GPIO	(GPI9 | FUNC(0))
+#define GPI10		(PIN(8,20) | PUD)
+#define GPI10_GPIO	(GPI10 | FUNC(0))
+#define GPI11		(PIN(8,22) | PUD)
+#define GPI11_GPIO	(GPI11 | FUNC(0))
+#define GPI12		(PIN(8,24) | PUD)
+#define GPI12_GPIO	(GPI12 | FUNC(0))
+#define GPI13		(PIN(8,26) | PUD)
+#define GPI13_GPIO	(GPI13 | FUNC(0))
+#define GPI14		(PIN(8,28) | PUD)
+#define GPI14_GPIO	(GPI14 | FUNC(0))
+#define GPI15		(PIN(8,30) | PUD)
+#define GPI15_GPIO	(GPI15 | FUNC(0))
+
+#define GPJ0		(PIN(9,0) | PUD)
+#define GPJ0_GPIO	(GPJ0 | FUNC(0))
+#define GPJ1		(PIN(9,2) | PUD)
+#define GPJ1_GPIO	(GPJ1 | FUNC(0))
+#define GPJ2		(PIN(9,4) | PUD)
+#define GPJ2_GPIO	(GPJ2 | FUNC(0))
+#define GPJ3		(PIN(9,6) | PUD)
+#define GPJ3_GPIO	(GPJ3 | FUNC(0))
+#define GPJ4		(PIN(9,8) | PUD)
+#define GPJ4_GPIO	(GPJ4 | FUNC(0))
+#define GPJ5		(PIN(9,10) | PUD)
+#define GPJ5_GPIO	(GPJ5 | FUNC(0))
+#define GPJ6		(PIN(9,12) | PUD)
+#define GPJ6_GPIO	(GPJ6 | FUNC(0))
+#define GPJ7		(PIN(9,14) | PUD)
+#define GPJ7_GPIO	(GPJ7 | FUNC(0))
+#define GPJ8		(PIN(9,16) | PUD)
+#define GPJ8_GPIO	(GPJ8 | FUNC(0))
+#define GPJ9		(PIN(9,18) | PUD)
+#define GPJ9_GPIO	(GPJ9 | FUNC(0))
+#define GPJ10		(PIN(9,20) | PUD)
+#define GPJ10_GPIO	(GPJ10 | FUNC(0))
+#define GPJ11		(PIN(9,22) | PUD)
+#define GPJ11_GPIO	(GPJ11 | FUNC(0))
+
+#define GPK0		(PIN(10,0) | PUD)
+#define GPK0_GPIO	(GPK0 | FUNC(0))
+#define GPK1		(PIN(10,4) | PUD)
+#define GPK1_GPIO	(GPK1 | FUNC(0))
+#define GPK2		(PIN(10,8) | PUD)
+#define GPK2_GPIO	(GPK2 | FUNC(0))
+#define GPK3		(PIN(10,12) | PUD)
+#define GPK3_GPIO	(GPK3 | FUNC(0))
+#define GPK4		(PIN(10,16) | PUD)
+#define GPK4_GPIO	(GPK4 | FUNC(0))
+#define GPK5		(PIN(10,20) | PUD)
+#define GPK5_GPIO	(GPK5 | FUNC(0))
+#define GPK6		(PIN(10,24) | PUD)
+#define GPK6_GPIO	(GPK6 | FUNC(0))
+#define GPK7		(PIN(10,28) | PUD)
+#define GPK7_GPIO	(GPK7 | FUNC(0))
+#define GPK8		(PIN(10,32) | PUD)
+#define GPK8_GPIO	(GPK8 | FUNC(0))
+#define GPK9		(PIN(10,36) | PUD)
+#define GPK9_GPIO	(GPK9 | FUNC(0))
+#define GPK10		(PIN(10,40) | PUD)
+#define GPK10_GPIO	(GPK10 | FUNC(0))
+#define GPK11		(PIN(10,44) | PUD)
+#define GPK11_GPIO	(GPK11 | FUNC(0))
+#define GPK12		(PIN(10,48) | PUD)
+#define GPK12_GPIO	(GPK12 | FUNC(0))
+#define GPK13		(PIN(10,52) | PUD)
+#define GPK13_GPIO	(GPK13 | FUNC(0))
+#define GPK14		(PIN(10,56) | PUD)
+#define GPK14_GPIO	(GPK14 | FUNC(0))
+#define GPK15		(PIN(10,60) | PUD)
+#define GPK15_GPIO	(GPK15 | FUNC(0))
+
+#define GPL0		(PIN(11,0) | PUD)
+#define GPL0_GPIO	(GPL0 | FUNC(0))
+#define GPL1		(PIN(11,4) | PUD)
+#define GPL1_GPIO	(GPL1 | FUNC(0))
+#define GPL2		(PIN(11,8) | PUD)
+#define GPL2_GPIO	(GPL2 | FUNC(0))
+#define GPL3		(PIN(11,12) | PUD)
+#define GPL3_GPIO	(GPL3 | FUNC(0))
+#define GPL4		(PIN(11,16) | PUD)
+#define GPL4_GPIO	(GPL4 | FUNC(0))
+#define GPL5		(PIN(11,20) | PUD)
+#define GPL5_GPIO	(GPL5 | FUNC(0))
+#define GPL6		(PIN(11,24) | PUD)
+#define GPL6_GPIO	(GPL6 | FUNC(0))
+#define GPL7		(PIN(11,28) | PUD)
+#define GPL7_GPIO	(GPL7 | FUNC(0))
+#define GPL8		(PIN(11,32) | PUD)
+#define GPL8_GPIO	(GPL8 | FUNC(0))
+#define GPL9		(PIN(11,36) | PUD)
+#define GPL9_GPIO	(GPL9 | FUNC(0))
+#define GPL10		(PIN(11,40) | PUD)
+#define GPL10_GPIO	(GPL10 | FUNC(0))
+#define GPL11		(PIN(11,44) | PUD)
+#define GPL11_GPIO	(GPL11 | FUNC(0))
+#define GPL12		(PIN(11,48) | PUD)
+#define GPL12_GPIO	(GPL12 | FUNC(0))
+#define GPL13		(PIN(11,52) | PUD)
+#define GPL13_GPIO	(GPL13 | FUNC(0))
+#define GPL14		(PIN(11,65) | PUD)
+#define GPL14_GPIO	(GPL14 | FUNC(0))
+
+#define GPM0		(PIN(12,0) | PUD)
+#define GPM0_GPIO	(GPM0 | FUNC(0))
+#define GPM1		(PIN(12,4) | PUD)
+#define GPM1_GPIO	(GPM1 | FUNC(0))
+#define GPM2		(PIN(12,8) | PUD)
+#define GPM2_GPIO	(GPM2 | FUNC(0))
+#define GPM3		(PIN(12,12) | PUD)
+#define GPM3_GPIO	(GPM3 | FUNC(0))
+#define GPM4		(PIN(12,16) | PUD)
+#define GPM4_GPIO	(GPM4 | FUNC(0))
+#define GPM5		(PIN(12,20) | PUD)
+#define GPM5_GPIO	(GPM5 | FUNC(0))
+
+#define GPN0		(PIN(13,0) | PUD)
+#define GPN0_GPIO	(GPN0 | FUNC(0))
+#define GPN1		(PIN(13,0) | PUD)
+#define GPN1_GPIO	(GPN1 | FUNC(0))
+#define GPN2		(PIN(13,0) | PUD)
+#define GPN2_GPIO	(GPN2 | FUNC(0))
+#define GPN3		(PIN(13,0) | PUD)
+#define GPN3_GPIO	(GPN3 | FUNC(0))
+#define GPN4		(PIN(13,0) | PUD)
+#define GPN4_GPIO	(GPN4 | FUNC(0))
+#define GPN5		(PIN(13,0) | PUD)
+#define GPN5_GPIO	(GPN5 | FUNC(0))
+#define GPN6		(PIN(13,0) | PUD)
+#define GPN6_GPIO	(GPN6 | FUNC(0))
+#define GPN7		(PIN(13,0) | PUD)
+#define GPN7_GPIO	(GPN7 | FUNC(0))
+#define GPN8		(PIN(13,0) | PUD)
+#define GPN8_GPIO	(GPN8 | FUNC(0))
+#define GPN9		(PIN(13,0) | PUD)
+#define GPN9_GPIO	(GPN9 | FUNC(0))
+#define GPN10		(PIN(13,20) | PUD)
+#define GPN10_GPIO	(GPN10 | FUNC(0))
+#define GPN11		(PIN(13,20) | PUD)
+#define GPN11_GPIO	(GPN11 | FUNC(0))
+#define GPN12		(PIN(13,20) | PUD)
+#define GPN12_GPIO	(GPN12 | FUNC(0))
+#define GPN13		(PIN(13,20) | PUD)
+#define GPN13_GPIO	(GPN13 | FUNC(0))
+#define GPN14		(PIN(13,20) | PUD)
+#define GPN14_GPIO	(GPN14 | FUNC(0))
+#define GPN15		(PIN(13,20) | PUD)
+#define GPN15_GPIO	(GPN15 | FUNC(0))
+
+#define GPO0		(PIN(14,0) | PUD)
+#define GPO0_NCS2	(GPO0 | FUNC(2))
+#define GPO1		(PIN(14,2) | PUD)
+#define GPO1_NCS3	(GPO1 | FUNC(2))
+#define GPO2		(PIN(14,4) | PUD)
+#define GPO2_NCS4	(GPO2 | FUNC(2))
+#define GPO3		(PIN(14,6) | PUD)
+#define GPO3_GPIO	(GPO3 | FUNC(0))
+#define GPO4		(PIN(14,8) | PUD)
+#define GPO4_GPIO	(GPO4 | FUNC(0))
+#define GPO5		(PIN(14,10) | PUD)
+#define GPO5_GPIO	(GPO5 | FUNC(0))
+#define GPO6		(PIN(14,12) | PUD)
+#define GPO6_ADDR6	(GPO6 | FUNC(2))
+#define GPO7		(PIN(14,14) | PUD)
+#define GPO7_GPIO	(GPO7 | FUNC(0))
+#define GPO7_ADDR7	(GPO7 | FUNC(2))
+#define GPO8		(PIN(14,16) | PUD)
+#define GPO8_GPIO	(GPO8 | FUNC(0))
+#define GPO8_ADDR8	(GPO8 | FUNC(2))
+#define GPO9		(PIN(14,18) | PUD)
+#define GPO9_GPIO	(GPO9 | FUNC(0))
+#define GPO9_ADDR9	(GPO9 | FUNC(2))
+#define GPO10		(PIN(14,20) | PUD)
+#define GPO10_GPIO	(GPO10 | FUNC(2))
+#define GPO10_ADDR10	(GPO10 | FUNC(2))
+#define GPO11		(PIN(14,22) | PUD)
+#define GPO11_GPIO	(GPO11 | FUNC(0))
+#define GPO11_ADDR11	(GPO11 | FUNC(2))
+#define GPO12		(PIN(14,24) | PUD)
+#define GPO12_GPIO	(GPO12 | FUNC(0))
+#define GPO12_ADDR12	(GPO12 | FUNC(2))
+#define GPO13		(PIN(14,26) | PUD)
+#define GPO13_GPIO	(GPO13 | FUNC(0))
+#define GPO13_ADDR13	(GPO13 | FUNC(2))
+#define GPO14		(PIN(14,28) | PUD)
+#define GPO14_GPIO	(GPO14 | FUNC(0))
+#define GPO14_ADDR14	(GPO14 | FUNC(2))
+#define GPO15		(PIN(14,30) | PUD)
+#define GPO15_GPIO	(GPO15 | FUNC(0))
+#define GPO15_ADDR15	(GPO15 | FUNC(2))
+
+#define GPP0		(PIN(15,0) | PUD)
+#define GPP0_GPIO	(GPP0 | FUNC(0))
+#define GPP1		(PIN(15,2) | PUD)
+#define GPP1_GPIO	(GPP1 | FUNC(0))
+#define GPP2		(PIN(15,4) | PUD)
+#define GPP2_NWAIT	(GPP2 | FUNC(2))
+#define GPP3		(PIN(15,6) | PUD)
+#define GPP3_FALE	(GPP3 | FUNC(2))
+#define GPP4		(PIN(15,8) | PUD)
+#define GPP4_FCLE	(GPP4 | FUNC(2))
+#define GPP5		(PIN(15,10) | PUD)
+#define GPP5_FWE	(GPP5 | FUNC(2))
+#define GPP6		(PIN(15,12) | PUD)
+#define GPP6_FRE	(GPP6 | FUNC(2))
+#define GPP7		(PIN(15,14) | PUD)
+#define GPP7_RNB	(GPP7 | FUNC(2))
+#define GPP8		(PIN(15,16) | PUD)
+#define GPP8_GPIO	(GPP8 | FUNC(0))
+#define GPP9		(PIN(15,18) | PUD)
+#define GPP9_GPIO	(GPP9 | FUNC(0))
+#define GPP10		(PIN(15,20) | PUD)
+#define GPP10_GPIO	(GPP10 | FUNC(0))
+#define GPP11		(PIN(15,22) | PUD)
+#define GPP11_GPIO	(GPP11 | FUNC(0))
+#define GPP12		(PIN(15,24) | PUD)
+#define GPP12_GPIO	(GPP12 | FUNC(0))
+#define GPP13		(PIN(15,26) | PUD)
+#define GPP13_GPIO	(GPP13 | FUNC(0))
+#define GPP14		(PIN(15,28) | PUD)
+#define GPP14_GPIO	(GPP14 | FUNC(0))
+
+#define GPQ0		(PIN(16,0) | PUD)
+#define GPQ0_GPIO	(GPQ0 | FUNC(0))
+#define GPQ1		(PIN(16,2) | PUD)
+#define GPQ1_GPIO	(GPQ1 | FUNC(0))
+#define GPQ2		(PIN(16,4) | PUD)
+#define GPQ2_GPIO	(GPQ2 | FUNC(0))
+#define GPQ3		(PIN(16,8) | PUD)
+#define GPQ3_GPIO	(GPQ3 | FUNC(0))
+#define GPQ4		(PIN(16,8) | PUD)
+#define GPQ4_GPIO	(GPQ4 | FUNC(0))
+#define GPQ5		(PIN(16,10) | PUD)
+#define GPQ5_GPIO	(GPQ5 | FUNC(0))
+#define GPQ6		(PIN(16,12) | PUD)
+#define GPQ6_GPIO	(GPQ6 | FUNC(0))
+#define GPQ7		(PIN(16,14) | PUD)
+#define GPQ7_GPIO	(GPQ7 | FUNC(0))
+#define GPQ8		(PIN(16,16) | PUD)
+#define GPQ8_GPIO	(GPQ7 | FUNC(0))
+
+
+#endif /* __MACH_IOMUX_S3C64XX_H */
-- 
1.7.10.4


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[PATCH 16/18] ARM/Samsung: add generic S3C6410 SoC specific functions

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/mach-samsung/Makefile                   |    2 +-
 arch/arm/mach-samsung/include/mach/s3c-generic.h |   13 +++++
 arch/arm/mach-samsung/mem-s3c64xx.c              |   65 ++++++++++++++++++++++
 3 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/mem-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 5187170..9402289 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -3,6 +3,6 @@ obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 329c2b4..42e8c5f 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -47,3 +47,16 @@ void s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int
 void s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
 uint32_t s5p_get_memory_size(void);
 #endif
+
+#ifdef CONFIG_ARCH_S3C64xx
+unsigned s3c6410_get_memory_size(void);
+struct s3c6410_chipselect {
+	unsigned adr_setup_t; /* in [ns] */
+	unsigned access_setup_t; /* in [ns] */
+	unsigned access_t; /* in [ns] */
+	unsigned cs_hold_t; /* in [ns] */
+	unsigned adr_hold_t; /* in [ns] */
+	unsigned char width; /* 8 or 16 */
+};
+int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
+#endif
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c b/arch/arm/mach-samsung/mem-s3c64xx.c
new file mode 100644
index 0000000..f312fb2
--- /dev/null
+++ b/arch/arm/mach-samsung/mem-s3c64xx.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <errno.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+
+#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
+
+/* note: this routine honors the first memory bank only */
+unsigned s3c6410_get_memory_size(void)
+{
+	unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG) & 0xff;
+
+	return ~(reg << 24) + 1;
+}
+
+/* configure the timing of one of the available external chip select lines */
+int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
+{
+	unsigned per_t = 1000000000 / s3c_get_hclk();
+	unsigned tacs, tcos, tacc, tcoh, tcah, shift;
+	uint32_t reg;
+
+	/* start of cycle to chip select assertion (= address/data setup) */
+	tacs = DIV_ROUND_UP(c->adr_setup_t, per_t);
+	/* start of CS to read/write assertion (= access setup) */
+	tcos = DIV_ROUND_UP(c->access_setup_t, per_t);
+	/* length of read/write assertion (= access lenght) */
+	tacc = DIV_ROUND_UP(c->access_t, per_t) - 1;
+	/* CS hold after access is finished */
+	tcoh = DIV_ROUND_UP(c->cs_hold_t, per_t);
+	/* adress/data hold after CS is deasserted */
+	tcah = DIV_ROUND_UP(c->adr_hold_t, per_t);
+
+	shift = no * 4;
+	reg = readl(S3C_SROM_BW) & ~(0xf << shift);
+	if (c->width == 16)
+		reg |= 0x1 << shift;
+	writel(reg, S3C_SROM_BW);
+#ifdef DEBUG
+	if (tacs > 15 || tcos > 15 || tacc > 31 || tcoh > 15 || tcah > 15) {
+		pr_err("At least one of the timings are invalid\n");
+		return -EINVAL;
+	}
+	pr_info("Will write 0x%08X\n", tacs << 28 | tcos << 24 | tacc << 16 |
+					tcoh << 12 | tcah << 8);
+#endif
+	writel(tacs << 28 | tcos << 24 | tacc << 16 | tcoh << 12 | tcah << 8,
+						S3C_SROM_BC0 + shift);
+
+	return 0;
+}
-- 
1.7.10.4


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[PATCH 17/18] ARM/Samsung: add the S3C6410 SoC

[Juergen Beisert]

After adding the base support, the CPU can now be enabled in the build system.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/Kconfig              |    6 ++++++
 arch/arm/mach-samsung/Kconfig |   21 ++++++++++++++++++++-
 drivers/serial/Kconfig        |    2 +-
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9590db9..2e79005 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -81,6 +81,12 @@ config ARCH_S3C24xx
 #	select CPU_V7
 #	select GENERIC_GPIO
 
+config ARCH_S3C64xx
+	bool "Samsung S3C64xx"
+	select ARCH_SAMSUNG
+	select CPU_V6
+	select GENERIC_GPIO
+
 config ARCH_VERSATILE
 	bool "ARM Versatile boards (ARM926EJ-S)"
 	select CPU_ARM926T
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 28bbc97..8acb7c9 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -19,6 +19,8 @@ config BOARDINFO
 config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
 	hex
 	default 0x1ff0 if ARCH_S5PCxx
+# TODO
+	default 0x2000 if ARCH_S3C64xx
 
 config SAMSUNG_IMPROVED_UART
 	bool
@@ -89,6 +91,24 @@ endmenu
 
 endif
 
+if ARCH_S3C64xx
+
+config CPU_S3C6410
+	select SAMSUNG_IMPROVED_UART
+	bool
+
+choice
+
+	prompt "S3C64xx Board Type"
+
+endchoice
+
+menu "Board specific settings       "
+
+endmenu
+
+endif
+
 if ARCH_S5PCxx
 
 config CPU_S5PC110
@@ -114,7 +134,6 @@ endchoice
 
 endif
 
-
 menu "S3C Features              "
 
 config S3C_LOWLEVEL_INIT
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a118aaf..283573e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -90,7 +90,7 @@ config DRIVER_SERIAL_S3C_CLK
 	prompt "input clock reference"
 	depends on DRIVER_SERIAL_S3C
 	default 0 if ARCH_S3C24xx
-	default 3 if ARCH_S5PCxx
+	default 3 if ARCH_S3C64xx || ARCH_S5PCxx
 	help
 	  Select one of up to four available clock sources for the UART:
 	   0+1: PCLK, 2: UCLK0, 3: UCLK1
-- 
1.7.10.4


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[PATCH 18/18] ARM/Samsung: add the Mini6410 platform as the first user of the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
---
 arch/arm/Makefile                   |    1 +
 arch/arm/boards/mini6410/Kconfig    |   27 +++
 arch/arm/boards/mini6410/Makefile   |    1 +
 arch/arm/boards/mini6410/config.h   |    8 +
 arch/arm/boards/mini6410/env/config |   56 +++++++
 arch/arm/boards/mini6410/mini6410.c |  317 +++++++++++++++++++++++++++++++++++
 arch/arm/configs/mini6410_defconfig |   40 +++++
 arch/arm/mach-samsung/Kconfig       |   12 ++
 8 files changed, 462 insertions(+)
 create mode 100644 arch/arm/boards/mini6410/Kconfig
 create mode 100644 arch/arm/boards/mini6410/Makefile
 create mode 100644 arch/arm/boards/mini6410/config.h
 create mode 100644 arch/arm/boards/mini6410/env/config
 create mode 100644 arch/arm/boards/mini6410/mini6410.c
 create mode 100644 arch/arm/configs/mini6410_defconfig

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9488359..6af9da2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -123,6 +123,7 @@ board-$(CONFIG_MACH_FREESCALE_MX53_LOCO)	:= freescale-mx53-loco
 board-$(CONFIG_MACH_FREESCALE_MX53_SMD)		:= freescale-mx53-smd
 board-$(CONFIG_MACH_GUF_CUPID)			:= guf-cupid
 board-$(CONFIG_MACH_MINI2440)			:= mini2440
+board-$(CONFIG_MACH_MINI6410)			:= mini6410
 board-$(CONFIG_MACH_QIL_A9260)			:= qil-a9260
 board-$(CONFIG_MACH_TNY_A9260)			:= tny-a926x
 board-$(CONFIG_MACH_TNY_A9263)			:= tny-a926x
diff --git a/arch/arm/boards/mini6410/Kconfig b/arch/arm/boards/mini6410/Kconfig
new file mode 100644
index 0000000..6d378ff
--- /dev/null
+++ b/arch/arm/boards/mini6410/Kconfig
@@ -0,0 +1,27 @@
+if MACH_MINI6410
+
+config MINI6410_VIDEO
+	bool
+	select VIDEO
+	select DRIVER_VIDEO_S3C
+
+config MINI6410_VIDEO_N35
+	bool "Support N35 display (240x320)"
+#	select MINI2440_VIDEO
+	help
+	  This adds support for NEC 3.5 inch TFT display,
+	  the most common one used with MINI2440 board.
+
+config MINI6410_VIDEO_A70
+	bool "Support A70 display (800x480)"
+#	select MINI2440_VIDEO
+	help
+	  This adds support for Innolux 7.0 inch TFT display.
+
+config MINI6410_VIDEO_SVGA
+	bool "Support SVGA video adapter"
+#	select MINI2440_VIDEO
+	help
+	  This adds support for MINI2440 SVGA (1024x768) video output adapter.
+
+endif
diff --git a/arch/arm/boards/mini6410/Makefile b/arch/arm/boards/mini6410/Makefile
new file mode 100644
index 0000000..cd7a427
--- /dev/null
+++ b/arch/arm/boards/mini6410/Makefile
@@ -0,0 +1 @@
+obj-y += mini6410.o
diff --git a/arch/arm/boards/mini6410/config.h b/arch/arm/boards/mini6410/config.h
new file mode 100644
index 0000000..ee38192
--- /dev/null
+++ b/arch/arm/boards/mini6410/config.h
@@ -0,0 +1,8 @@
+/* FriendlyARM Mini6410 specific global settings */
+
+#ifndef _MINI6410_CONFIG_H_
+# define _MINI6410_CONFIG_H_
+
+#define S3C64XX_CLOCK_REFERENCE 12000000
+
+#endif /* _MINI6410_CONFIG_H_ */
diff --git a/arch/arm/boards/mini6410/env/config b/arch/arm/boards/mini6410/env/config
new file mode 100644
index 0000000..b160a0e
--- /dev/null
+++ b/arch/arm/boards/mini6410/env/config
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+machine=mini6410
+eth0.serverip=192.168.1.7
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+#ip=dhcp
+
+# or set your networking parameters here
+eth0.ipaddr=192.168.1.187
+eth0.netmask=255.255.255.0
+eth0.gateway=192.168.1.1
+eth0.ethaddr=08:90:90:90:90:90
+
+# can be either 'nfs', 'tftp' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-${machine}.${rootfs_type}
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-${machine}
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+	kernelimage="${user}"-"${kernelimage}"
+	nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}"
+	rootfsimage="${user}"-"${rootfsimage}"
+else
+	nfsroot="${eth0.serverip}:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+#
+# "mini6410" kernel parameter
+# 0 .. 9 = screen type
+# i = touchscreen with propritary FriendlyARM protocol
+# Note: can be "minit6410= " if nothing of these components are connected
+#
+bootargs="console=ttySAC0,115200 mini6410=0"
+
+nand_device="nand"
+nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)"
+rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/mini6410/mini6410.c b/arch/arm/boards/mini6410/mini6410.c
new file mode 100644
index 0000000..b586820
--- /dev/null
+++ b/arch/arm/boards/mini6410/mini6410.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * In some ways inspired by code
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <sizes.h>
+#include <generated/mach-types.h>
+#include <dm9000.h>
+#include <gpio.h>
+#include <io.h>
+#include <asm/armlinux.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+
+/*
+ * dm9000 network controller onboard
+ * Connected to CS line 1 and interrupt line EINT7,
+ * data width is 16 bit
+ * Area 1: Offset 0x300...0x301
+ * Area 2: Offset 0x304...0x305
+ */
+static struct dm9000_platform_data dm9000_data = {
+	.srom = 0,	/* no serial ROM for the ethernet address */
+};
+
+static const unsigned pin_usage[] = {
+	/* UART2 (spare, 3,3 V TTL level only) */
+	GPA4_RXD1 | ENABLE_PU,
+	GPA5_TXD1,
+	GPA6_NCTS1 | ENABLE_PU,
+	GPA7_NRTS1,
+	/* UART3 (spare, 3,3 V TTL level only) */
+	GPB0_RXD2 | ENABLE_PU,
+	GPB1_TXD2,
+	/* UART4 (spare, 3,3 V TTL level only) */
+	GPB2_RXD3 | ENABLE_PU,
+	GPB3_TXD3,
+
+	GPB4_GPIO | GPIO_IN | ENABLE_PU,
+
+	/* I2C bus */
+	GPB5_IIC0_SCL,	/* external PU */
+	GPB6_IIC0_SDA,	/* external PU */
+
+	GPC0_SPI0_MISO | ENABLE_PU,
+	GPC1_SPI0_CLK,
+	GPC2_SPI0_MOSI,
+	GPC3_SPI0_NCS,
+
+	GPC4_SPI1_MISO | ENABLE_PU,
+	GPC5_SPI1_CLK,
+	GPC6_SPI1_MOSI,
+	GPC7_SPI1_NCS,
+
+	GPD0_AC97_BITCLK,
+	GPD1_AC97_NRST,
+	GPD2_AC97_SYNC,
+	GPD3_AC97_SDI | ENABLE_PU,
+	GPD4_AC97_SDO,
+
+	GPE0_GPIO | GPIO_OUT | GPIO_VAL(0), /* LCD backlight off */
+	GPE1_GPIO | GPIO_IN | ENABLE_PU,
+	GPE2_GPIO | GPIO_IN | ENABLE_PU,
+	GPE3_GPIO | GPIO_IN | ENABLE_PU,
+	GPE4_GPIO | GPIO_IN | ENABLE_PU,
+
+	/* keep all camera signals at reasonable values */
+	GPF0_GPIO | GPIO_IN | ENABLE_PU,
+	GPF1_GPIO | GPIO_IN | ENABLE_PU,
+	GPF2_GPIO | GPIO_IN | ENABLE_PU,
+	GPF3_GPIO | GPIO_IN | ENABLE_PU,
+	GPF4_GPIO | GPIO_IN | ENABLE_PU,
+	GPF5_GPIO | GPIO_IN | ENABLE_PU,
+	GPF6_GPIO | GPIO_IN | ENABLE_PU,
+	GPF7_GPIO | GPIO_IN | ENABLE_PU,
+	GPF8_GPIO | GPIO_IN | ENABLE_PU,
+	GPF9_GPIO | GPIO_IN | ENABLE_PU,
+	GPF10_GPIO | GPIO_IN | ENABLE_PU,
+	GPF11_GPIO | GPIO_IN | ENABLE_PU,
+	GPF12_GPIO | GPIO_IN | ENABLE_PU,
+	GPF13_GPIO | GPIO_OUT | GPIO_VAL(0), /* USB power off */
+	GPF14_GPIO | GPIO_OUT | GPIO_VAL(0), /* Buzzer off */
+	GPF15_GPIO | GPIO_OUT | GPIO_VAL(0), /* Backlight PWM inactive */
+
+	/* SD card slot (all signals have external PU) */
+	GPG0_MMC0_CLK,
+	GPG1_MMC0_CMD,
+	GPG2_MMC0_DAT0,
+	GPG3_MMC0_DAT1,
+	GPG4_MMC0_DAT2,
+	GPG5_MMC0_DAT3,
+	GPG6_MMC0_NCD,
+
+	/* SDIO slot (all used signals have external PU) */
+	GPH0_GPIO | GPIO_IN,	/* CLK */
+	GPH1_GPIO | GPIO_IN,	/* CMD */
+	GPH2_GPIO | GPIO_IN,	/* DAT0 */
+	GPH3_GPIO | GPIO_IN,	/* DAT1 */
+	GPH4_GPIO | GPIO_IN,	/* DAT2 */
+	GPH5_GPIO | GPIO_IN,	/* DAT3 */
+	GPH6_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
+	GPH7_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
+	GPH8_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
+	GPH9_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */
+
+	/* as long as we are not using the LCD controller, disable the pins */
+	GPI0_GPIO | GPIO_IN | ENABLE_PD,
+	GPI1_GPIO | GPIO_IN | ENABLE_PD,
+	GPI2_GPIO | GPIO_IN | ENABLE_PD,
+	GPI3_GPIO | GPIO_IN | ENABLE_PD,
+	GPI4_GPIO | GPIO_IN | ENABLE_PD,
+	GPI5_GPIO | GPIO_IN | ENABLE_PD,
+	GPI6_GPIO | GPIO_IN | ENABLE_PD,
+	GPI7_GPIO | GPIO_IN | ENABLE_PD,
+	GPI8_GPIO | GPIO_IN | ENABLE_PD,
+	GPI9_GPIO | GPIO_IN | ENABLE_PD,
+	GPI10_GPIO | GPIO_IN | ENABLE_PD,
+	GPI11_GPIO | GPIO_IN | ENABLE_PD,
+	GPI12_GPIO | GPIO_IN | ENABLE_PD,
+	GPI13_GPIO | GPIO_IN | ENABLE_PD,
+	GPI14_GPIO | GPIO_IN | ENABLE_PD,
+	GPI15_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ0_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ1_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ2_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ3_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ4_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ5_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ6_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ7_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ8_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ9_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ10_GPIO | GPIO_IN | ENABLE_PD,
+	GPJ11_GPIO | GPIO_IN | ENABLE_PD,
+
+	GPK0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK2_GPIO | GPIO_IN,
+	GPK3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK4_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #1 (high = LED off) */
+	GPK5_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #2 (high = LED off) */
+	GPK6_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #3 (high = LED off) */
+	GPK7_GPIO | GPIO_OUT | GPIO_VAL(1),	/* LED #4 (high = LED off) */
+	GPK8_GPIO | GPIO_IN, 			/* (external PU) */
+	GPK9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK12_GPIO | GPIO_IN,			/* OCT_DET */
+	GPK13_GPIO | GPIO_IN,			/* WIFI power (external PU) */
+	GPK14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPK15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+
+	GPL0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL2_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL4_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL6_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPL8_GPIO | GPIO_IN,			/* EINT16 (external PU) */
+	GPL9_GPIO | GPIO_IN | ENABLE_PU,	/* EINT17 */
+	GPL10_GPIO | GPIO_IN | ENABLE_PU,	/* EINT18 */
+	GPL11_GPIO | GPIO_IN,			/* EINT19 + K7 (external PU) */
+	GPL12_GPIO | GPIO_IN,			/* EINT20 + K6 (external PU) */
+	GPL13_GPIO | GPIO_IN,			/* SD0 WP (external PU) */
+	GPL14_GPIO | GPIO_IN,			/* SD1 WP (external PU) */
+
+	GPM0_GPIO | GPIO_IN,			/* (external PU) */
+	GPM1_GPIO | GPIO_IN,			/* (external PU) */
+	GPM2_GPIO | GPIO_IN,			/* (external PU) */
+	GPM3_GPIO | GPIO_IN,			/* (external PU) */
+	GPM4_GPIO | GPIO_IN,			/* (external PU) */
+	GPM5_GPIO | GPIO_IN,			/* (external PU) */
+
+	GPN0_GPIO | GPIO_IN,			/* EINT0 (external PU) */
+	GPN1_GPIO | GPIO_IN,			/* EINT1 (external PU) */
+	GPN2_GPIO | GPIO_IN,			/* EINT2 (external PU) */
+	GPN3_GPIO | GPIO_IN,			/* EINT3 (external PU) */
+	GPN4_GPIO | GPIO_IN,			/* EINT4 (external PU) */
+	GPN5_GPIO | GPIO_IN,			/* EINT5 (external PU) */
+	GPN6_GPIO | GPIO_IN,			/* EINT6 (external PU) */
+	GPN7_GPIO | GPIO_IN | ENABLE_PU,	/* EINT7 DM9000 interrupt */
+	GPN8_GPIO | GPIO_IN,			/* EINT8 USB detect (external PU) */
+	GPN9_GPIO | GPIO_IN,			/* EINT9 (external PU) */
+	GPN10_GPIO | GPIO_IN,			/* SD1 CD (external PU) */
+	GPN11_GPIO | GPIO_IN,			/* EINT11 (external PU) */
+	GPN12_GPIO | GPIO_IN,			/* EINT12 IR in (external PU) */
+	GPN13_GPIO | GPIO_IN,			/* BOOT0/EINT13 (externally fixed) */
+	GPN14_GPIO | GPIO_IN,			/* BOOT1/EINT14 (externally fixed) */
+	GPN15_GPIO | GPIO_IN,			/* BOOT2/EINT15 (externally fixed) */
+
+	GPO0_NCS2,				/* NAND */
+	GPO1_NCS3,				/* NAND */
+	GPO2_NCS4,				/* CON5 */
+	GPO3_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO4_GPIO | GPIO_IN | ENABLE_PU,	/* CON5 pin 8 */
+	GPO5_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO6_ADDR6,				/* CON5 */
+	GPO7_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO10_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO11_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPO15_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+
+	GPP0_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP1_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP2_NWAIT | ENABLE_PU,			/* CON5 */
+	GPP3_FALE,				/* NAND */
+	GPP4_FCLE,				/* NAND */
+	GPP5_FWE,				/* NAND */
+	GPP6_FRE,				/* NAND */
+	GPP7_RNB,				/* NAND (external PU) */
+	GPP8_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP9_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP10_GPIO | GPIO_IN,			/* (external PU) */
+	GPP11_GPIO | GPIO_IN,			/* (external PU) */
+	GPP12_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP13_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+	GPP14_GPIO | GPIO_IN | ENABLE_PU,	/* not used */
+
+	GPQ0_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR18 */
+	GPQ1_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ2_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ3_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ4_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ5_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ6_GPIO | GPIO_IN,			/* (external PU) */
+	GPQ7_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR17 */
+	GPQ8_GPIO | GPIO_IN | ENABLE_PU,	/* not used as LADDR16 */
+};
+
+static int mini6410_mem_init(void)
+{
+	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size());
+
+	return 0;
+}
+mem_initcall(mini6410_mem_init);
+
+static const struct s3c6410_chipselect dm900_cs = {
+	.adr_setup_t = 0,
+	.access_setup_t = 0,
+	.access_t = 20,
+	.cs_hold_t = 3,
+	.adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */
+	.width = 16,
+};
+
+static void mini6410_setup_dm9000_cs(void)
+{
+	s3c6410_setup_chipselect(1, &dm900_cs);
+}
+
+static int mini6410_devices_init(void)
+{
+	int i;
+
+	/* ----------- configure the access to the outer space ---------- */
+	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
+		s3c_gpio_mode(pin_usage[i]);
+
+	mini6410_setup_dm9000_cs();
+	add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304,
+				IORESOURCE_MEM_16BIT, &dm9000_data);
+
+	armlinux_set_bootparams((void *)S3C_SDRAM_BASE + 0x100);
+	armlinux_set_architecture(MACH_TYPE_MINI6410);
+
+	return 0;
+}
+
+device_initcall(mini6410_devices_init);
+
+static int mini6410_console_init(void)
+{
+	/*
+	 * configure the UART1 right now, as barebox will
+	 * start to send data immediately
+	 */
+	s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU);
+	s3c_gpio_mode(GPA1_TXD0);
+	s3c_gpio_mode(GPA2_NCTS0 | ENABLE_PU);
+	s3c_gpio_mode(GPA3_NRTS0);
+
+	add_generic_device("s3c_serial", -1, NULL, S3C_UART1_BASE,
+				S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+
+	return 0;
+}
+
+console_initcall(mini6410_console_init);
diff --git a/arch/arm/configs/mini6410_defconfig b/arch/arm/configs/mini6410_defconfig
new file mode 100644
index 0000000..61872c8
--- /dev/null
+++ b/arch/arm/configs/mini6410_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARCH_S3C64xx=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_BROKEN=y
+CONFIG_PROMPT="mini6410:"
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_PARTITION_DISK=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/mini6410/env"
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_DRIVER_NET_DM9K=y
+# CONFIG_SPI is not set
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 8acb7c9..746c029 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -6,12 +6,14 @@ if ARCH_SAMSUNG
 config ARCH_TEXT_BASE
 	hex
 	default 0x31fc0000 if MACH_MINI2440
+	default 0x57fc0000 if MACH_MINI6410
 	default 0x31fc0000 if MACH_A9M2440
 	default 0x31fc0000 if MACH_A9M2410
 	default 0x23e00000 if MACH_TINY210
 
 config BOARDINFO
 	default "Mini 2440"    if MACH_MINI2440
+	default "Mini 6410"    if MACH_MINI6410
 	default "Digi A9M2440" if MACH_A9M2440
 	default "Digi A9M2410" if MACH_A9M2410
 	default "Tiny 210"     if MACH_TINY210
@@ -101,10 +103,20 @@ choice
 
 	prompt "S3C64xx Board Type"
 
+config MACH_MINI6410
+	bool "Mini 6410"
+	select CPU_S3C6410
+	select HAS_DM9000
+	help
+	  Say Y here if you are using FriendlyARM Mini6410 board equipped
+	  with a Samsung S3C6410 Processor
+
 endchoice
 
 menu "Board specific settings       "
 
+source arch/arm/boards/mini6410/Kconfig
+
 endmenu
 
 endif
-- 
1.7.10.4


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Re: [PATCH 05/18] Samsung/serial: make the clock source configureable

[Sascha Hauer]

On Fri, Jul 13, 2012 at 09:00:57PM +0200, Juergen Beisert wrote:
> Instead of taking the value from somewhere, use the menu to select one. Also
> provide sane default values for known SoCs.

Do we really really need this in Kconfig? I don't like having things in
Kconfig which decide between 'right' and 'wrong'. You should rather have
some cpu_is or platformdata mechanism.

Sascha

> 
> Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
> ---
>  drivers/serial/Kconfig      |   12 ++++++++++++
>  drivers/serial/serial_s3c.c |    7 +------
>  2 files changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index a9383da..a118aaf 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -85,6 +85,18 @@ config DRIVER_SERIAL_S3C
>  	help
>  	  Say Y here if you want to use the CONS on a Samsung S3C CPU
>  
> +config DRIVER_SERIAL_S3C_CLK
> +	int
> +	prompt "input clock reference"
> +	depends on DRIVER_SERIAL_S3C
> +	default 0 if ARCH_S3C24xx
> +	default 3 if ARCH_S5PCxx
> +	help
> +	  Select one of up to four available clock sources for the UART:
> +	   0+1: PCLK, 2: UCLK0, 3: UCLK1
> +	  Note: not all values are possible on all Samsung SoCs. Read the
> +	  manual if unsure.
> +
>  config DRIVER_SERIAL_S3C_AUTOSYNC
>  	bool "Enable auto flow"
>  	depends on DRIVER_SERIAL_S3C
> diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
> index ff3792b..5c05ba8 100644
> --- a/drivers/serial/serial_s3c.c
> +++ b/drivers/serial/serial_s3c.c
> @@ -47,11 +47,6 @@
>  # define UINTM 0x38		/* interrupt mask register */
>  #endif
>  
> -#ifndef S3C_UART_CLKSEL
> -/* Use pclk */
> -# define S3C_UART_CLKSEL 0
> -#endif
> -
>  struct s3c_uart {
>  	void __iomem *regs;
>  	struct console_device cdev;
> @@ -108,7 +103,7 @@ static int s3c_serial_init_port(struct console_device *cdev)
>  
>  	/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
>  	 * normal, interrupt or polling, no pre-divider */
> -	writew(0x0245 | ((S3C_UART_CLKSEL) << 10), base + UCON);
> +	writew(0x0245 | ((CONFIG_DRIVER_SERIAL_S3C_CLK) << 10), base + UCON);
>  
>  #ifdef S3C_UART_HAS_UINTM
>  	/* 'interrupt or polling mode' for both directions */
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 02/18] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Sascha Hauer]

On Fri, Jul 13, 2012 at 09:00:54PM +0200, Juergen Beisert wrote:
> Barebox crashes since it has trouble with a resource size of 0. Most of the
> S3C24XX based platforms crashes at runtime and can't use devices with resource
> sizes of 0 anymore. This patch fix it by unifying the device registration for
> all current Barebox's S3C24XX based platforms.
> 
> - A9M2410 and A9M2440 compile time tested only.
> - Mini2440 also runtime tested.

So this is stuff for master, right?

Sascha

> 
> Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
> ---
>  arch/arm/boards/a9m2410/a9m2410.c                  |    6 +--
>  arch/arm/boards/a9m2440/a9m2440.c                  |    7 ++-
>  arch/arm/boards/mini2440/mini2440.c                |   16 +++---
>  .../mach-samsung/include/mach/devices-s3c24xx.h    |   54 ++++++++++++++++++++
>  4 files changed, 65 insertions(+), 18 deletions(-)
>  create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
> 
> diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
> index eaafdbd..c2d4b87 100644
> --- a/arch/arm/boards/a9m2410/a9m2410.c
> +++ b/arch/arm/boards/a9m2410/a9m2410.c
> @@ -32,6 +32,7 @@
>  #include <partition.h>
>  #include <nand.h>
>  #include <io.h>
> +#include <mach/devices-s3c24xx.h>
>  #include <mach/s3c-iomap.h>
>  #include <mach/s3c24xx-nand.h>
>  #include <mach/s3c-generic.h>
> @@ -109,8 +110,7 @@ static int a9m2410_devices_init(void)
>  	writel(reg, S3C_MISCCR);
>  
>  	/* ----------- the devices the boot loader should work with -------- */
> -	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
> -			0, IORESOURCE_MEM, &nand_info);
> +	s3c24xx_add_nand(&nand_info);
>  	/*
>  	 * SMSC 91C111 network controller on the baseboard
>  	 * connected to CS line 1 and interrupt line
> @@ -145,8 +145,6 @@ void __bare_init nand_boot(void)
>  
>  static int a9m2410_console_init(void)
>  {
> -	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
> -			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
>  	return 0;
>  }
>  
> diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
> index 1d20248..8975c15 100644
> --- a/arch/arm/boards/a9m2440/a9m2440.c
> +++ b/arch/arm/boards/a9m2440/a9m2440.c
> @@ -32,6 +32,7 @@
>  #include <partition.h>
>  #include <nand.h>
>  #include <io.h>
> +#include <mach/devices-s3c24xx.h>
>  #include <mach/s3c-iomap.h>
>  #include <mach/s3c24xx-nand.h>
>  #include <mach/s3c-generic.h>
> @@ -129,8 +130,7 @@ static int a9m2440_devices_init(void)
>  	writel(reg, S3C_MISCCR);
>  
>  	/* ----------- the devices the boot loader should work with -------- */
> -	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, 0,
> -			   IORESOURCE_MEM, &nand_info);
> +	s3c24xx_add_nand(&nand_info);
>  	/*
>  	 * cs8900 network controller onboard
>  	 * Connected to CS line 5 + A24 and interrupt line EINT9,
> @@ -164,8 +164,7 @@ void __bare_init nand_boot(void)
>  
>  static int a9m2440_console_init(void)
>  {
> -	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
> -			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
> +	s3c24xx_add_uart1();
>  	return 0;
>  }
>  
> diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
> index 3d3b820..3523949 100644
> --- a/arch/arm/boards/mini2440/mini2440.c
> +++ b/arch/arm/boards/mini2440/mini2440.c
> @@ -39,6 +39,7 @@
>  #include <io.h>
>  #include <mach/gpio.h>
>  #include <mach/s3c-iomap.h>
> +#include <mach/devices-s3c24xx.h>
>  #include <mach/s3c24xx-nand.h>
>  #include <mach/s3c-generic.h>
>  #include <mach/s3c-mci.h>
> @@ -297,8 +298,7 @@ static int mini2440_devices_init(void)
>  	reg |= 0x10000;
>  	writel(reg, S3C_MISCCR);
>  
> -	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE,
> -			0, IORESOURCE_MEM, &nand_info);
> +	s3c24xx_add_nand(&nand_info);
>  
>  	add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
>  			  IORESOURCE_MEM_16BIT, &dm9000_data);
> @@ -312,12 +312,9 @@ static int mini2440_devices_init(void)
>  	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
>  	dev_add_bb_dev("env_raw", "env0");
>  #endif
> -	add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
> -			   IORESOURCE_MEM, &mci_data);
> -	add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
> -			   IORESOURCE_MEM, &s3c24x0_fb_data);
> -	add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
> -			   IORESOURCE_MEM, NULL);
> +	s3c24xx_add_mci(&mci_data);
> +	s3c24xx_add_fb(&s3c24x0_fb_data);
> +	s3c24xx_add_ohci();
>  	armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
>  	armlinux_set_architecture(MACH_TYPE_MINI2440);
>  
> @@ -344,8 +341,7 @@ static int mini2440_console_init(void)
>  	s3c_gpio_mode(GPH2_TXD0);
>  	s3c_gpio_mode(GPH3_RXD0);
>  
> -	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
> -			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
> +	s3c24xx_add_uart1();
>  	return 0;
>  }
>  
> diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
> new file mode 100644
> index 0000000..d099732
> --- /dev/null
> +++ b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright 2012 Juergen Beisert
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H
> +# define INCLUDE_MACH_DEVICES_S3C24XX_H
> +
> +#include <mach/s3c24xx-iomap.h>
> +#include <mach/s3c24xx-nand.h>
> +#include <mach/s3c-mci.h>
> +#include <mach/s3c24xx-fb.h>
> +
> +static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d)
> +{
> +	add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL,
> +				S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d);
> +}
> +
> +static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d)
> +{
> +	add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL,
> +				S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d);
> +}
> +
> +static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d)
> +{
> +	add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL,
> +				S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d);
> +}
> +
> +static inline void s3c24xx_add_ohci(void)
> +{
> +	add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL,
> +			S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL);
> +}
> +
> +static inline void s3c24xx_add_uart1(void)
> +{
> +	add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
> +			S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
> +}
> +
> +#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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Re: [PATCH 11/18] ARM/Samsung: add generic lowlevel init

[Sascha Hauer]

On Fri, Jul 13, 2012 at 09:01:03PM +0200, Juergen Beisert wrote:
> Just a placeholder for some required low level routines
> ---
>  arch/arm/mach-samsung/Makefile           |    1 +
>  arch/arm/mach-samsung/lowlevel-s3c64xx.c |   14 ++++++++++++++
>  2 files changed, 15 insertions(+)
>  create mode 100644 arch/arm/mach-samsung/lowlevel-s3c64xx.c

Please just drop this one.

Sascha

> 
> diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
> index 091b600..ac34d86 100644
> --- a/arch/arm/mach-samsung/Makefile
> +++ b/arch/arm/mach-samsung/Makefile
> @@ -1,5 +1,6 @@
>  obj-y += s3c-timer.o generic.o
>  obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
> +obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
>  obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
>  obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
>  obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
> diff --git a/arch/arm/mach-samsung/lowlevel-s3c64xx.c b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
> new file mode 100644
> index 0000000..b1ba719
> --- /dev/null
> +++ b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
> @@ -0,0 +1,14 @@
> +/*
> + * Copyright (C) 2012 Juergen Beisert
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH 02/18] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Juergen Beisert]

Sascha Hauer wrote:
> On Fri, Jul 13, 2012 at 09:00:54PM +0200, Juergen Beisert wrote:
> > Barebox crashes since it has trouble with a resource size of 0. Most of
> > the S3C24XX based platforms crashes at runtime and can't use devices with
> > resource sizes of 0 anymore. This patch fix it by unifying the device
> > registration for all current Barebox's S3C24XX based platforms.
> >
> > - A9M2410 and A9M2440 compile time tested only.
> > - Mini2440 also runtime tested.
>
> So this is stuff for master, right?

Hmm, yes. :)

jbe

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