[PATCH 0/5] IMX i2c driver update for the PPC 85xx

[PATCH 0/5] IMX i2c driver update for the PPC 85xx

[Renaud Barbier]

This patch replaces the patch "ppc: Freescale TSEC driver".
This patch set prepares the PPC 85xx SOC to use the IMX i2c driver and updates
the driver with specific clock settings.
The patch also introduces a function returning the system clock to calculate
the i2c frequency bus divider. Finally, the P2020RDB board support is updated
to test the driver on 8-bit and 16-bit I2C.

This patch has not been tested on a IMX board.

Renaud Barbier (5):
  mpc85xx: i2c frequency
  ppc/asm/fsl_i2c.h is removed
  mpc85xx: header update
  i2c: adapt the i2c-imx driver to mpc85xx machines.
  ppc: p2020rdb i2c support

 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c      |   18 +++-
 arch/ppc/configs/p2020rdb_defconfig                |    3 +
 arch/ppc/include/asm/fsl_i2c.h                     |   86 -------------------
 .../include/mach/{clocks.h => clock.h}             |    1 +
 arch/ppc/mach-mpc85xx/include/mach/generic.h       |   24 ++++++
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h    |    3 +
 arch/ppc/mach-mpc85xx/speed.c                      |   11 ++-
 arch/ppc/mach-mpc85xx/time.c                       |    2 +-
 drivers/i2c/busses/Kconfig                         |    4 +-
 drivers/i2c/busses/i2c-imx.c                       |   87 +++++++++++++++++++-
 10 files changed, 143 insertions(+), 96 deletions(-)
 delete mode 100644 arch/ppc/include/asm/fsl_i2c.h
 rename arch/ppc/mach-mpc85xx/include/mach/{clocks.h => clock.h} (91%)
 create mode 100644 arch/ppc/mach-mpc85xx/include/mach/generic.h


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[PATCH 1/5] mpc85xx: i2c frequency

[Renaud Barbier]

A function that returns the system bus frequency used to compute the i2c bus
frequency is added for future use.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/mach-mpc85xx/include/mach/clocks.h |    1 +
 arch/ppc/mach-mpc85xx/speed.c               |    9 +++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
index 2ab367b..e20d685 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/clocks.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
@@ -12,5 +12,6 @@ struct sys_info {
 
 unsigned long fsl_get_bus_freq(ulong dummy);
 unsigned long fsl_get_timebase_clock(void);
+unsigned long fsl_get_i2c_freq(void);
 void fsl_get_sys_info(struct sys_info *sysInfo);
 #endif /* __ASM_ARCH_CLOCKS_H */
diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c
index 40d3664..fff2d22 100644
--- a/arch/ppc/mach-mpc85xx/speed.c
+++ b/arch/ppc/mach-mpc85xx/speed.c
@@ -102,3 +102,12 @@ unsigned long fsl_get_timebase_clock(void)
 
 	return (sysinfo.freqSystemBus + 4UL)/8UL;
 }
+
+unsigned long fsl_get_i2c_freq(void)
+{
+	struct sys_info sysinfo;
+
+	fsl_get_sys_info(&sysinfo);
+
+	return sysinfo.freqSystemBus / 2;
+}
-- 
1.7.1


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[PATCH 2/5] ppc/asm/fsl_i2c.h is removed

[Renaud Barbier]

The i2c-imx driver is able to support the I2C bus on the 85xx machines
with minor modifications. It already defines register offsets. Therefore,
this header file is no longer needed.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/include/asm/fsl_i2c.h |   86 ----------------------------------------
 1 files changed, 0 insertions(+), 86 deletions(-)
 delete mode 100644 arch/ppc/include/asm/fsl_i2c.h

diff --git a/arch/ppc/include/asm/fsl_i2c.h b/arch/ppc/include/asm/fsl_i2c.h
deleted file mode 100644
index 4f71341..0000000
--- a/arch/ppc/include/asm/fsl_i2c.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Freescale I2C Controller
- *
- * Copyright 2006 Freescale Semiconductor, Inc.
- *
- * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
- * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
- * and Jeff Brown.
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_FSL_I2C_H_
-#define _ASM_FSL_I2C_H_
-
-#include <asm/types.h>
-
-typedef struct fsl_i2c {
-
-	u8 adr;		/* I2C slave address */
-	u8 res0[3];
-#define I2C_ADR		0xFE
-#define I2C_ADR_SHIFT	1
-#define I2C_ADR_RES	~(I2C_ADR)
-
-	u8 fdr;		/* I2C frequency divider register */
-	u8 res1[3];
-#define IC2_FDR		0x3F
-#define IC2_FDR_SHIFT	0
-#define IC2_FDR_RES	~(IC2_FDR)
-
-	u8 cr;		/* I2C control redister	*/
-	u8 res2[3];
-#define I2C_CR_MEN	0x80
-#define I2C_CR_MIEN	0x40
-#define I2C_CR_MSTA	0x20
-#define I2C_CR_MTX	0x10
-#define I2C_CR_TXAK	0x08
-#define I2C_CR_RSTA	0x04
-#define I2C_CR_BCST	0x01
-
-	u8 sr;		/* I2C status register */
-	u8 res3[3];
-#define I2C_SR_MCF	0x80
-#define I2C_SR_MAAS	0x40
-#define I2C_SR_MBB	0x20
-#define I2C_SR_MAL	0x10
-#define I2C_SR_BCSTM	0x08
-#define I2C_SR_SRW	0x04
-#define I2C_SR_MIF	0x02
-#define I2C_SR_RXAK	0x01
-
-	u8 dr;		/* I2C data register */
-	u8 res4[3];
-#define I2C_DR		0xFF
-#define I2C_DR_SHIFT	0
-#define I2C_DR_RES	~(I2C_DR)
-
-	u8 dfsrr;	/* I2C digital filter sampling rate register */
-	u8 res5[3];
-#define I2C_DFSRR	0x3F
-#define I2C_DFSRR_SHIFT	0
-#define I2C_DFSRR_RES	~(I2C_DR)
-
-	/* Fill out the reserved block */
-	u8 res6[0xE8];
-} fsl_i2c_t;
-
-#endif	/* _ASM_I2C_H_ */
-- 
1.7.1


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[PATCH 3/5] mpc85xx: header update

[Renaud Barbier]

In order to use the IMX i2c driver on the mpc85xx SOC, the file
mach/clocks.h is renamed mach/clock.h. Files using this header are updated
accordingly. The file mach/generic.h is also added to accommodate the driver.

Finally, there is a clean up of a line too long.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c      |    6 ++--
 .../include/mach/{clocks.h => clock.h}             |    0
 arch/ppc/mach-mpc85xx/include/mach/generic.h       |   24 ++++++++++++++++++++
 arch/ppc/mach-mpc85xx/speed.c                      |    2 +-
 arch/ppc/mach-mpc85xx/time.c                       |    2 +-
 5 files changed, 29 insertions(+), 5 deletions(-)
 rename arch/ppc/mach-mpc85xx/include/mach/{clocks.h => clock.h} (100%)
 create mode 100644 arch/ppc/mach-mpc85xx/include/mach/generic.h

diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 734fef9..2de6cc4 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -34,7 +34,7 @@
 #include <mach/mpc85xx.h>
 #include <mach/mmu.h>
 #include <mach/immap_85xx.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 #include <mach/gianfar.h>
 #include <mach/early_udelay.h>
 
@@ -95,8 +95,8 @@ static int p2020_console_init(void)
 {
 	serial_plat.clock = fsl_get_bus_freq(0);
 
-	add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16, IORESOURCE_MEM_8BIT,
-			   &serial_plat);
+	add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16,
+			IORESOURCE_MEM_8BIT, &serial_plat);
 	return 0;
 }
 
diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clock.h
similarity index 100%
rename from arch/ppc/mach-mpc85xx/include/mach/clocks.h
rename to arch/ppc/mach-mpc85xx/include/mach/clock.h
diff --git a/arch/ppc/mach-mpc85xx/include/mach/generic.h b/arch/ppc/mach-mpc85xx/include/mach/generic.h
new file mode 100644
index 0000000..02f589b
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/generic.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * File derived from ARM architecture. Added so that the imx i2c driver
+ * can be used.
+ */
+
+#define cpu_is_mx1()	(0)
diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c
index fff2d22..6778d57 100644
--- a/arch/ppc/mach-mpc85xx/speed.c
+++ b/arch/ppc/mach-mpc85xx/speed.c
@@ -30,7 +30,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 #include <mach/immap_85xx.h>
 #include <mach/mpc85xx.h>
 
diff --git a/arch/ppc/mach-mpc85xx/time.c b/arch/ppc/mach-mpc85xx/time.c
index 408a28a..c50591c 100644
--- a/arch/ppc/mach-mpc85xx/time.c
+++ b/arch/ppc/mach-mpc85xx/time.c
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <clock.h>
 #include <init.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 
 uint64_t ppc_clocksource_read(void)
 {
-- 
1.7.1


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[PATCH 4/5] i2c: adapt the i2c-imx driver to mpc85xx machines.

[Renaud Barbier]

A function to calculate the frequency divider and digital filter sampling rate
for the 85xx processors is added to the i2c-imx driver. Hence, this driver is
used on IMX and 85xx machines.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h |    3 +
 drivers/i2c/busses/Kconfig                      |    4 +-
 drivers/i2c/busses/i2c-imx.c                    |   87 ++++++++++++++++++++++-
 3 files changed, 90 insertions(+), 4 deletions(-)

diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
index bf0f7f5..d2f8bbe 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
@@ -136,4 +136,7 @@
 
 #define GFAR_BASE_ADDR		(CFG_IMMR + TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CFG_IMMR + 0x24000)
+
+#define I2C1_BASE_ADDR		(CFG_IMMR + 0x3000)
+#define I2C2_BASE_ADDR		(CFG_IMMR + 0x3100)
 #endif /*__IMMAP_85xx__*/
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 1ce5c00..3f998ea 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -5,8 +5,8 @@
 menu "I2C Hardware Bus support"
 
 config I2C_IMX
-	bool "i.MX I2C Master driver"
-	depends on ARCH_IMX && !ARCH_IMX1
+	bool "MPC85xx/i.MX I2C Master driver"
+	depends on (ARCH_IMX && !ARCH_IMX1) || ARCH_MPC85XX
 
 config I2C_OMAP
 	bool "OMAP I2C Master driver"
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index da6218f..2dfa4f1 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
  * Copyright (C) 2002 Motorola GSG-China
  *               2009 Marc Kleine-Budde, Pengutronix
  *
@@ -22,7 +23,8 @@
  *
  * Desc.:
  *  Implementation of I2C Adapter/Algorithm Driver
- *  for I2C Bus integrated in Freescale i.MX/MXC processors
+ *  for I2C Bus integrated in Freescale i.MX/MXC processors and
+ *  85xx processors.
  *
  * Derived from Motorola GSG China I2C example driver
  *
@@ -36,7 +38,6 @@
 #include <clock.h>
 #include <common.h>
 #include <driver.h>
-#include <gpio.h>
 #include <init.h>
 #include <malloc.h>
 #include <types.h>
@@ -50,7 +51,11 @@
 #include <mach/clock.h>
 
 /* This will be the driver name */
+#ifdef CONFIG_PPC
+#define DRIVER_NAME "i2c-mpc"
+#else
 #define DRIVER_NAME "i2c-imx"
+#endif
 
 /* Default value */
 #define IMX_I2C_BIT_RATE	100000	/* 100kHz */
@@ -61,6 +66,7 @@
 #define IMX_I2C_I2CR	0x08	/* i2c control */
 #define IMX_I2C_I2SR	0x0C	/* i2c status */
 #define IMX_I2C_I2DR	0x10	/* i2c transfer data */
+#define IMX_I2C_DFSRR	0x14	/* i2c digital filter smapling rate */
 
 /* Bits of IMX I2C registers */
 #define I2SR_RXAK	0x01
@@ -85,6 +91,7 @@
  *
  * Duplicated divider values removed from list
  */
+#ifndef CONFIG_PPC
 static u16 i2c_clk_div[50][2] = {
 	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
 	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
@@ -100,6 +107,7 @@ static u16 i2c_clk_div[50][2] = {
 	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
+#endif
 
 struct imx_i2c_struct {
 	void __iomem		*base;
@@ -107,6 +115,7 @@ struct imx_i2c_struct {
 	unsigned int 		disable_delay;
 	int			stopped;
 	unsigned int		ifdr;	/* IMX_I2C_IFDR */
+	unsigned int		dfsrr;  /* IMX_I2C_DFSRR */
 };
 #define to_imx_i2c_struct(a)	container_of(a, struct imx_i2c_struct, adapter)
 
@@ -215,6 +224,8 @@ static int i2c_imx_start(struct i2c_adapter *adapter)
 	int result;
 
 	writeb(i2c_imx->ifdr, base + IMX_I2C_IFDR);
+	if (i2c_imx->dfsrr != -1)
+		writeb(i2c_imx->dfsrr, base + IMX_I2C_DFSRR);
 	/* Enable I2C controller */
 	writeb(0, base + IMX_I2C_I2SR);
 	writeb(I2CR_IEN, base + IMX_I2C_I2CR);
@@ -271,6 +282,76 @@ static void i2c_imx_stop(struct i2c_adapter *adapter)
 	writeb(0, base + IMX_I2C_I2CR);
 }
 
+#ifdef CONFIG_PPC
+static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
+				    unsigned int rate)
+{
+	void __iomem *base;
+	unsigned int i2c_clk;
+	unsigned short divider;
+	/*
+	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
+	 * is equal to or lower than the requested speed.  That means that we
+	 * want the first divider that is equal to or greater than the
+	 * calculated divider.
+	 */
+	u8 dfsr, fdr;
+	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
+	unsigned short a, b, ga, gb;
+	unsigned long c_div, est_div;
+
+	fdr = 0x31; /* Default if no FDR found */
+	base = i2c_imx->base;
+	i2c_clk = fsl_get_i2c_freq();
+	divider = min((unsigned short)(i2c_clk / rate), (unsigned short) -1);
+
+	/*
+	 * Condition 1: dfsr <= 50ns/T (T=period of I2C source clock in ns).
+	 * or (dfsr * T) <= 50ns.
+	 * Translate to dfsr = 5 * Frequency / 100,000,000
+	 */
+	dfsr = (5 * (i2c_clk / 1000)) / 100000;
+	dev_dbg(i2c_imx->adapter.dev,
+		"<%s> requested speed:%d, i2c_clk:%d\n", __func__,
+		rate, i2c_clk);
+	if (!dfsr)
+		dfsr = 1;
+
+	est_div = ~0;
+	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
+		for (gb = 0; gb < 8; gb++) {
+			b = 16 << gb;
+			c_div = b * (a + ((3*dfsr)/b)*2);
+			if ((c_div > divider) && (c_div < est_div)) {
+				unsigned short bin_gb, bin_ga;
+
+				est_div = c_div;
+				bin_gb = gb << 2;
+				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
+				fdr = bin_gb | bin_ga;
+				rate = i2c_clk / est_div;
+				dev_dbg(i2c_imx->adapter.dev,
+					"FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x,"
+					" a:%d, b:%d, speed:%d\n", fdr, est_div,
+					ga, gb, a, b, rate);
+				/* Condition 2 not accounted for */
+				dev_dbg(i2c_imx->adapter.dev,
+					"Tr <= %d ns\n", (b - 3 * dfsr) *
+					1000000 / (i2c_clk / 1000));
+			}
+		}
+		if (a == 20)
+			a += 2;
+		if (a == 24)
+			a += 4;
+	}
+	dev_dbg(i2c_imx->adapter.dev,
+		"divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
+	dev_dbg(i2c_imx->adapter.dev, "FDR:0x%.2x, speed:%d\n", fdr, rate);
+	i2c_imx->ifdr = fdr;
+	i2c_imx->dfsrr = dfsr;
+}
+#else
 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 			    unsigned int rate)
 {
@@ -307,6 +388,7 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 	dev_dbg(i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
 		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
 }
+#endif
 
 static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
@@ -474,6 +556,7 @@ static int __init i2c_imx_probe(struct device_d *pdev)
 	i2c_imx->adapter.nr = pdev->id;
 	i2c_imx->adapter.dev = pdev;
 	i2c_imx->base = dev_request_mem_region(pdev, 0);
+	i2c_imx->dfsrr = -1;
 
 	/* Set up clock divider */
 	if (pdata && pdata->bitrate)
-- 
1.7.1


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[PATCH 5/5] ppc: p2020rdb i2c support

[Renaud Barbier]

Support for both i2c busses on the p2020rdb board is added and the
configuration file is updated to add the I2C driver and commands.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c |   12 +++++++++++-
 arch/ppc/configs/p2020rdb_defconfig           |    3 +++
 2 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 2de6cc4..59a9d12 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -26,6 +26,7 @@
 #include <driver.h>
 #include <ns16550.h>
 #include <types.h>
+#include <i2c/i2c.h>
 #include <partition.h>
 #include <memory.h>
 #include <asm/cache.h>
@@ -62,6 +63,11 @@
 #define SYSCLK_50	50000000
 #define SYSCLK_100	100000000
 
+/* I2C busses. */
+struct i2c_platform_data i2cplat = {
+	.bitrate = 400000,
+};
+
 /* Ethernet. Use eTSEC3 */
 static struct gfar_info_struct gfar_info[] = {
 	{
@@ -71,11 +77,15 @@ static struct gfar_info_struct gfar_info[] = {
 	},
 };
 
-
 static int devices_init(void)
 {
 	add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
 
+	add_generic_device("i2c-mpc", 0, NULL, I2C1_BASE_ADDR,
+			0x100, IORESOURCE_MEM, &i2cplat);
+	add_generic_device("i2c-mpc", 1, NULL, I2C2_BASE_ADDR,
+			0x100, IORESOURCE_MEM, &i2cplat);
+
 	/* eTSEC3 */
 	fsl_eth_init(3, &gfar_info[0]);
 
diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig
index d025a40..7690327 100644
--- a/arch/ppc/configs/p2020rdb_defconfig
+++ b/arch/ppc/configs/p2020rdb_defconfig
@@ -27,3 +27,6 @@ CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_PING=y
 CONFIG_TFTP=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_CMD_I2C=y
-- 
1.7.1


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Re: [PATCH 3/5] mpc85xx: header update

[Sascha Hauer]

Hi Renaud,

On Thu, Aug 30, 2012 at 03:00:15PM +0100, Renaud Barbier wrote:
> In order to use the IMX i2c driver on the mpc85xx SOC, the file
> mach/clocks.h is renamed mach/clock.h. Files using this header are updated
> accordingly. The file mach/generic.h is also added to accommodate the driver.
> 
> Finally, there is a clean up of a line too long.

Please drop this. If you are really interested in the line wrap, you can
send a separate patch, but having this in an unrelated patch is not
good.


>  	return 0;
>  }
>  
> +
> +#define cpu_is_mx1()	(0)

Rather than adding a cpu_is_mx1() for ppc you can simply drop the code
in the i2c driver. i.MX1 is quite old, noone uses i2c on i.MX1 and it's
unlikely that someone ever will.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 4/5] i2c: adapt the i2c-imx driver to mpc85xx machines.

[Sascha Hauer]

On Thu, Aug 30, 2012 at 03:00:16PM +0100, Renaud Barbier wrote:
> A function to calculate the frequency divider and digital filter sampling rate
> for the 85xx processors is added to the i2c-imx driver. Hence, this driver is
> used on IMX and 85xx machines.
> 
>  
>  /* This will be the driver name */
> +#ifdef CONFIG_PPC
> +#define DRIVER_NAME "i2c-mpc"
> +#else
>  #define DRIVER_NAME "i2c-imx"
> +#endif

Can we run a s/imx/fsl/ over the driver in the first step?

>  
>  /* Default value */
>  #define IMX_I2C_BIT_RATE	100000	/* 100kHz */
> @@ -61,6 +66,7 @@
>  #define IMX_I2C_I2CR	0x08	/* i2c control */
>  #define IMX_I2C_I2SR	0x0C	/* i2c status */
>  #define IMX_I2C_I2DR	0x10	/* i2c transfer data */
> +#define IMX_I2C_DFSRR	0x14	/* i2c digital filter smapling rate */

s/smapling/sampling/

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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[PATCH V2 0/6 ] IMX i2c driver update for the PPC 85xx

[Renaud Barbier]

This patch set prepares the PPC 85xx SOC to use the IMX i2c driver and updates
the driver with specific clock settings. The driver name is renamed "i2c-fsl".
The patch also introduces a function returning the system clock to calculate
the i2c frequency bus divider. Finally, the P2020RDB board support is updated
to test the driver on 8-bit and 16-bit I2C devices.

This patch has NOT been tested on a IMX board.

Renaud Barbier (6):
  mpc85xx: i2c frequency
  ppc/asm/fsl_i2c.h is removed
  mpc85xx: header update
  IMX driver: replace imx -> fsl
  i2c: adapt the i2c-imx driver to mpc85xx machines
  ppc: p2020rdb i2c support

 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c      |   14 +-
 arch/ppc/configs/p2020rdb_defconfig                |    3 +
 arch/ppc/include/asm/fsl_i2c.h                     |   86 ------
 .../include/mach/{clocks.h => clock.h}             |    1 +
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h    |    3 +
 arch/ppc/mach-mpc85xx/speed.c                      |   11 +-
 arch/ppc/mach-mpc85xx/time.c                       |    2 +-
 drivers/i2c/busses/Kconfig                         |    4 +-
 drivers/i2c/busses/i2c-imx.c                       |  324 ++++++++++++--------
 9 files changed, 230 insertions(+), 218 deletions(-)
 delete mode 100644 arch/ppc/include/asm/fsl_i2c.h
 rename arch/ppc/mach-mpc85xx/include/mach/{clocks.h => clock.h} (91%)


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[PATCH 1/6] mpc85xx: i2c frequency

[Renaud Barbier]

A function that returns the system bus frequency used to compute the i2c bus
frequency is added for future use.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/mach-mpc85xx/include/mach/clocks.h |    1 +
 arch/ppc/mach-mpc85xx/speed.c               |    9 +++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
index 2ab367b..e20d685 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/clocks.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
@@ -12,5 +12,6 @@ struct sys_info {
 
 unsigned long fsl_get_bus_freq(ulong dummy);
 unsigned long fsl_get_timebase_clock(void);
+unsigned long fsl_get_i2c_freq(void);
 void fsl_get_sys_info(struct sys_info *sysInfo);
 #endif /* __ASM_ARCH_CLOCKS_H */
diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c
index 40d3664..fff2d22 100644
--- a/arch/ppc/mach-mpc85xx/speed.c
+++ b/arch/ppc/mach-mpc85xx/speed.c
@@ -102,3 +102,12 @@ unsigned long fsl_get_timebase_clock(void)
 
 	return (sysinfo.freqSystemBus + 4UL)/8UL;
 }
+
+unsigned long fsl_get_i2c_freq(void)
+{
+	struct sys_info sysinfo;
+
+	fsl_get_sys_info(&sysinfo);
+
+	return sysinfo.freqSystemBus / 2;
+}
-- 
1.7.1


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[PATCH 2/6] ppc/asm/fsl_i2c.h is removed

[Renaud Barbier]

The i2c-imx driver is able to support the I2C bus on the 85xx machines
with minor modifications. It already defines register offsets. Therefore,
this header file is no longer needed.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/include/asm/fsl_i2c.h |   86 ----------------------------------------
 1 files changed, 0 insertions(+), 86 deletions(-)
 delete mode 100644 arch/ppc/include/asm/fsl_i2c.h

diff --git a/arch/ppc/include/asm/fsl_i2c.h b/arch/ppc/include/asm/fsl_i2c.h
deleted file mode 100644
index 4f71341..0000000
--- a/arch/ppc/include/asm/fsl_i2c.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Freescale I2C Controller
- *
- * Copyright 2006 Freescale Semiconductor, Inc.
- *
- * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
- * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
- * and Jeff Brown.
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_FSL_I2C_H_
-#define _ASM_FSL_I2C_H_
-
-#include <asm/types.h>
-
-typedef struct fsl_i2c {
-
-	u8 adr;		/* I2C slave address */
-	u8 res0[3];
-#define I2C_ADR		0xFE
-#define I2C_ADR_SHIFT	1
-#define I2C_ADR_RES	~(I2C_ADR)
-
-	u8 fdr;		/* I2C frequency divider register */
-	u8 res1[3];
-#define IC2_FDR		0x3F
-#define IC2_FDR_SHIFT	0
-#define IC2_FDR_RES	~(IC2_FDR)
-
-	u8 cr;		/* I2C control redister	*/
-	u8 res2[3];
-#define I2C_CR_MEN	0x80
-#define I2C_CR_MIEN	0x40
-#define I2C_CR_MSTA	0x20
-#define I2C_CR_MTX	0x10
-#define I2C_CR_TXAK	0x08
-#define I2C_CR_RSTA	0x04
-#define I2C_CR_BCST	0x01
-
-	u8 sr;		/* I2C status register */
-	u8 res3[3];
-#define I2C_SR_MCF	0x80
-#define I2C_SR_MAAS	0x40
-#define I2C_SR_MBB	0x20
-#define I2C_SR_MAL	0x10
-#define I2C_SR_BCSTM	0x08
-#define I2C_SR_SRW	0x04
-#define I2C_SR_MIF	0x02
-#define I2C_SR_RXAK	0x01
-
-	u8 dr;		/* I2C data register */
-	u8 res4[3];
-#define I2C_DR		0xFF
-#define I2C_DR_SHIFT	0
-#define I2C_DR_RES	~(I2C_DR)
-
-	u8 dfsrr;	/* I2C digital filter sampling rate register */
-	u8 res5[3];
-#define I2C_DFSRR	0x3F
-#define I2C_DFSRR_SHIFT	0
-#define I2C_DFSRR_RES	~(I2C_DR)
-
-	/* Fill out the reserved block */
-	u8 res6[0xE8];
-} fsl_i2c_t;
-
-#endif	/* _ASM_I2C_H_ */
-- 
1.7.1


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[PATCH 3/6] mpc85xx: header update

[Renaud Barbier]

In order to use the IMX i2c driver on the mpc85xx SOC, the file mach/clocks.h
is renamed mach/clock.h. Files using this header are updated accordingly.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c      |    2 +-
 .../include/mach/{clocks.h => clock.h}             |    0
 arch/ppc/mach-mpc85xx/speed.c                      |    2 +-
 arch/ppc/mach-mpc85xx/time.c                       |    2 +-
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/ppc/mach-mpc85xx/include/mach/{clocks.h => clock.h} (100%)

diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 734fef9..23d752d 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -34,7 +34,7 @@
 #include <mach/mpc85xx.h>
 #include <mach/mmu.h>
 #include <mach/immap_85xx.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 #include <mach/gianfar.h>
 #include <mach/early_udelay.h>
 
diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clock.h
similarity index 100%
rename from arch/ppc/mach-mpc85xx/include/mach/clocks.h
rename to arch/ppc/mach-mpc85xx/include/mach/clock.h
diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c
index fff2d22..6778d57 100644
--- a/arch/ppc/mach-mpc85xx/speed.c
+++ b/arch/ppc/mach-mpc85xx/speed.c
@@ -30,7 +30,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 #include <mach/immap_85xx.h>
 #include <mach/mpc85xx.h>
 
diff --git a/arch/ppc/mach-mpc85xx/time.c b/arch/ppc/mach-mpc85xx/time.c
index 408a28a..c50591c 100644
--- a/arch/ppc/mach-mpc85xx/time.c
+++ b/arch/ppc/mach-mpc85xx/time.c
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <clock.h>
 #include <init.h>
-#include <mach/clocks.h>
+#include <mach/clock.h>
 
 uint64_t ppc_clocksource_read(void)
 {
-- 
1.7.1


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[PATCH 4/6] IMX driver: replace imx -> fsl

[Renaud Barbier]

The IMX i2c driver is to be used by SOCs on both the ARM and PPC architetures.
Use a more neutral name for the structure, function names and #define.
The driver name is now "i2c-fsl".

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 drivers/i2c/busses/i2c-imx.c |  235 +++++++++++++++++++++---------------------
 1 files changed, 118 insertions(+), 117 deletions(-)

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index da6218f..8bbe87b 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2012 GE Intelligent Platforms, Inc
  * Copyright (C) 2002 Motorola GSG-China
  *               2009 Marc Kleine-Budde, Pengutronix
  *
@@ -50,19 +51,19 @@
 #include <mach/clock.h>
 
 /* This will be the driver name */
-#define DRIVER_NAME "i2c-imx"
+#define DRIVER_NAME "i2c-fsl"
 
 /* Default value */
-#define IMX_I2C_BIT_RATE	100000	/* 100kHz */
+#define FSL_I2C_BIT_RATE	100000	/* 100kHz */
 
-/* IMX I2C registers */
-#define IMX_I2C_IADR	0x00	/* i2c slave address */
-#define IMX_I2C_IFDR	0x04	/* i2c frequency divider */
-#define IMX_I2C_I2CR	0x08	/* i2c control */
-#define IMX_I2C_I2SR	0x0C	/* i2c status */
-#define IMX_I2C_I2DR	0x10	/* i2c transfer data */
+/* FSL I2C registers */
+#define FSL_I2C_IADR	0x00	/* i2c slave address */
+#define FSL_I2C_IFDR	0x04	/* i2c frequency divider */
+#define FSL_I2C_I2CR	0x08	/* i2c control */
+#define FSL_I2C_I2SR	0x0C	/* i2c status */
+#define FSL_I2C_I2DR	0x10	/* i2c transfer data */
 
-/* Bits of IMX I2C registers */
+/* Bits of FSL I2C registers */
 #define I2SR_RXAK	0x01
 #define I2SR_IIF	0x02
 #define I2SR_SRW	0x04
@@ -101,23 +102,23 @@ static u16 i2c_clk_div[50][2] = {
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
 
-struct imx_i2c_struct {
+struct fsl_i2c_struct {
 	void __iomem		*base;
 	struct i2c_adapter	adapter;
 	unsigned int 		disable_delay;
 	int			stopped;
-	unsigned int		ifdr;	/* IMX_I2C_IFDR */
+	unsigned int		ifdr;	/* FSL_I2C_IFDR */
 };
-#define to_imx_i2c_struct(a)	container_of(a, struct imx_i2c_struct, adapter)
+#define to_fsl_i2c_struct(a)	container_of(a, struct fsl_i2c_struct, adapter)
 
 #ifdef CONFIG_I2C_DEBUG
-static void i2c_imx_dump_reg(struct i2c_adapter *adapter)
+static void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
 	u32 reg_cr, reg_sr;
 
-	reg_cr = readb(i2c_imx->base + IMX_I2C_I2CR);
-	reg_sr = readb(i2c_imx->base + IMX_I2C_I2SR);
+	reg_cr = readb(i2c_fsl->base + FSL_I2C_I2CR);
+	reg_sr = readb(i2c_fsl->base + FSL_I2C_I2SR);
 
 	dev_dbg(adapter->dev, "CONTROL:\t"
 		"IEN =%d, IIEN=%d, MSTA=%d, MTX =%d, TXAK=%d, RSTA=%d\n",
@@ -133,22 +134,22 @@ static void i2c_imx_dump_reg(struct i2c_adapter *adapter)
 		(reg_sr & I2SR_RXAK ? 1 : 0));
 }
 #else
-static inline void i2c_imx_dump_reg(struct i2c_adapter *adapter)
+static inline void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
 {
 	return;
 }
 #endif
 
-static int i2c_imx_bus_busy(struct i2c_adapter *adapter, int for_busy)
+static int i2c_fsl_bus_busy(struct i2c_adapter *adapter, int for_busy)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 	unsigned int temp;
 
 	start = get_time_ns();
 	while (1) {
-		temp = readb(base + IMX_I2C_I2SR);
+		temp = readb(base + FSL_I2C_I2SR);
 		if (for_busy && (temp & I2SR_IBB))
 			break;
 		if (!for_busy && !(temp & I2SR_IBB))
@@ -164,15 +165,15 @@ static int i2c_imx_bus_busy(struct i2c_adapter *adapter, int for_busy)
 	return 0;
 }
 
-static int i2c_imx_trx_complete(struct i2c_adapter *adapter)
+static int i2c_fsl_trx_complete(struct i2c_adapter *adapter)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 
 	start = get_time_ns();
 	while (1) {
-		unsigned int reg = readb(base + IMX_I2C_I2SR);
+		unsigned int reg = readb(base + FSL_I2C_I2SR);
 		if (reg & I2SR_IIF)
 			break;
 
@@ -181,20 +182,20 @@ static int i2c_imx_trx_complete(struct i2c_adapter *adapter)
 			return -EIO;
 		}
 	}
-	writeb(0, base + IMX_I2C_I2SR);
+	writeb(0, base + FSL_I2C_I2SR);
 
 	return 0;
 }
 
-static int i2c_imx_acked(struct i2c_adapter *adapter)
+static int i2c_fsl_acked(struct i2c_adapter *adapter)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 
 	start = get_time_ns();
 	while (1) {
-		unsigned int reg = readb(base + IMX_I2C_I2SR);
+		unsigned int reg = readb(base + FSL_I2C_I2SR);
 		if (!(reg & I2SR_RXAK))
 			break;
 
@@ -207,71 +208,71 @@ static int i2c_imx_acked(struct i2c_adapter *adapter)
 	return 0;
 }
 
-static int i2c_imx_start(struct i2c_adapter *adapter)
+static int i2c_fsl_start(struct i2c_adapter *adapter)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	unsigned int temp = 0;
 	int result;
 
-	writeb(i2c_imx->ifdr, base + IMX_I2C_IFDR);
+	writeb(i2c_fsl->ifdr, base + FSL_I2C_IFDR);
 	/* Enable I2C controller */
-	writeb(0, base + IMX_I2C_I2SR);
-	writeb(I2CR_IEN, base + IMX_I2C_I2CR);
+	writeb(0, base + FSL_I2C_I2SR);
+	writeb(I2CR_IEN, base + FSL_I2C_I2CR);
 
 	/* Wait controller to be stable */
 	udelay(100);
 
 	/* Start I2C transaction */
-	temp = readb(base + IMX_I2C_I2CR);
+	temp = readb(base + FSL_I2C_I2CR);
 	temp |= I2CR_MSTA;
-	writeb(temp, base + IMX_I2C_I2CR);
+	writeb(temp, base + FSL_I2C_I2CR);
 
-	result = i2c_imx_bus_busy(adapter, 1);
+	result = i2c_fsl_bus_busy(adapter, 1);
 	if (result)
 		return result;
 
-	i2c_imx->stopped = 0;
+	i2c_fsl->stopped = 0;
 
 	temp |= I2CR_MTX | I2CR_TXAK;
-	writeb(temp, base + IMX_I2C_I2CR);
+	writeb(temp, base + FSL_I2C_I2CR);
 
 	return result;
 }
 
-static void i2c_imx_stop(struct i2c_adapter *adapter)
+static void i2c_fsl_stop(struct i2c_adapter *adapter)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	unsigned int temp = 0;
 
-	if (!i2c_imx->stopped) {
+	if (!i2c_fsl->stopped) {
 		/* Stop I2C transaction */
-		temp = readb(base + IMX_I2C_I2CR);
+		temp = readb(base + FSL_I2C_I2CR);
 		temp &= ~(I2CR_MSTA | I2CR_MTX);
-		writeb(temp, base + IMX_I2C_I2CR);
+		writeb(temp, base + FSL_I2C_I2CR);
 		/* wait for the stop condition to be send, otherwise the i2c
 		 * controller is disabled before the STOP is sent completely */
-		i2c_imx->stopped = i2c_imx_bus_busy(adapter, 0) ? 0 : 1;
+		i2c_fsl->stopped = i2c_fsl_bus_busy(adapter, 0) ? 0 : 1;
 	}
 	if (cpu_is_mx1()) {
 		/*
 		 * This delay caused by an i.MXL hardware bug.
 		 * If no (or too short) delay, no "STOP" bit will be generated.
 		 */
-		udelay(i2c_imx->disable_delay);
+		udelay(i2c_fsl->disable_delay);
 	}
 
-	if (!i2c_imx->stopped) {
-		i2c_imx_bus_busy(adapter, 0);
-		i2c_imx->stopped = 1;
+	if (!i2c_fsl->stopped) {
+		i2c_fsl_bus_busy(adapter, 0);
+		i2c_fsl->stopped = 1;
 	}
 
 	/* Disable I2C controller, and force our state to stopped */
-	writeb(0, base + IMX_I2C_I2CR);
+	writeb(0, base + FSL_I2C_I2CR);
 }
 
-static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
+static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 			    unsigned int rate)
 {
 	unsigned int i2c_clk_rate;
@@ -279,7 +280,7 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 	int i;
 
 	/* Divider value calculation */
-	i2c_clk_rate = imx_get_i2cclk();
+	i2c_clk_rate = fsl_get_i2cclk();
 	div = (i2c_clk_rate + rate - 1) / rate;
 	if (div < i2c_clk_div[0][0])
 		i = 0;
@@ -290,7 +291,7 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 			;
 
 	/* Store divider value */
-	i2c_imx->ifdr = i2c_clk_div[i][1];
+	i2c_fsl->ifdr = i2c_clk_div[i][1];
 
 	/*
 	 * There dummy delay is calculated.
@@ -298,20 +299,20 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 	 * This delay is used in I2C bus disable function
 	 * to fix chip hardware bug.
 	 */
-	i2c_imx->disable_delay =
+	i2c_fsl->disable_delay =
 		(500000U * i2c_clk_div[i][0] + (i2c_clk_rate / 2) - 1) /
 		(i2c_clk_rate / 2);
 
-	dev_dbg(i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
+	dev_dbg(i2c_fsl->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
 		__func__, i2c_clk_rate, div);
-	dev_dbg(i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
+	dev_dbg(i2c_fsl->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
 		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
 }
 
-static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
+static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	int i, result;
 
 	if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
@@ -320,12 +321,12 @@ static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			__func__, msgs->addr << 1);
 
 		/* write slave address */
-		writeb(msgs->addr << 1, base + IMX_I2C_I2DR);
+		writeb(msgs->addr << 1, base + FSL_I2C_I2DR);
 
-		result = i2c_imx_trx_complete(adapter);
+		result = i2c_fsl_trx_complete(adapter);
 		if (result)
 			return result;
-		result = i2c_imx_acked(adapter);
+		result = i2c_fsl_acked(adapter);
 		if (result)
 			return result;
 	}
@@ -335,27 +336,27 @@ static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 		dev_dbg(adapter->dev,
 			"<%s> write byte: B%d=0x%02X\n",
 			__func__, i, msgs->buf[i]);
-		writeb(msgs->buf[i], base + IMX_I2C_I2DR);
+		writeb(msgs->buf[i], base + FSL_I2C_I2DR);
 
-		result = i2c_imx_trx_complete(adapter);
+		result = i2c_fsl_trx_complete(adapter);
 		if (result)
 			return result;
-		result = i2c_imx_acked(adapter);
+		result = i2c_fsl_acked(adapter);
 		if (result)
 			return result;
 	}
 	return 0;
 }
 
-static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
+static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	int i, result;
 	unsigned int temp;
 
 	/* clear IIF */
-	writeb(0x0, base + IMX_I2C_I2SR);
+	writeb(0x0, base + FSL_I2C_I2SR);
 
 	if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
 		dev_dbg(adapter->dev,
@@ -363,28 +364,28 @@ static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			__func__, (msgs->addr << 1) | 0x01);
 
 		/* write slave address */
-		writeb((msgs->addr << 1) | 0x01, base + IMX_I2C_I2DR);
+		writeb((msgs->addr << 1) | 0x01, base + FSL_I2C_I2DR);
 
-		result = i2c_imx_trx_complete(adapter);
+		result = i2c_fsl_trx_complete(adapter);
 		if (result)
 			return result;
-		result = i2c_imx_acked(adapter);
+		result = i2c_fsl_acked(adapter);
 		if (result)
 			return result;
 	}
 
 	/* setup bus to read data */
-	temp = readb(base + IMX_I2C_I2CR);
+	temp = readb(base + FSL_I2C_I2CR);
 	temp &= ~I2CR_MTX;
 	if (msgs->len - 1)
 		temp &= ~I2CR_TXAK;
-	writeb(temp, base + IMX_I2C_I2CR);
+	writeb(temp, base + FSL_I2C_I2CR);
 
-	readb(base + IMX_I2C_I2DR);	/* dummy read */
+	readb(base + FSL_I2C_I2DR);	/* dummy read */
 
 	/* read data */
 	for (i = 0; i < msgs->len; i++) {
-		result = i2c_imx_trx_complete(adapter);
+		result = i2c_fsl_trx_complete(adapter);
 		if (result)
 			return result;
 
@@ -393,23 +394,23 @@ static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			 * It must generate STOP before read I2DR to prevent
 			 * controller from generating another clock cycle
 			 */
-			temp = readb(base + IMX_I2C_I2CR);
+			temp = readb(base + FSL_I2C_I2CR);
 			temp &= ~(I2CR_MSTA | I2CR_MTX);
-			writeb(temp, base + IMX_I2C_I2CR);
+			writeb(temp, base + FSL_I2C_I2CR);
 
 			/*
 			 * adding this delay helps on low bitrates
 			 */
-			udelay(i2c_imx->disable_delay);
+			udelay(i2c_fsl->disable_delay);
 
-			i2c_imx_bus_busy(adapter, 0);
-			i2c_imx->stopped = 1;
+			i2c_fsl_bus_busy(adapter, 0);
+			i2c_fsl->stopped = 1;
 		} else if (i == (msgs->len - 2)) {
-			temp = readb(base + IMX_I2C_I2CR);
+			temp = readb(base + FSL_I2C_I2CR);
 			temp |= I2CR_TXAK;
-			writeb(temp, base + IMX_I2C_I2CR);
+			writeb(temp, base + FSL_I2C_I2CR);
 		}
-		msgs->buf[i] = readb(base + IMX_I2C_I2DR);
+		msgs->buf[i] = readb(base + FSL_I2C_I2DR);
 
 		dev_dbg(adapter->dev, "<%s> read byte: B%d=0x%02X\n",
 			__func__, i, msgs->buf[i]);
@@ -417,76 +418,76 @@ static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 	return 0;
 }
 
-static int i2c_imx_xfer(struct i2c_adapter *adapter,
+static int i2c_fsl_xfer(struct i2c_adapter *adapter,
 			struct i2c_msg *msgs, int num)
 {
-	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	void __iomem *base = i2c_imx->base;
+	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
+	void __iomem *base = i2c_fsl->base;
 	unsigned int i, temp;
 	int result;
 
 	/* Start I2C transfer */
-	result = i2c_imx_start(adapter);
+	result = i2c_fsl_start(adapter);
 	if (result)
 		goto fail0;
 
 	/* read/write data */
 	for (i = 0; i < num; i++) {
 		if (i && !(msgs[i].flags & I2C_M_DATA_ONLY)) {
-			temp = readb(base + IMX_I2C_I2CR);
+			temp = readb(base + FSL_I2C_I2CR);
 			temp |= I2CR_RSTA;
-			writeb(temp, base + IMX_I2C_I2CR);
+			writeb(temp, base + FSL_I2C_I2CR);
 
-			result = i2c_imx_bus_busy(adapter, 1);
+			result = i2c_fsl_bus_busy(adapter, 1);
 			if (result)
 				goto fail0;
 		}
-		i2c_imx_dump_reg(adapter);
+		i2c_fsl_dump_reg(adapter);
 
 		/* write/read data */
 		if (msgs[i].flags & I2C_M_RD)
-			result = i2c_imx_read(adapter, &msgs[i]);
+			result = i2c_fsl_read(adapter, &msgs[i]);
 		else
-			result = i2c_imx_write(adapter, &msgs[i]);
+			result = i2c_fsl_write(adapter, &msgs[i]);
 		if (result)
 			goto fail0;
 	}
 
 fail0:
 	/* Stop I2C transfer */
-	i2c_imx_stop(adapter);
+	i2c_fsl_stop(adapter);
 
 	return (result < 0) ? result : num;
 }
 
-static int __init i2c_imx_probe(struct device_d *pdev)
+static int __init i2c_fsl_probe(struct device_d *pdev)
 {
-	struct imx_i2c_struct *i2c_imx;
+	struct fsl_i2c_struct *i2c_fsl;
 	struct i2c_platform_data *pdata;
 	int ret;
 
 	pdata = pdev->platform_data;
 
-	i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
+	i2c_fsl = kzalloc(sizeof(struct fsl_i2c_struct), GFP_KERNEL);
 
-	/* Setup i2c_imx driver structure */
-	i2c_imx->adapter.master_xfer = i2c_imx_xfer;
-	i2c_imx->adapter.nr = pdev->id;
-	i2c_imx->adapter.dev = pdev;
-	i2c_imx->base = dev_request_mem_region(pdev, 0);
+	/* Setup i2c_fsl driver structure */
+	i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
+	i2c_fsl->adapter.nr = pdev->id;
+	i2c_fsl->adapter.dev = pdev;
+	i2c_fsl->base = dev_request_mem_region(pdev, 0);
 
 	/* Set up clock divider */
 	if (pdata && pdata->bitrate)
-		i2c_imx_set_clk(i2c_imx, pdata->bitrate);
+		i2c_fsl_set_clk(i2c_fsl, pdata->bitrate);
 	else
-		i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
+		i2c_fsl_set_clk(i2c_fsl, FSL_I2C_BIT_RATE);
 
 	/* Set up chip registers to defaults */
-	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
-	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
+	writeb(0, i2c_fsl->base + FSL_I2C_I2CR);
+	writeb(0, i2c_fsl->base + FSL_I2C_I2SR);
 
 	/* Add I2C adapter */
-	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
+	ret = i2c_add_numbered_adapter(&i2c_fsl->adapter);
 	if (ret < 0) {
 		dev_err(pdev, "registration failed\n");
 		goto fail;
@@ -495,17 +496,17 @@ static int __init i2c_imx_probe(struct device_d *pdev)
 	return 0;
 
 fail:
-	kfree(i2c_imx);
+	kfree(i2c_fsl);
 	return ret;
 }
 
-static struct driver_d i2c_imx_driver = {
-	.probe	= i2c_imx_probe,
+static struct driver_d i2c_fsl_driver = {
+	.probe	= i2c_fsl_probe,
 	.name	= DRIVER_NAME,
 };
 
-static int __init i2c_adap_imx_init(void)
+static int __init i2c_adap_fsl_init(void)
 {
-	return register_driver(&i2c_imx_driver);
+	return register_driver(&i2c_fsl_driver);
 }
-device_initcall(i2c_adap_imx_init);
+device_initcall(i2c_adap_fsl_init);
-- 
1.7.1


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[PATCH 5/6] i2c: adapt the i2c-imx driver to mpc85xx machines

[Renaud Barbier]

A function to calculate the frequency divider and digital filter sampling rate
for the 85xx processors is added to the i2c-imx driver. Hence, this driver is
usable on IMX and 85xx machines.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h |    3 +
 drivers/i2c/busses/Kconfig                      |    4 +-
 drivers/i2c/busses/i2c-imx.c                    |   91 ++++++++++++++++++++---
 3 files changed, 86 insertions(+), 12 deletions(-)

diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
index bf0f7f5..d2f8bbe 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
@@ -136,4 +136,7 @@
 
 #define GFAR_BASE_ADDR		(CFG_IMMR + TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CFG_IMMR + 0x24000)
+
+#define I2C1_BASE_ADDR		(CFG_IMMR + 0x3000)
+#define I2C2_BASE_ADDR		(CFG_IMMR + 0x3100)
 #endif /*__IMMAP_85xx__*/
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 1ce5c00..3f998ea 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -5,8 +5,8 @@
 menu "I2C Hardware Bus support"
 
 config I2C_IMX
-	bool "i.MX I2C Master driver"
-	depends on ARCH_IMX && !ARCH_IMX1
+	bool "MPC85xx/i.MX I2C Master driver"
+	depends on (ARCH_IMX && !ARCH_IMX1) || ARCH_MPC85XX
 
 config I2C_OMAP
 	bool "OMAP I2C Master driver"
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 8bbe87b..6018204 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -23,7 +23,8 @@
  *
  * Desc.:
  *  Implementation of I2C Adapter/Algorithm Driver
- *  for I2C Bus integrated in Freescale i.MX/MXC processors
+ *  for I2C Bus integrated in Freescale i.MX/MXC processors and
+ *  85xx processors.
  *
  * Derived from Motorola GSG China I2C example driver
  *
@@ -37,7 +38,6 @@
 #include <clock.h>
 #include <common.h>
 #include <driver.h>
-#include <gpio.h>
 #include <init.h>
 #include <malloc.h>
 #include <types.h>
@@ -47,7 +47,6 @@
 
 #include <io.h>
 #include <i2c/i2c.h>
-#include <mach/generic.h>
 #include <mach/clock.h>
 
 /* This will be the driver name */
@@ -62,6 +61,7 @@
 #define FSL_I2C_I2CR	0x08	/* i2c control */
 #define FSL_I2C_I2SR	0x0C	/* i2c status */
 #define FSL_I2C_I2DR	0x10	/* i2c transfer data */
+#define FSL_I2C_DFSRR	0x14	/* i2c digital filter sampling rate */
 
 /* Bits of FSL I2C registers */
 #define I2SR_RXAK	0x01
@@ -86,6 +86,7 @@
  *
  * Duplicated divider values removed from list
  */
+#ifndef CONFIG_PPC
 static u16 i2c_clk_div[50][2] = {
 	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
 	{ 30,	0x00 },	{ 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
@@ -101,6 +102,7 @@ static u16 i2c_clk_div[50][2] = {
 	{ 1920,	0x1B },	{ 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
+#endif
 
 struct fsl_i2c_struct {
 	void __iomem		*base;
@@ -108,6 +110,7 @@ struct fsl_i2c_struct {
 	unsigned int 		disable_delay;
 	int			stopped;
 	unsigned int		ifdr;	/* FSL_I2C_IFDR */
+	unsigned int		dfsrr;  /* FSL_I2C_DFSRR */
 };
 #define to_fsl_i2c_struct(a)	container_of(a, struct fsl_i2c_struct, adapter)
 
@@ -216,6 +219,9 @@ static int i2c_fsl_start(struct i2c_adapter *adapter)
 	int result;
 
 	writeb(i2c_fsl->ifdr, base + FSL_I2C_IFDR);
+	if (i2c_fsl->dfsrr != -1)
+		writeb(i2c_fsl->dfsrr, base + FSL_I2C_DFSRR);
+
 	/* Enable I2C controller */
 	writeb(0, base + FSL_I2C_I2SR);
 	writeb(I2CR_IEN, base + FSL_I2C_I2CR);
@@ -255,13 +261,6 @@ static void i2c_fsl_stop(struct i2c_adapter *adapter)
 		 * controller is disabled before the STOP is sent completely */
 		i2c_fsl->stopped = i2c_fsl_bus_busy(adapter, 0) ? 0 : 1;
 	}
-	if (cpu_is_mx1()) {
-		/*
-		 * This delay caused by an i.MXL hardware bug.
-		 * If no (or too short) delay, no "STOP" bit will be generated.
-		 */
-		udelay(i2c_fsl->disable_delay);
-	}
 
 	if (!i2c_fsl->stopped) {
 		i2c_fsl_bus_busy(adapter, 0);
@@ -272,6 +271,76 @@ static void i2c_fsl_stop(struct i2c_adapter *adapter)
 	writeb(0, base + FSL_I2C_I2CR);
 }
 
+#ifdef CONFIG_PPC
+static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
+				    unsigned int rate)
+{
+	void __iomem *base;
+	unsigned int i2c_clk;
+	unsigned short divider;
+	/*
+	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
+	 * is equal to or lower than the requested speed.  That means that we
+	 * want the first divider that is equal to or greater than the
+	 * calculated divider.
+	 */
+	u8 dfsr, fdr;
+	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
+	unsigned short a, b, ga, gb;
+	unsigned long c_div, est_div;
+
+	fdr = 0x31; /* Default if no FDR found */
+	base = i2c_fsl->base;
+	i2c_clk = fsl_get_i2c_freq();
+	divider = min((unsigned short)(i2c_clk / rate), (unsigned short) -1);
+
+	/*
+	 * Condition 1: dfsr <= 50ns/T (T=period of I2C source clock in ns).
+	 * or (dfsr * T) <= 50ns.
+	 * Translate to dfsr = 5 * Frequency / 100,000,000
+	 */
+	dfsr = (5 * (i2c_clk / 1000)) / 100000;
+	dev_dbg(i2c_fsl->adapter.dev,
+		"<%s> requested speed:%d, i2c_clk:%d\n", __func__,
+		rate, i2c_clk);
+	if (!dfsr)
+		dfsr = 1;
+
+	est_div = ~0;
+	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
+		for (gb = 0; gb < 8; gb++) {
+			b = 16 << gb;
+			c_div = b * (a + ((3*dfsr)/b)*2);
+			if ((c_div > divider) && (c_div < est_div)) {
+				unsigned short bin_gb, bin_ga;
+
+				est_div = c_div;
+				bin_gb = gb << 2;
+				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
+				fdr = bin_gb | bin_ga;
+				rate = i2c_clk / est_div;
+				dev_dbg(i2c_fsl->adapter.dev,
+					"FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x,"
+					" a:%d, b:%d, speed:%d\n", fdr, est_div,
+					ga, gb, a, b, rate);
+				/* Condition 2 not accounted for */
+				dev_dbg(i2c_fsl->adapter.dev,
+					"Tr <= %d ns\n", (b - 3 * dfsr) *
+					1000000 / (i2c_clk / 1000));
+			}
+		}
+		if (a == 20)
+			a += 2;
+		if (a == 24)
+			a += 4;
+	}
+	dev_dbg(i2c_fsl->adapter.dev,
+		"divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
+	dev_dbg(i2c_fsl->adapter.dev, "FDR:0x%.2x, speed:%d\n", fdr, rate);
+	i2c_fsl->ifdr = fdr;
+	i2c_fsl->dfsrr = dfsr;
+}
+#else
 static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 			    unsigned int rate)
 {
@@ -308,6 +377,7 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 	dev_dbg(i2c_fsl->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
 		__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
 }
+#endif
 
 static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
@@ -475,6 +545,7 @@ static int __init i2c_fsl_probe(struct device_d *pdev)
 	i2c_fsl->adapter.nr = pdev->id;
 	i2c_fsl->adapter.dev = pdev;
 	i2c_fsl->base = dev_request_mem_region(pdev, 0);
+	i2c_fsl->dfsrr = -1;
 
 	/* Set up clock divider */
 	if (pdata && pdata->bitrate)
-- 
1.7.1


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[PATCH 6/6] ppc: p2020rdb i2c support

[Renaud Barbier]

Support for both i2c busses on the p2020rdb board is added and the
configuration file is updated to add the I2C driver and commands.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c |   12 +++++++++++-
 arch/ppc/configs/p2020rdb_defconfig           |    3 +++
 2 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 23d752d..94b5935 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -26,6 +26,7 @@
 #include <driver.h>
 #include <ns16550.h>
 #include <types.h>
+#include <i2c/i2c.h>
 #include <partition.h>
 #include <memory.h>
 #include <asm/cache.h>
@@ -62,6 +63,11 @@
 #define SYSCLK_50	50000000
 #define SYSCLK_100	100000000
 
+/* I2C busses. */
+struct i2c_platform_data i2cplat = {
+	.bitrate = 400000,
+};
+
 /* Ethernet. Use eTSEC3 */
 static struct gfar_info_struct gfar_info[] = {
 	{
@@ -71,11 +77,15 @@ static struct gfar_info_struct gfar_info[] = {
 	},
 };
 
-
 static int devices_init(void)
 {
 	add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
 
+	add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR,
+			0x100, IORESOURCE_MEM, &i2cplat);
+	add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
+			0x100, IORESOURCE_MEM, &i2cplat);
+
 	/* eTSEC3 */
 	fsl_eth_init(3, &gfar_info[0]);
 
diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig
index d025a40..7690327 100644
--- a/arch/ppc/configs/p2020rdb_defconfig
+++ b/arch/ppc/configs/p2020rdb_defconfig
@@ -27,3 +27,6 @@ CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_PING=y
 CONFIG_TFTP=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_CMD_I2C=y
-- 
1.7.1


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Re: [PATCH V2 0/6 ] IMX i2c driver update for the PPC 85xx

[Sascha Hauer]

On Fri, Aug 31, 2012 at 03:10:29PM +0100, Renaud Barbier wrote:
> This patch set prepares the PPC 85xx SOC to use the IMX i2c driver and updates
> the driver with specific clock settings. The driver name is renamed "i2c-fsl".
> The patch also introduces a function returning the system clock to calculate
> the i2c frequency bus divider. Finally, the P2020RDB board support is updated
> to test the driver on 8-bit and 16-bit I2C devices.
> 
> This patch has NOT been tested on a IMX board.

Applied, thanks.

I added the missing conversion of the device name from i2c-imx to
i2c-fsl to the i.MX SoC part.

Sascha


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