[PATCH] pbl updates

[PATCH] pbl updates

[Sascha Hauer]

Here are two updates for the MMU code in the decompressor. The first
one may come in handy when a JTAG debugger is connected. The second
one is more important. It actually makes turning on the MMU in the
decompressor useful by making map_cachable work. It turned out that
this didn't work leaving the whole mapping uncached.
Note that the code in current master should work, but slow. Since
it actually does work I do not want to put this into the upcoming
release.

Sascha

----------------------------------------------------------------
Sascha Hauer (2):
      ARM pbl: Provide a dummy error function for the decompressor
      ARM pbl: actually create cached mappings in the decompressor

 arch/arm/cpu/start-pbl.c |   14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

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[PATCH 1/2] ARM pbl: Provide a dummy error function for the decompressor

[Sascha Hauer]

We can't do anything useful in the error function, so we just hang.
This has the advantage that at least when a JTAG debugger is connected
we can see what happens. Otherwise the code just jumps to NULL in case
of an error.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/start-pbl.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 932a3da..2cd33ce 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -113,6 +113,11 @@ static void mmu_disable(void)
 	__mmu_cache_off();
 }
 
+void noinline errorfn(char *error)
+{
+	while (1);
+}
+
 static void barebox_uncompress(void *compressed_start, unsigned int len)
 {
 	void (*barebox)(void);
@@ -135,7 +140,7 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
 	decompress((void *)compressed_start,
 			len,
 			NULL, NULL,
-			(void *)TEXT_BASE, NULL, NULL);
+			(void *)TEXT_BASE, NULL, errorfn);
 
 	if (use_mmu)
 		mmu_disable();
-- 
1.7.10.4


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[PATCH 2/2] ARM pbl: actually create cached mappings in the decompressor

[Sascha Hauer]

We called create_sections with 4096MB as size argument, but create_sections
expected the argument in bytes, so create sections was completely optimized
away due to the size >>= 20. This patch changes the size argument to be in
megabytes and adjusts map_cachable to pass the argument in megabytes.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/start-pbl.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 2cd33ce..1626eb3 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -56,14 +56,13 @@ extern void *input_data_end;
 
 static unsigned long *ttb;
 
-static void create_sections(unsigned long addr, int size, unsigned int flags)
+static void create_sections(unsigned long addr, int size_m, unsigned int flags)
 {
 	int i;
 
 	addr >>= 20;
-	size >>= 20;
 
-	for (i = size; i > 0; i--, addr++)
+	for (i = size_m; i > 0; i--, addr++)
 		ttb[addr] = (addr << 20) | flags;
 }
 
@@ -72,7 +71,7 @@ static void map_cachable(unsigned long start, unsigned long size)
 	start &= ~(SZ_1M - 1);
 	size = (size + (SZ_1M - 1)) & ~(SZ_1M - 1);
 
-	create_sections(start, size, PMD_SECT_AP_WRITE |
+	create_sections(start, size >> 20, PMD_SECT_AP_WRITE |
 			PMD_SECT_AP_READ | PMD_TYPE_SECT | PMD_SECT_WB);
 }
 
-- 
1.7.10.4


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Re: [PATCH] pbl updates

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:06 Tue 02 Oct     , Sascha Hauer wrote:
> Here are two updates for the MMU code in the decompressor. The first
> one may come in handy when a JTAG debugger is connected. The second
> one is more important. It actually makes turning on the MMU in the
> decompressor useful by making map_cachable work. It turned out that
> this didn't work leaving the whole mapping uncached.
> Note that the code in current master should work, but slow. Since
> it actually does work I do not want to put this into the upcoming
> release.
As I report the current code does not work on at91sam9g45
I suspect as we boot from the second ram controler on this SoC

So please hold the release that I can try those patch on sam9g45 if they fix
the PBL they will be mandatory for it

Best Regards,
J.

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Re: [PATCH] pbl updates

[Sascha Hauer]

On Tue, Oct 02, 2012 at 04:30:11PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:06 Tue 02 Oct     , Sascha Hauer wrote:
> > Here are two updates for the MMU code in the decompressor. The first
> > one may come in handy when a JTAG debugger is connected. The second
> > one is more important. It actually makes turning on the MMU in the
> > decompressor useful by making map_cachable work. It turned out that
> > this didn't work leaving the whole mapping uncached.
> > Note that the code in current master should work, but slow. Since
> > it actually does work I do not want to put this into the upcoming
> > release.
> As I report the current code does not work on at91sam9g45
> I suspect as we boot from the second ram controler on this SoC
> 
> So please hold the release that I can try those patch on sam9g45 if they fix
> the PBL they will be mandatory for it

I think they won't fix it. map_cachable currently is a noop, but this
should be fine as now we have a complete 1:1 uncached mapping. I don't
see why this shouldn't work. I hope you find out.

What we can do for now is to add an additional Kconfig option to make
enabling the MMU in the pbl optional. Then at least it should work on
your boards.

BTW I hunted down a strange problem with the MMU on a KaRO Tx53 board.
It turned out that the image header (which basically is a poke table
to initialize the SDRAM) indeed initialized the SDRAM. The problem was
that this SDRAM setup depends on some other lowlevel setup which is done
later. The SDRAM setup was good enough to load with MMU disabled, but
once the MMU is enabled the SDRAM does burst accesses and the board goes
to nirvana.
Maybe your problem is related somehow.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH] pbl updates

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:50 Tue 02 Oct     , Sascha Hauer wrote:
> On Tue, Oct 02, 2012 at 04:30:11PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:06 Tue 02 Oct     , Sascha Hauer wrote:
> > > Here are two updates for the MMU code in the decompressor. The first
> > > one may come in handy when a JTAG debugger is connected. The second
> > > one is more important. It actually makes turning on the MMU in the
> > > decompressor useful by making map_cachable work. It turned out that
> > > this didn't work leaving the whole mapping uncached.
> > > Note that the code in current master should work, but slow. Since
> > > it actually does work I do not want to put this into the upcoming
> > > release.
> > As I report the current code does not work on at91sam9g45
> > I suspect as we boot from the second ram controler on this SoC
> > 
> > So please hold the release that I can try those patch on sam9g45 if they fix
> > the PBL they will be mandatory for it
> 
> I think they won't fix it. map_cachable currently is a noop, but this
> should be fine as now we have a complete 1:1 uncached mapping. I don't
> see why this shouldn't work. I hope you find out.
> 
> What we can do for now is to add an additional Kconfig option to make
> enabling the MMU in the pbl optional. Then at least it should work on
> your boards.
Was thinking about this too
> 
> BTW I hunted down a strange problem with the MMU on a KaRO Tx53 board.
> It turned out that the image header (which basically is a poke table
> to initialize the SDRAM) indeed initialized the SDRAM. The problem was
> that this SDRAM setup depends on some other lowlevel setup which is done
> later. The SDRAM setup was good enough to load with MMU disabled, but
> once the MMU is enabled the SDRAM does burst accesses and the board goes
> to nirvana.
> Maybe your problem is related somehow.
yeah It may solve my issue with the MMU and nand boot

I was thinking to add a initcall support to the pbl and enable the MMU at the
right momment. This will allow to simplify the adding of generic SPL framework

Best Regards,
J.

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Re: [PATCH] pbl updates

[Sascha Hauer]

On Tue, Oct 02, 2012 at 08:36:41PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:50 Tue 02 Oct     , Sascha Hauer wrote:
> > On Tue, Oct 02, 2012 at 04:30:11PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 15:06 Tue 02 Oct     , Sascha Hauer wrote:
> > > > Here are two updates for the MMU code in the decompressor. The first
> > > > one may come in handy when a JTAG debugger is connected. The second
> > > > one is more important. It actually makes turning on the MMU in the
> > > > decompressor useful by making map_cachable work. It turned out that
> > > > this didn't work leaving the whole mapping uncached.
> > > > Note that the code in current master should work, but slow. Since
> > > > it actually does work I do not want to put this into the upcoming
> > > > release.
> > > As I report the current code does not work on at91sam9g45
> > > I suspect as we boot from the second ram controler on this SoC
> > > 
> > > So please hold the release that I can try those patch on sam9g45 if they fix
> > > the PBL they will be mandatory for it
> > 
> > I think they won't fix it. map_cachable currently is a noop, but this
> > should be fine as now we have a complete 1:1 uncached mapping. I don't
> > see why this shouldn't work. I hope you find out.
> > 
> > What we can do for now is to add an additional Kconfig option to make
> > enabling the MMU in the pbl optional. Then at least it should work on
> > your boards.
> Was thinking about this too

Ok, I'll prepare a patch.

> > 
> > BTW I hunted down a strange problem with the MMU on a KaRO Tx53 board.
> > It turned out that the image header (which basically is a poke table
> > to initialize the SDRAM) indeed initialized the SDRAM. The problem was
> > that this SDRAM setup depends on some other lowlevel setup which is done
> > later. The SDRAM setup was good enough to load with MMU disabled, but
> > once the MMU is enabled the SDRAM does burst accesses and the board goes
> > to nirvana.
> > Maybe your problem is related somehow.
> yeah It may solve my issue with the MMU and nand boot
> 
> I was thinking to add a initcall support to the pbl and enable the MMU at the
> right momment. This will allow to simplify the adding of generic SPL framework

I don't think this is a good idea. I don't want to grow a second
bootloader in the pbl. It should stay simple.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH] pbl updates

[Jean-Christophe PLAGNIOL-VILLARD]

On 12:06 Wed 03 Oct     , Sascha Hauer wrote:
> On Tue, Oct 02, 2012 at 08:36:41PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 18:50 Tue 02 Oct     , Sascha Hauer wrote:
> > > On Tue, Oct 02, 2012 at 04:30:11PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 15:06 Tue 02 Oct     , Sascha Hauer wrote:
> > > > > Here are two updates for the MMU code in the decompressor. The first
> > > > > one may come in handy when a JTAG debugger is connected. The second
> > > > > one is more important. It actually makes turning on the MMU in the
> > > > > decompressor useful by making map_cachable work. It turned out that
> > > > > this didn't work leaving the whole mapping uncached.
> > > > > Note that the code in current master should work, but slow. Since
> > > > > it actually does work I do not want to put this into the upcoming
> > > > > release.
> > > > As I report the current code does not work on at91sam9g45
> > > > I suspect as we boot from the second ram controler on this SoC
> > > > 
> > > > So please hold the release that I can try those patch on sam9g45 if they fix
> > > > the PBL they will be mandatory for it
> > > 
> > > I think they won't fix it. map_cachable currently is a noop, but this
> > > should be fine as now we have a complete 1:1 uncached mapping. I don't
> > > see why this shouldn't work. I hope you find out.
> > > 
> > > What we can do for now is to add an additional Kconfig option to make
> > > enabling the MMU in the pbl optional. Then at least it should work on
> > > your boards.
> > Was thinking about this too
> 
> Ok, I'll prepare a patch.
> 
> > > 
> > > BTW I hunted down a strange problem with the MMU on a KaRO Tx53 board.
> > > It turned out that the image header (which basically is a poke table
> > > to initialize the SDRAM) indeed initialized the SDRAM. The problem was
> > > that this SDRAM setup depends on some other lowlevel setup which is done
> > > later. The SDRAM setup was good enough to load with MMU disabled, but
> > > once the MMU is enabled the SDRAM does burst accesses and the board goes
> > > to nirvana.
> > > Maybe your problem is related somehow.
> > yeah It may solve my issue with the MMU and nand boot
> > 
> > I was thinking to add a initcall support to the pbl and enable the MMU at the
> > right momment. This will allow to simplify the adding of generic SPL framework
> 
> I don't think this is a good idea. I don't want to grow a second
> bootloader in the pbl. It should stay simple.
I want to add spi boot and mmc boot where the non shell barebox is too big to
fit in sram

Begards,
J.
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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