From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-we0-f177.google.com ([74.125.82.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TKyv0-0006RO-CZ for barebox@lists.infradead.org; Sun, 07 Oct 2012 22:01:51 +0000 Received: by mail-we0-f177.google.com with SMTP id u50so2294765wey.36 for ; Sun, 07 Oct 2012 15:01:49 -0700 (PDT) From: Vicente Date: Mon, 8 Oct 2012 00:01:17 +0200 Message-Id: <1349647287-28224-4-git-send-email-vicencb@gmail.com> In-Reply-To: <1349647287-28224-1-git-send-email-vicencb@gmail.com> References: <1349647287-28224-1-git-send-email-vicencb@gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: barebox-bounces@lists.infradead.org Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH 03/13] ARM: ensure irqs are disabled To: barebox@lists.infradead.org Cc: Vicente Signed-off-by: Vicente --- arch/arm/cpu/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index 87ba877..da88f00 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -28,6 +28,7 @@ #include #include #include +#include /** * Enable processor's instruction cache @@ -85,6 +86,16 @@ void arch_shutdown(void) : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory" ); #endif + /* + * barebox normally does not use interrupts, but some functionalities + * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are + * disabled before exiting. + */ +#if __LINUX_ARM_ARCH__ >= 6 + __asm__ __volatile__ ("cpsid i\n"); +#else + __asm__ __volatile__ ("msr cpsr_c, #PSR_I_BIT | SVC_MODE\n"); +#endif } #ifdef CONFIG_THUMB2_BAREBOX -- 1.7.12.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox