* [PATCH 01/13] ARM i.MX: Use SoC specific base to access sdram controller registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 02/13] ARM i.MX nand layout: make multisoc safe Sascha Hauer
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
This redefines the sdram controller registers as offsets to the base
rather than as absolute addresses. All users are fixed to use the
SoC specific base address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 14 +++++-----
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 24 +++++++++++------
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 14 +++++-----
arch/arm/boards/guf-cupid/lowlevel.c | 33 +++++++++++++----------
arch/arm/boards/guf-neso/lowlevel.c | 21 ++++++++++-----
arch/arm/boards/karo-tx25/lowlevel.c | 8 +++---
arch/arm/boards/pcm037/lowlevel_init.S | 26 +++++++++---------
arch/arm/boards/pcm038/lowlevel.c | 21 ++++++++++-----
arch/arm/boards/pcm043/lowlevel.c | 21 ++++++++-------
arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 22 ++++++++++-----
arch/arm/mach-imx/include/mach/esdctl.h | 10 +++----
arch/arm/mach-imx/include/mach/imx27-regs.h | 2 +-
12 files changed, 126 insertions(+), 90 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index cd80b25..fe4e70c 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -129,22 +129,22 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* Init Mobile DDR */
- writel(0x0000000E, ESDMISC);
- writel(0x00000004, ESDMISC);
+ writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
- writel(0x0029572B, ESDCFG0);
- writel(0x92210000, ESDCTL0);
+ writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400);
- writel(0xA2210000, ESDCTL0);
+ writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR);
writeb(0xda, MX25_CSD0_BASE_ADDR);
- writel(0xB2210000, ESDCTL0);
+ writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33);
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
- writel(0x82216080, ESDCTL0);
+ writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index 1983d48..eac9ecc 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -22,7 +22,8 @@
/*
* DDR on CSD0
*/
- writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */
+ /* Enable DDR SDRAM operation */
+ writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
writel(0x55555555, DSCR(3)) /* Set the driving strength */
writel(0x55555555, DSCR(5))
@@ -30,12 +31,16 @@
writel(0x00005005, DSCR(7))
writel(0x15555555, DSCR(8))
- writel(0x00000004, ESDMISC) /* Initial reset */
- writel(CFG0, ESDCFG0)
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
@@ -45,7 +50,8 @@
subs r2, #1
bne 1b
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
@@ -56,7 +62,9 @@
#endif
mov r1, #0xff
strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
.endm
.section ".text_bare_init","ax"
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index ea932f7..7f9395e 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -138,22 +138,22 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* Init Mobile DDR */
- writel(0x0000000E, ESDMISC);
- writel(0x00000004, ESDMISC);
+ writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
- writel(0x0009572B, ESDCFG0);
- writel(0x92220000, ESDCTL0);
+ writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
- writel(0xA2220000, ESDCTL0);
+ writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR);
writeb(0xda, MX35_CSD0_BASE_ADDR);
- writel(0xB2220000, ESDCTL0);
+ writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
- writel(0x82228080, ESDCTL0);
+ writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index d451fd9..aa42697 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -71,15 +71,15 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
u32 r1, r0;
/* disable second SDRAM region to save power */
- r1 = readl(ESDCTL1);
+ r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
r1 &= ~ESDCTL0_SDE;
- writel(r1, ESDCTL1);
+ writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST;
- writel(mode, ESDMISC);
+ writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST);
- writel(mode, ESDMISC);
+ writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
/* wait for esdctl reset */
for (loop = 0; loop < 0x20000; loop++);
@@ -90,16 +90,18 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 |
ESDCFGx_tRCD_3 | ESDCFGx_tRC_20;
- writel(r1, ESDCFG0);
+ writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
/* enable SDRAM controller */
- writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_NORMAL,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
/* Micron Datasheet Initialization Step 3: Wait 200us before first command */
for (loop = 0; loop < 1000; loop++);
/* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */
- writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_PRECHARGE,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, sdram_addr);
/* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns)
@@ -109,7 +111,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP
* (at least 140ns)
*/
- writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, r9); /* AUTO REFRESH #1 */
for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
@@ -119,7 +122,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
/* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */
- writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(memsize | ESDCTL0_SMODE_LOAD_MODE,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3));
/* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP
@@ -134,7 +138,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
*/
/* Now configure SDRAM-Controller and check that it works */
- writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0);
+ writel(memsize | ESDCTL0_BL | ESDCTL0_REF4,
+ MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
/* Freescale asks for first access to be a write to properly
* initialize DQS pin-state and keepers
@@ -156,10 +161,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* if both value are identical, we don't have 14 rows. assume 13 instead */
if (readl(r9) == readl(r9 + (1 << 25))) {
- r0 = readl(ESDCTL0);
+ r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
r0 &= ~ESDCTL0_ROW_MASK;
r0 |= ESDCTL0_ROW13;
- writel(r0, ESDCTL0);
+ writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
/* So far we asssumed that we have 10 columns, verify this */
@@ -168,10 +173,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
/* if both value are identical, we don't have 10 cols. assume 9 instead */
if (readl(r9) == readl(r9 + (1 << 11))) {
- r0 = readl(ESDCTL0);
+ r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
r0 &= ~ESDCTL0_COL_MASK;
r0 |= ESDCTL0_COL9;
- writel(r0, ESDCTL0);
+ writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
}
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index e2e3c78..eff1f8d 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -71,7 +71,8 @@ void __bare_init __naked reset(void)
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
DSCR(3) = 0x55555555; /* Set the driving strength */
DSCR(5) = 0x55555555;
@@ -79,22 +80,28 @@ void __bare_init __naked reset(void)
DSCR(7) = 0x00005005;
DSCR(8) = 0x15555555;
- writel(0x00000004, ESDMISC); /* Initial reset */
- writel(0x006ac73a, ESDCFG0);
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
- ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 3192abd..6a324ce 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -46,8 +46,8 @@ static void __bare_init __naked insdram(void)
static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
uint32_t esdcfg)
{
- uint32_t esdctlreg = ESDCTL0;
- uint32_t esdcfgreg = ESDCFG0;
+ uint32_t esdctlreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0;
+ uint32_t esdcfgreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0;
if (base == 0x90000000) {
esdctlreg += 8;
@@ -137,9 +137,9 @@ void __bare_init __naked reset(void)
/* set to 3.3v SDRAM */
writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454);
- writel(ESDMISC_RST, ESDMISC);
+ writel(ESDMISC_RST, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
- while (!(readl(ESDMISC) & (1 << 31)));
+ while (!(readl(MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC) & (1 << 31)));
#define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \
ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL)
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index a6747c2..49e9b36 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -96,19 +96,19 @@ clear_iomux:
#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
#define ROWS0 ESDCTL0_ROW14
#endif
- writel(0x00000004, ESDMISC)
- writel(0x006ac73a, ESDCFG0)
- writel(0x90100000 | ROWS0, ESDCTL0)
+ writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
+ writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS0, ESDCTL0)
+ writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x12344321, MX31_CSD0_BASE_ADDR)
writel(0x12344321, MX31_CSD0_BASE_ADDR)
- writel(0xb0100000 | ROWS0, ESDCTL0)
+ writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS0, ESDCTL0)
+ writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
- writel(0x0000000c, ESDMISC)
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
@@ -116,18 +116,18 @@ clear_iomux:
#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
#define ROWS1 ESDCTL0_ROW14
#endif
- writel(0x006ac73a, ESDCFG1)
- writel(0x90100000 | ROWS1, ESDCTL1)
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1)
+ writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS1, ESDCTL1)
+ writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0x12344321, MX31_CSD1_BASE_ADDR)
writel(0x12344321, MX31_CSD1_BASE_ADDR)
- writel(0xb0100000 | ROWS1, ESDCTL1)
+ writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS1, ESDCTL1)
+ writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
- writel(0x0000000c, ESDMISC)
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
#endif
#ifdef CONFIG_NAND_IMX_BOOT
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index bed1c3f..2211e42 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -76,7 +76,8 @@ void __bare_init __naked reset(void)
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
DSCR(3) = 0x55555555; /* Set the driving strength */
DSCR(5) = 0x55555555;
@@ -84,22 +85,28 @@ void __bare_init __naked reset(void)
DSCR(7) = 0x00005005;
DSCR(8) = 0x15555555;
- writel(0x00000004, ESDMISC); /* Initial reset */
- writel(0x006ac73a, ESDCFG0);
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
for (i = 0; i < 8; i++)
writel(0, 0xa0000f00);
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, 0xa0000033);
writeb(0xff, 0xa1000000);
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
- ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 4516e9f..a3c1a09 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -66,6 +66,7 @@ void __bare_init __naked reset(void)
uint32_t r, s;
unsigned long ccm_base = MX35_CCM_BASE_ADDR;
unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR;
+ unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
@@ -154,17 +155,17 @@ void __bare_init __naked reset(void)
writel(r, iomuxc_base + 0x7a4);
/* MDDR init, enable mDDR*/
- writel(0x00000304, ESDMISC); /* was 0x00000004 */
+ writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */
/* set timing paramters */
- writel(0x0025541F, ESDCFG0);
+ writel(0x0025541F, esdctl_base + IMX_ESDCFG0);
/* select Precharge-All mode */
- writel(0x92220000, ESDCTL0);
+ writel(0x92220000, esdctl_base + IMX_ESDCTL0);
/* Precharge-All */
writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Load-Mode-Register mode */
- writel(0xB8001000, ESDCTL0);
+ writel(0xB8001000, esdctl_base + IMX_ESDCTL0);
/* Load reg EMR2 */
writeb(0xda, 0x84000000);
/* Load reg EMR3 */
@@ -175,18 +176,18 @@ void __bare_init __naked reset(void)
writeb(0xda, 0x80000333);
/* select Precharge-All mode */
- writel(0x92220000, ESDCTL0);
+ writel(0x92220000, esdctl_base + IMX_ESDCTL0);
/* Precharge-All */
writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400);
/* select Manual-Refresh mode */
- writel(0xA2220000, ESDCTL0);
+ writel(0xA2220000, esdctl_base + IMX_ESDCTL0);
/* Manual-Refresh 2 times */
writel(0x87654321, MX35_CSD0_BASE_ADDR);
writel(0x87654321, MX35_CSD0_BASE_ADDR);
/* select Load-Mode-Register mode */
- writel(0xB2220000, ESDCTL0);
+ writel(0xB2220000, esdctl_base + IMX_ESDCTL0);
/* Load reg MR -- CL3, BL8, end DLL reset */
writeb(0xda, 0x80000233);
/* Load reg EMR1 -- OCD default */
@@ -198,12 +199,12 @@ void __bare_init __naked reset(void)
* DSIZ32-bit, BL8, COL10-bit, ROW13-bit
* disable PWT & PRCT
* disable Auto-Refresh */
- writel(0x82220080, ESDCTL0);
+ writel(0x82220080, esdctl_base + IMX_ESDCTL0);
/* enable Auto-Refresh */
- writel(0x82228080, ESDCTL0);
+ writel(0x82228080, esdctl_base + IMX_ESDCTL0);
/* enable Auto-Refresh */
- writel(0x00002000, ESDCTL1);
+ writel(0x00002000, esdctl_base + IMX_ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index 3c36889..4b9add9 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -21,7 +21,8 @@
/*
* DDR on CSD0
*/
- writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
writel(0x55555555, DSCR(3)) /* Set the driving strength */
writel(0x55555555, DSCR(5))
@@ -29,12 +30,16 @@
writel(0x00005005, DSCR(7))
writel(0x15555555, DSCR(8))
- writel(0x00000004, ESDMISC) /* Initial reset */
- writel(0x006ac73a, ESDCFG0)
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
@@ -44,14 +49,17 @@
subs r2, #1
bne 1b
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
ldr r0, =0xA1000000
mov r1, #0xff
strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
.endm
.section ".text_bare_init","ax"
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 10c8b9b..8124c87 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -1,10 +1,10 @@
/* SDRAM Controller registers */
-#define ESDCTL0 (IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
-#define ESDCFG0 (IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-#define ESDCTL1 (IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
-#define ESDCFG1 (IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-#define ESDMISC (IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
+#define IMX_ESDCTL0 0x00 /* Enhanced SDRAM Control Register 0 */
+#define IMX_ESDCFG0 0x04 /* Enhanced SDRAM Configuration Register 0 */
+#define IMX_ESDCTL1 0x08 /* Enhanced SDRAM Control Register 1 */
+#define IMX_ESDCFG1 0x0C /* Enhanced SDRAM Configuration Register 1 */
+#define IMX_ESDMISC 0x10 /* Enhanced SDRAM Miscellanious Register */
#define ESDCTL0_SDE (1 << 31)
#define ESDCTL0_SMODE_NORMAL (0 << 28)
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index e7372e4..afc7a39 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -86,7 +86,7 @@
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_SIZE SZ_1M
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_ESDCTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 02/13] ARM i.MX nand layout: make multisoc safe
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
2012-10-11 7:13 ` [PATCH 01/13] ARM i.MX: Use SoC specific base to access sdram controller registers Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 03/13] ARM i.MX31: Cleanup remaining unprefixed registers Sascha Hauer
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/nand.c | 53 +++++++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index fff9a12..b347664 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -12,20 +12,20 @@
*/
#include <common.h>
+#include <mach/generic.h>
#include <mach/imx-regs.h>
#include <io.h>
-#if defined(CONFIG_ARCH_IMX35) || defined (CONFIG_ARCH_IMX25)
-
#define RCSR_NFC_FMS (1 << 8)
#define RCSR_NFC_4K (1 << 9)
#define RCSR_NFC_16BIT_SEL (1 << 14)
-void imx_nand_set_layout(int writesize, int datawidth)
+static __maybe_unused void imx25_35_nand_set_layout(void __iomem *reg_rcsr,
+ int writesize, int datawidth)
{
unsigned int rcsr;
- rcsr = readl(IMX_CCM_BASE + CCM_RCSR);
+ rcsr = readl(reg_rcsr);
switch (writesize) {
case 512:
@@ -52,19 +52,18 @@ void imx_nand_set_layout(int writesize, int datawidth)
break;
}
- writel(rcsr, IMX_CCM_BASE + CCM_RCSR);
+ writel(rcsr, reg_rcsr);
}
-#elif defined(CONFIG_ARCH_IMX21) || defined (CONFIG_ARCH_IMX27)
-
#define FMCR_NF_FMS (1 << 5)
#define FMCR_NF_16BIT_SEL (1 << 4)
-void imx_nand_set_layout(int writesize, int datawidth)
+static __maybe_unused void imx21_27_nand_set_layout(void __iomem *reg_fmcr,
+ int writesize, int datawidth)
{
unsigned int fmcr;
- fmcr = FMCR;
+ fmcr = readl(reg_fmcr);
switch (writesize) {
case 512:
@@ -88,23 +87,29 @@ void imx_nand_set_layout(int writesize, int datawidth)
break;
}
- FMCR = fmcr;
-}
-
-#elif defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53
-
-void imx_nand_set_layout(int writesize, int datawidth)
-{
- /* Just silence the compiler warning below. On i.MX51 we don't
- * have external boot.
- */
+ writel(fmcr, reg_fmcr);
}
-#else
-#warning using empty imx_nand_set_layout(). NAND flash will not work properly if not booting from it
-
void imx_nand_set_layout(int writesize, int datawidth)
{
-}
-
+#ifdef CONFIG_ARCH_IMX21
+ if (cpu_is_mx21())
+ imx21_27_nand_set_layout((void *)(MX21_SYSCTRL_BASE_ADDR +
+ 0x14), writesize, datawidth);
#endif
+#ifdef CONFIG_ARCH_IMX27
+ if (cpu_is_mx27())
+ imx21_27_nand_set_layout((void *)(MX27_SYSCTRL_BASE_ADDR +
+ 0x14), writesize, datawidth);
+#endif
+#ifdef CONFIG_ARCH_IMX25
+ if (cpu_is_mx25())
+ imx25_35_nand_set_layout((void *)MX25_CCM_BASE_ADDR +
+ CCM_RCSR, writesize, datawidth);
+#endif
+#ifdef CONFIG_ARCH_IMX35
+ if (cpu_is_mx35())
+ imx25_35_nand_set_layout((void *)MX35_CCM_BASE_ADDR +
+ CCM_RCSR, writesize, datawidth);
+#endif
+}
--
1.7.10.4
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 03/13] ARM i.MX31: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
2012-10-11 7:13 ` [PATCH 01/13] ARM i.MX: Use SoC specific base to access sdram controller registers Sascha Hauer
2012-10-11 7:13 ` [PATCH 02/13] ARM i.MX nand layout: make multisoc safe Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 04/13] ARM i.MX25: " Sascha Hauer
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/lowlevel_init.S | 37 +++++---
arch/arm/boards/pcm037/pcm037.c | 2 +-
arch/arm/mach-imx/external-nand-boot.c | 2 +-
arch/arm/mach-imx/include/mach/imx31-regs.h | 131 ++++++++++-----------------
4 files changed, 71 insertions(+), 101 deletions(-)
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index 49e9b36..283ea54 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -20,6 +20,7 @@
#include <mach/imx-regs.h>
#include <mach/imx-pll.h>
#include <asm/barebox-arm-head.h>
+#include <mach/esdctl.h>
#define writel(val, reg) \
ldr r0, =reg; \
@@ -46,24 +47,30 @@ reset:
common_reset r0
- writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR)
+ writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
DELAY 0x40000
- writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR)
- writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR)
-
- writel(PDR0_CSI_PODF(0xff1) | \
- PDR0_PER_PODF(7) | \
- PDR0_HSP_PODF(3) | \
- PDR0_NFC_PODF(5) | \
- PDR0_IPG_PODF(1) | \
- PDR0_MAX_PODF(3) | \
- PDR0_MCU_PODF(0), \
- MX31_CCM_BASE_ADDR + CCM_PDR0)
-
- writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL)
- writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL)
+ writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
+ MX31_CCM_CCMR)
+ writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
+ MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
+
+ writel(MX31_PDR0_CSI_PODF(0xff1) | \
+ MX31_PDR0_PER_PODF(7) | \
+ MX31_PDR0_HSP_PODF(3) | \
+ MX31_PDR0_NFC_PODF(5) | \
+ MX31_PDR0_IPG_PODF(1) | \
+ MX31_PDR0_MAX_PODF(3) | \
+ MX31_PDR0_MCU_PODF(0), \
+ MX31_CCM_BASE_ADDR + MX31_CCM_PDR0)
+
+ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
+ IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
+ MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL)
+ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
+ IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
+ MX31_CCM_SPCTL)
/* Configure IOMUXC
* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 1a1688d..79ea1dc 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -96,7 +96,7 @@ static void pcm037_usb_init(void)
/* Host 2 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
tmp |= 1 << 11;
- writel(tmp, IOMUXC_BASE + 0x8);
+ writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8);
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index a590992..6927eac 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -128,7 +128,7 @@ static int __maybe_unused is_pagesize_2k(void)
return 0;
#endif
#ifdef CONFIG_ARCH_IMX31
- if (readl(IMX_CCM_BASE + CCM_RCSR) & RCSR_NFMS)
+ if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
return 1;
else
return 0;
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index 57f65da..c11187e 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -140,95 +140,58 @@
/*
* Clock Controller Module (CCM)
*/
-#define CCM_CCMR 0x00
-#define CCM_PDR0 0x04
-#define CCM_PDR1 0x08
-#define CCM_RCSR 0x0c
-#define CCM_MPCTL 0x10
-#define CCM_UPCTL 0x14
-#define CCM_SPCTL 0x18
-#define CCM_COSR 0x1C
-
-/*
- * ?????????????
- */
-#define CCMR_MDS (1 << 7)
-#define CCMR_SBYCS (1 << 4)
-#define CCMR_MPE (1 << 3)
-#define CCMR_PRCS_MASK (3 << 1)
-#define CCMR_FPM (1 << 1)
-#define CCMR_CKIH (2 << 1)
-
-#define RCSR_NFMS (1 << 30)
-
-/*
- * ?????????????
- */
-#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
-#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
-#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
-#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
-#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
-#define PDR0_MCU_PODF(x) ((x) & 0x7)
-
-#include "esdctl.h"
-
-/*
- * ???????????
- */
-#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
-#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
-#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
+#define MX31_CCM_CCMR 0x00
+#define MX31_CCM_PDR0 0x04
+#define MX31_CCM_PDR1 0x08
+#define MX31_CCM_RCSR 0x0c
+#define MX31_CCM_MPCTL 0x10
+#define MX31_CCM_UPCTL 0x14
+#define MX31_CCM_SPCTL 0x18
+#define MX31_CCM_COSR 0x1C
+
+#define MX31_CCMR_MDS (1 << 7)
+#define MX31_CCMR_SBYCS (1 << 4)
+#define MX31_CCMR_MPE (1 << 3)
+#define MX31_CCMR_PRCS_MASK (3 << 1)
+#define MX31_CCMR_FPM (1 << 1)
+#define MX31_CCMR_CKIH (2 << 1)
+
+#define MX31_RCSR_NFMS (1 << 30)
+
+#define MX31_PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define MX31_PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
+#define MX31_PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
+#define MX31_PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
+#define MX31_PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
+#define MX31_PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
+#define MX31_PDR0_MCU_PODF(x) ((x) & 0x7)
+
+#define MX31_IOMUXC_GPR (IOMUXC_BASE + 0x8)
+#define MX31_IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
+#define MX31_IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
/*
* Signal Multiplexing (IOMUX)
*/
/* bits in the SW_MUX_CTL registers */
-#define MUX_CTL_OUT_GPIO_DR (0 << 4)
-#define MUX_CTL_OUT_FUNC (1 << 4)
-#define MUX_CTL_OUT_ALT1 (2 << 4)
-#define MUX_CTL_OUT_ALT2 (3 << 4)
-#define MUX_CTL_OUT_ALT3 (4 << 4)
-#define MUX_CTL_OUT_ALT4 (5 << 4)
-#define MUX_CTL_OUT_ALT5 (6 << 4)
-#define MUX_CTL_OUT_ALT6 (7 << 4)
-#define MUX_CTL_IN_NONE (0 << 0)
-#define MUX_CTL_IN_GPIO (1 << 0)
-#define MUX_CTL_IN_FUNC (2 << 0)
-#define MUX_CTL_IN_ALT1 (4 << 0)
-#define MUX_CTL_IN_ALT2 (8 << 0)
-
-#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
-#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
-#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
-#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
-
-/* Register offsets based on IOMUXC_BASE */
-/* 0x00 .. 0x7b */
-#define MUX_CTL_RTS1 0x7c
-#define MUX_CTL_CTS1 0x7d
-#define MUX_CTL_DTR_DCE1 0x7e
-#define MUX_CTL_DSR_DCE1 0x7f
-#define MUX_CTL_CSPI2_SCLK 0x80
-#define MUX_CTL_CSPI2_SPI_RDY 0x81
-#define MUX_CTL_RXD1 0x82
-#define MUX_CTL_TXD1 0x83
-#define MUX_CTL_CSPI2_MISO 0x84
-/* 0x85 .. 0x8a */
-#define MUX_CTL_CSPI2_MOSI 0x8b
-
-/* The modes a specific pin can be in
- * these macros can be used in mx31_gpio_mux() and have the form
- * MUX_[contact name]__[pin function]
- */
-#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
-#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
-#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
-#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
-
-#define MUX_CSPI2_MOSI_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
-#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+#define MX31_MUX_CTL_OUT_GPIO_DR (0 << 4)
+#define MX31_MUX_CTL_OUT_FUNC (1 << 4)
+#define MX31_MUX_CTL_OUT_ALT1 (2 << 4)
+#define MX31_MUX_CTL_OUT_ALT2 (3 << 4)
+#define MX31_MUX_CTL_OUT_ALT3 (4 << 4)
+#define MX31_MUX_CTL_OUT_ALT4 (5 << 4)
+#define MX31_MUX_CTL_OUT_ALT5 (6 << 4)
+#define MX31_MUX_CTL_OUT_ALT6 (7 << 4)
+#define MX31_MUX_CTL_IN_NONE (0 << 0)
+#define MX31_MUX_CTL_IN_GPIO (1 << 0)
+#define MX31_MUX_CTL_IN_FUNC (2 << 0)
+#define MX31_MUX_CTL_IN_ALT1 (4 << 0)
+#define MX31_MUX_CTL_IN_ALT2 (8 << 0)
+
+#define MX31_MUX_CTL_FUNC (MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC)
+#define MX31_MUX_CTL_ALT1 (MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1)
+#define MX31_MUX_CTL_ALT2 (MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2)
+#define MX31_MUX_CTL_GPIO (MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO)
#endif /* __ASM_ARCH_MX31_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 04/13] ARM i.MX25: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (2 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 03/13] ARM i.MX31: Cleanup remaining unprefixed registers Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 05/13] ARM i.MX35: " Sascha Hauer
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 12 ++--
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 4 +-
.../boards/freescale-mx25-3-stack/lowlevel_init.S | 6 +-
arch/arm/boards/karo-tx25/board.c | 2 +-
arch/arm/boards/karo-tx25/lowlevel.c | 8 +--
arch/arm/mach-imx/external-nand-boot.c | 8 ++-
arch/arm/mach-imx/imx25.c | 6 +-
arch/arm/mach-imx/include/mach/imx25-regs.h | 60 ++++++++++----------
arch/arm/mach-imx/nand.c | 2 +-
9 files changed, 57 insertions(+), 51 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index fe4e70c..61105a7 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -57,15 +57,15 @@ void __bare_init __naked reset(void)
common_reset();
/* restart the MPLL and wait until it's stable */
- writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27),
- MX25_CCM_BASE_ADDR + CCM_CCTL);
- while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {};
+ writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27),
+ MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
+ while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {};
/* Configure dividers and ARM clock source
* ARM @ 400 MHz
* AHB @ 133 MHz
*/
- writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
/* Enable UART1 / FEC / */
/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0);
@@ -118,10 +118,10 @@ void __bare_init __naked reset(void)
writel(0x1, 0xb8003000);
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
r &= ~0xf;
r |= 0x1;
- writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index a0ae938..f5af7c5 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -215,7 +215,7 @@ static int imx25_devices_init(void)
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
@@ -298,7 +298,7 @@ void __bare_init nand_boot(void)
static int imx25_core_setup(void)
{
- writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2);
+ writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
return 0;
}
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index f911f9d..6635571 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -66,9 +66,9 @@ reset:
str r1, [r0, #MX25_CCM_MCR]
/* enable all the clocks */
- writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0)
- writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1)
- writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2)
+ writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0)
+ writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1)
+ writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2)
writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR)
/* Skip SDRAM initialization if we run from RAM */
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 82d5eb5..5c7b28b 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -108,7 +108,7 @@ static int tx25_devices_init(void)
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
- if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14))
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 6a324ce..0689f83 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -122,12 +122,12 @@ void __bare_init __naked reset(void)
writel(0x1, 0xb8003000);
/* configure ARM clk */
- writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL);
+ writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
/* enable all the clocks */
- writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0);
- writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1);
- writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2);
+ writel(0x1fffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0);
+ writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1);
+ writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 6927eac..9bcfcca 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -121,6 +121,12 @@ static int __maybe_unused is_pagesize_2k(void)
else
return 0;
#endif
+#if defined(CONFIG_ARCH_IMX25)
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
+ return 1;
+ else
+ return 0;
+#endif
#ifdef CONFIG_ARCH_IMX27
if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
return 1;
@@ -133,7 +139,7 @@ static int __maybe_unused is_pagesize_2k(void)
else
return 0;
#endif
-#if defined(CONFIG_ARCH_IMX35) || defined(CONFIG_ARCH_IMX25)
+#if defined(CONFIG_ARCH_IMX35)
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8))
return 1;
else
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 92b5a1b..0f92b17 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -61,9 +61,9 @@ static int imx25_init(void)
{
uint32_t val;
- val = readl(MX25_CCM_BASE_ADDR + CCM_RCSR);
- imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
- (val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+ val = readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> MX25_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> MX25_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 0bf6e11..46fdf48 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -86,36 +86,36 @@
/*
* Clock Controller Module (CCM)
*/
-#define CCM_MPCTL 0x00
-#define CCM_UPCTL 0x04
-#define CCM_CCTL 0x08
-#define CCM_CGCR0 0x0C
-#define CCM_CGCR1 0x10
-#define CCM_CGCR2 0x14
-#define CCM_PCDR0 0x18
-#define CCM_PCDR1 0x1C
-#define CCM_PCDR2 0x20
-#define CCM_PCDR3 0x24
-#define CCM_RCSR 0x28
-#define CCM_CRDR 0x2C
-#define CCM_DCVR0 0x30
-#define CCM_DCVR1 0x34
-#define CCM_DCVR2 0x38
-#define CCM_DCVR3 0x3c
-#define CCM_LTR0 0x40
-#define CCM_LTR1 0x44
-#define CCM_LTR2 0x48
-#define CCM_LTR3 0x4c
-
-#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
-#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
-#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
-#define PDR0_AUTO_CON (1 << 0)
-#define PDR0_PER_SEL (1 << 26)
-
-#define CCM_RCSR_MEM_CTRL_SHIFT 30
-#define CCM_RCSR_MEM_TYPE_SHIFT 28
+#define MX25_CCM_MPCTL 0x00
+#define MX25_CCM_UPCTL 0x04
+#define MX25_CCM_CCTL 0x08
+#define MX25_CCM_CGCR0 0x0C
+#define MX25_CCM_CGCR1 0x10
+#define MX25_CCM_CGCR2 0x14
+#define MX25_CCM_PCDR0 0x18
+#define MX25_CCM_PCDR1 0x1C
+#define MX25_CCM_PCDR2 0x20
+#define MX25_CCM_PCDR3 0x24
+#define MX25_CCM_RCSR 0x28
+#define MX25_CCM_CRDR 0x2C
+#define MX25_CCM_DCVR0 0x30
+#define MX25_CCM_DCVR1 0x34
+#define MX25_CCM_DCVR2 0x38
+#define MX25_CCM_DCVR3 0x3c
+#define MX25_CCM_LTR0 0x40
+#define MX25_CCM_LTR1 0x44
+#define MX25_CCM_LTR2 0x48
+#define MX25_CCM_LTR3 0x4c
+
+#define MX25_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
+#define MX25_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
+#define MX25_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
+#define MX25_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
+#define MX25_PDR0_AUTO_CON (1 << 0)
+#define MX25_PDR0_PER_SEL (1 << 26)
+
+#define MX25_CCM_RCSR_MEM_CTRL_SHIFT 30
+#define MX25_CCM_RCSR_MEM_TYPE_SHIFT 28
/*
* Adresses and ranges of the external chip select lines
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index b347664..9b53b70 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -105,7 +105,7 @@ void imx_nand_set_layout(int writesize, int datawidth)
#ifdef CONFIG_ARCH_IMX25
if (cpu_is_mx25())
imx25_35_nand_set_layout((void *)MX25_CCM_BASE_ADDR +
- CCM_RCSR, writesize, datawidth);
+ MX25_CCM_RCSR, writesize, datawidth);
#endif
#ifdef CONFIG_ARCH_IMX35
if (cpu_is_mx35())
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 05/13] ARM i.MX35: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (3 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 04/13] ARM i.MX25: " Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 06/13] ARM i.MX external nand boot: Use SoC specific base addresses Sascha Hauer
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c | 20 +++----
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 24 ++++----
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 10 ++--
.../boards/freescale-mx35-3-stack/lowlevel_init.S | 20 +++----
arch/arm/boards/guf-cupid/board.c | 6 +-
arch/arm/boards/guf-cupid/lowlevel.c | 18 +++---
arch/arm/boards/pcm043/lowlevel.c | 18 +++---
arch/arm/boards/pcm043/pcm043.c | 6 +-
arch/arm/mach-imx/external-nand-boot.c | 2 +-
arch/arm/mach-imx/imx35.c | 6 +-
arch/arm/mach-imx/include/mach/imx35-regs.h | 62 ++++++++++----------
arch/arm/mach-imx/nand.c | 2 +-
drivers/video/imx-ipu-fb.c | 4 +-
13 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 53cc428..5d8830b 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -246,14 +246,14 @@ static int eukrea_cpuimx35_core_init(void)
u32 reg;
/* enable clock for I2C1, SDHC1, USB and FEC */
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
- reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
- reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2);
- reg |= 0x3 << CCM_CGR2_USB_SHIFT;
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_SDHC1_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT,
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
+ reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT;
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
@@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index 7f9395e..c6ab3be 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -41,10 +41,10 @@ static void __bare_init __naked insdram(void)
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4);
+ r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
- writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4);
+ writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
@@ -106,27 +106,27 @@ void __bare_init __naked reset(void)
* End of ARM1136 init
*/
- writel(0x003F4208, ccm_base + CCM_CCMR);
+ writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
- writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
- writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
- writel(0x00001000, ccm_base + CCM_PDR0);
+ writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
+ writel(0x00001000, ccm_base + MX35_CCM_PDR0);
- r = readl(ccm_base + CCM_CGR0);
+ r = readl(ccm_base + MX35_CCM_CGR0);
r |= 0x00300000;
- writel(r, ccm_base + CCM_CGR0);
+ writel(r, ccm_base + MX35_CCM_CGR0);
- r = readl(ccm_base + CCM_CGR1);
+ r = readl(ccm_base + MX35_CCM_CGR1);
r |= 0x00030C00;
r |= 0x00000003;
- writel(r, ccm_base + CCM_CGR1);
+ writel(r, ccm_base + MX35_CCM_CGR1);
/* enable watchdog asap */
- r = readl(ccm_base + CCM_CGR2);
+ r = readl(ccm_base + MX35_CCM_CGR2);
r |= 0x03000000;
- writel(r, ccm_base + CCM_CGR2);
+ writel(r, ccm_base + MX35_CCM_CGR2);
r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 1a5bf5b..4c79317 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -144,7 +144,7 @@ static int f3s_devices_init(void)
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -282,10 +282,10 @@ static int f3s_core_init(void)
imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
/* enable clock for I2C1 and FEC */
- reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
- reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
- reg |= 0x3 << CCM_CGR1_I2C1_SHIFT;
- reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+ reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
+ reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index e5d0feb..bd3dd7f 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -98,27 +98,27 @@ reset:
ldr r0, CCM_BASE_ADDR_W
ldr r2, CCM_CCMR_W
- str r2, [r0, #CCM_CCMR]
+ str r2, [r0, #MX35_CCM_CCMR]
ldr r3, MPCTL_PARAM_532_W /* consumer path*/
/* Set MPLL, arm clock and ahb clock */
- str r3, [r0, #CCM_MPCTL]
+ str r3, [r0, #MX35_CCM_MPCTL]
ldr r1, PPCTL_PARAM_W
- str r1, [r0, #CCM_PPCTL]
+ str r1, [r0, #MX35_CCM_PPCTL]
ldr r1, CCM_PDR0_W
- str r1, [r0, #CCM_PDR0]
+ str r1, [r0, #MX35_CCM_PDR0]
- ldr r1, [r0, #CCM_CGR0]
+ ldr r1, [r0, #MX35_CCM_CGR0]
orr r1, r1, #0x00300000
- str r1, [r0, #CCM_CGR0]
+ str r1, [r0, #MX35_CCM_CGR0]
- ldr r1, [r0, #CCM_CGR1]
+ ldr r1, [r0, #MX35_CCM_CGR1]
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
- str r1, [r0, #CCM_CGR1]
+ str r1, [r0, #MX35_CCM_CGR1]
/* Skip SDRAM initialization if we run from RAM */
cmp pc, #CSD0_BASE_ADDR
@@ -140,13 +140,13 @@ reset:
/* setup bank 0 */
mov r5, #0x00
mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
+ mov r1, #MX35_CSD0_BASE_ADDR
bl setup_sdram_bank
/* setup bank 1 */
mov r5, #0x00
mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
+ mov r1, #MX35_CSD1_BASE_ADDR
bl setup_sdram_bank
mov lr, fp
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 933a9cd..e36fee8 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -117,7 +117,7 @@ static int cupid_devices_init(void)
gpio_direction_output(GPIO_LCD_ENABLE, 0);
gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index aa42697..900bdf9 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -304,27 +304,27 @@ void __bare_init __naked reset(void)
/* Configure clocks */
/* setup cpu/bus clocks */
- writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR);
+ writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR);
/* configure MPLL */
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
/* configure PPLL */
- writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL);
+ writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL);
/* configure core dividers */
- r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2);
+ r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2);
- writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0);
/* configure clock-gates */
- r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0);
+ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
r0 |= 0x00300000;
- writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
- r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1);
+ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
r0 |= 0x00000c03;
- writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1);
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* Configure SDRAM */
/* Try 32-Bit 256 MB DDR memory */
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index a3c1a09..58c0840 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -111,28 +111,28 @@ void __bare_init __naked reset(void)
* End of ARM1136 init
*/
- writel(0x003F4208, ccm_base + CCM_CCMR);
+ writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
- writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
- writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
+ writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
/* Check silicon revision and use 532MHz if >=2.1 */
r = readl(MX35_IIM_BASE_ADDR + 0x24);
if (r >= IMX35_CHIP_REVISION_2_1)
- writel(CCM_PDR0_532, ccm_base + CCM_PDR0);
+ writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0);
else
- writel(CCM_PDR0_399, ccm_base + CCM_PDR0);
+ writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0);
- r = readl(ccm_base + CCM_CGR0);
+ r = readl(ccm_base + MX35_CCM_CGR0);
r |= 0x00300000;
- writel(r, ccm_base + CCM_CGR0);
+ writel(r, ccm_base + MX35_CCM_CGR0);
- r = readl(ccm_base + CCM_CGR1);
+ r = readl(ccm_base + MX35_CCM_CGR1);
r |= 0x00000C00;
r |= 0x00000003;
- writel(r, ccm_base + CCM_CGR1);
+ writel(r, ccm_base + MX35_CCM_CGR1);
r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
r |= 0x1000;
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 09bc96a..b0d48ba 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -127,7 +127,7 @@ static int imx35_devices_init(void)
led_gpio_register(&led0);
- reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
@@ -308,10 +308,10 @@ static int do_cpufreq(int argc, char *argv[])
switch (freq) {
case 399:
- writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
case 532:
- writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL);
+ writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 9bcfcca..7cf2a07 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -140,7 +140,7 @@ static int __maybe_unused is_pagesize_2k(void)
return 0;
#endif
#if defined(CONFIG_ARCH_IMX35)
- if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8))
+ if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
return 1;
else
return 0;
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 946c8dd..5560157 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -63,9 +63,9 @@ static int imx35_init(void)
imx35_silicon_revision();
- val = readl(MX35_CCM_BASE_ADDR + CCM_RCSR);
- imx_25_35_boot_save_loc((val >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
- (val >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
+ val = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
+ imx_25_35_boot_save_loc((val >> MX35_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3,
+ (val >> MX35_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3);
add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 19f6389..37a4dad 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -141,36 +141,36 @@
/*
* Clock Controller Module (CCM)
*/
-#define CCM_CCMR 0x00
-#define CCM_PDR0 0x04
-#define CCM_PDR1 0x08
-#define CCM_PDR2 0x0C
-#define CCM_PDR3 0x10
-#define CCM_PDR4 0x14
-#define CCM_RCSR 0x18
-#define CCM_MPCTL 0x1C
-#define CCM_PPCTL 0x20
-#define CCM_ACMR 0x24
-#define CCM_COSR 0x28
-#define CCM_CGR0 0x2C
-#define CCM_CGR1 0x30
-#define CCM_CGR2 0x34
-#define CCM_CGR3 0x38
-
-#define CCM_CGR0_CSPI1_SHIFT 10
-#define CCM_CGR1_FEC_SHIFT 0
-#define CCM_CGR1_I2C1_SHIFT 10
-#define CCM_CGR1_SDHC1_SHIFT 26
-#define CCM_CGR2_USB_SHIFT 22
-
-#define CCM_RCSR_MEM_CTRL_SHIFT 25
-#define CCM_RCSR_MEM_TYPE_SHIFT 23
-
-#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
-#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
-#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
-#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
-#define PDR0_AUTO_CON (1 << 0)
-#define PDR0_PER_SEL (1 << 26)
+#define MX35_CCM_CCMR 0x00
+#define MX35_CCM_PDR0 0x04
+#define MX35_CCM_PDR1 0x08
+#define MX35_CCM_PDR2 0x0C
+#define MX35_CCM_PDR3 0x10
+#define MX35_CCM_PDR4 0x14
+#define MX35_CCM_RCSR 0x18
+#define MX35_CCM_MPCTL 0x1C
+#define MX35_CCM_PPCTL 0x20
+#define MX35_CCM_ACMR 0x24
+#define MX35_CCM_COSR 0x28
+#define MX35_CCM_CGR0 0x2C
+#define MX35_CCM_CGR1 0x30
+#define MX35_CCM_CGR2 0x34
+#define MX35_CCM_CGR3 0x38
+
+#define MX35_CCM_CGR0_CSPI1_SHIFT 10
+#define MX35_CCM_CGR1_FEC_SHIFT 0
+#define MX35_CCM_CGR1_I2C1_SHIFT 10
+#define MX35_CCM_CGR1_SDHC1_SHIFT 26
+#define MX35_CCM_CGR2_USB_SHIFT 22
+
+#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25
+#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23
+
+#define MX35_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
+#define MX35_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
+#define MX35_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
+#define MX35_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
+#define MX35_PDR0_AUTO_CON (1 << 0)
+#define MX35_PDR0_PER_SEL (1 << 26)
#endif /* __ASM_ARCH_MX35_REGS_H */
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index 9b53b70..e793015 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -110,6 +110,6 @@ void imx_nand_set_layout(int writesize, int datawidth)
#ifdef CONFIG_ARCH_IMX35
if (cpu_is_mx35())
imx25_35_nand_set_layout((void *)MX35_CCM_BASE_ADDR +
- CCM_RCSR, writesize, datawidth);
+ MX35_CCM_RCSR, writesize, datawidth);
#endif
}
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 3f8fd33..5b9d7d5 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -742,9 +742,9 @@ static void ipu_fb_enable(struct fb_info *info)
/* ipu_idmac.c::ipu_probe() */
/* Start the clock */
- reg = readl(IMX_CCM_BASE + CCM_CGR1);
+ reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
reg |= (3 << 18);
- writel(reg, IMX_CCM_BASE + CCM_CGR1);
+ writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
/* ipu_idmac.c::ipu_idmac_init() */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 06/13] ARM i.MX external nand boot: Use SoC specific base addresses
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (4 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 05/13] ARM i.MX35: " Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 07/13] ARM i.MX: remove unused improperly prefixed register defines Sascha Hauer
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/external-nand-boot.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 7cf2a07..7fed26f 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -169,7 +169,21 @@ void __bare_init imx_nand_load_image(void *dest, int size)
blocksize = 16 * 1024;
}
- base = (void __iomem *)IMX_NFC_BASE;
+#ifdef CONFIG_ARCH_IMX21
+ base = (void __iomem *)MX21_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX25
+ base = (void __iomem *)MX25_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX27
+ base = (void __iomem *)MX27_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX31
+ base = (void __iomem *)MX31_NFC_BASE_ADDR;
+#endif
+#ifdef CONFIG_ARCH_IMX35
+ base = (void __iomem *)MX35_NFC_BASE_ADDR;
+#endif
if (nfc_is_v21()) {
regs = base + 0x1e00;
spare0 = base + 0x1000;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 07/13] ARM i.MX: remove unused improperly prefixed register defines
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (5 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 06/13] ARM i.MX external nand boot: Use SoC specific base addresses Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 08/13] ARM i.MX1: Cleanup remaining unprefixed registers Sascha Hauer
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 4 ++--
arch/arm/boards/guf-cupid/lowlevel.c | 2 +-
arch/arm/mach-imx/external-nand-boot.c | 2 +-
arch/arm/mach-imx/include/mach/imx1-regs.h | 5 -----
arch/arm/mach-imx/include/mach/imx21-regs.h | 6 ------
arch/arm/mach-imx/include/mach/imx25-regs.h | 17 -----------------
arch/arm/mach-imx/include/mach/imx27-regs.h | 6 ------
arch/arm/mach-imx/include/mach/imx31-regs.h | 7 -------
arch/arm/mach-imx/include/mach/imx35-regs.h | 8 --------
arch/arm/mach-imx/include/mach/imx51-regs.h | 4 ----
arch/arm/mach-imx/include/mach/imx53-regs.h | 4 ----
arch/arm/mach-imx/include/mach/imx6-regs.h | 6 ------
12 files changed, 4 insertions(+), 67 deletions(-)
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index f5af7c5..8b3c43d 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -167,8 +167,8 @@ static int imx25_3ds_fec_init(void)
* FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
* FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
*/
- writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
- writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */
+ writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */
+ writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */
#define FEC_ENABLE_GPIO 35
#define FEC_RESET_B_GPIO 104
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index 900bdf9..22ebaa0 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -187,7 +187,7 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad
void __bare_init __naked reset(void)
{
u32 r0, r1;
- void *iomuxc_base = (void *)IMX_IOMUXC_BASE;
+ void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR;
int i;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 7fed26f..d3f2637 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -116,7 +116,7 @@ static void __bare_init __memcpy32(void *trg, const void *src, int size)
static int __maybe_unused is_pagesize_2k(void)
{
#ifdef CONFIG_ARCH_IMX21
- if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5))
+ if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
return 1;
else
return 0;
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index a4d1690..5d9de1a 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -59,11 +59,6 @@
#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
-/* FIXME: get rid of these */
-#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR
-#define IMX_WDT_BASE MX1_WDT_BASE_ADDR
-#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR
-
/* SYSCTRL Registers */
#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */
#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 9952b8b..0b8ff22 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -71,12 +71,6 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
-/* FIXME: Get rid of these */
-#define IMX_GPIO_BASE MX21_GPIO_BASE_ADDR
-#define IMX_TIM1_BASE MX21_GPT1_BASE_ADDR
-#define IMX_WDT_BASE MX21_WDOG_BASE_ADDR
-#define IMX_SYSTEM_CTL_BASE MX21_SYSCTRL_BASE_ADDR
-
/* AIPI */
#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00)
#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04)
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 46fdf48..b8ae45a 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -76,13 +76,6 @@
#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
#define MX25_CSI_BASE_ADDR 0x53ff8000
-/* FIXME: Get rid of these */
-#define IMX_TIM1_BASE MX25_GPT1_BASE_ADDR
-#define IMX_IOMUXC_BASE MX25_IOMUXC_BASE_ADDR
-#define IMX_WDT_BASE MX25_WDOG_BASE_ADDR
-#define IMX_CCM_BASE MX25_CCM_BASE_ADDR
-#define IMX_ESD_BASE MX25_ESDCTL_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
@@ -139,14 +132,4 @@
#define MX25_ESDCTL_BASE_ADDR 0xb8001000
#define MX25_WEIM_BASE_ADDR 0xb8002000
-/*
- * Watchdog Registers
- */
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
#endif /* __ASM_ARCH_MX25_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index afc7a39..a9658fa 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -101,12 +101,6 @@
/* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
-/* FIXME: get rid of these */
-#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR
-#define IMX_NFC_BASE MX27_NFC_BASE_ADDR
-#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR
-#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR
-
#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00)
#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04)
#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08)
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index c11187e..f641fe6 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -130,13 +130,6 @@
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
-/* FIXME: Get rid of these */
-#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR
-#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR
-#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR
-#define IMX_NFC_BASE MX31_NFC_BASE_ADDR
-#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 37a4dad..bbfde23 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -130,14 +130,6 @@
#define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
-/* FIXME: Get rid of these */
-#define IMX_WDT_BASE MX35_WDOG_BASE_ADDR
-#define IMX_TIM1_BASE MX35_GPT1_BASE_ADDR
-#define IMX_ESD_BASE MX35_ESDCTL_BASE_ADDR
-#define IMX_IOMUXC_BASE MX35_IOMUXC_BASE_ADDR
-#define IMX_CCM_BASE MX35_CCM_BASE_ADDR
-#define IMX_NFC_BASE MX35_NFC_BASE_ADDR
-
/*
* Clock Controller Module (CCM)
*/
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
index c451004..8eb74cd 100644
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX51_REGS_H
#define __MACH_IMX51_REGS_H
-#define IMX_TIM1_BASE 0x73fa0000
-#define IMX_WDT_BASE 0x73f98000
-#define IMX_IOMUXC_BASE 0x73fa8000
-
/* WEIM registers */
#define WEIM_CSxGCR1(n) (((n) * 0x18) + 0x00)
#define WEIM_CSxGCR2(n) (((n) * 0x18) + 0x04)
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
index e57d1ab..8025e97 100644
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX53_REGS_H
#define __MACH_IMX53_REGS_H
-#define IMX_TIM1_BASE 0X53FA0000
-#define IMX_WDT_BASE 0X53F98000
-#define IMX_IOMUXC_BASE 0X53FA8000
-
#define MX53_IROM_BASE_ADDR 0x0
/*
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index eca4fa6..716e6b4 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -1,10 +1,6 @@
#ifndef __MACH_IMX6_REGS_H
#define __MACH_IMX6_REGS_H
-#define IMX_TIM1_BASE 0x02098000
-#define IMX_WDT_BASE 0x020bc000
-#define IMX_IOMUXC_BASE 0x020e0000
-
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
@@ -12,8 +8,6 @@
#define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR
#define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR
-#define IPU_CTRL_BASE_ADDR 0x02400000
-
/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
#define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000)
#define MX6_ECSPI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x08000)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 08/13] ARM i.MX1: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (6 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 07/13] ARM i.MX: remove unused improperly prefixed register defines Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 09/13] ARM i.MX21: " Sascha Hauer
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/scb9328/lowlevel_init.S | 29 +++++++++++++----------
arch/arm/boards/scb9328/scb9328.c | 4 ++--
arch/arm/mach-imx/include/mach/imx1-regs.h | 35 ++++++++++++++--------------
3 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index fabc89e..c303d2d 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -82,13 +82,13 @@ reset:
common_reset r0
/* Change PERCLK1DIV to 14 ie 14+1 */
- writel(CFG_PCDR_VAL, PCDR)
+ writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR)
/* set MCU PLL Control Register 0 */
- writel(CFG_MPCTL0_VAL, MPCTL0)
+ writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0)
/* set mpll restart bit */
- ldr r0, =CSCR
+ ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
ldr r1, [r0]
orr r1,r1,#(1<<21)
str r1, [r0]
@@ -104,10 +104,10 @@ reset:
bne 1b
/* set System PLL Control Register 0 */
- writel(CFG_SPCTL0_VAL, SPCTL0)
+ writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0)
/* set spll restart bit */
- ldr r0, =CSCR
+ ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
ldr r1, [r0]
orr r1,r1,#(1<<22)
str r1, [r0]
@@ -122,7 +122,7 @@ reset:
subs r2,r2,#1
bne 1b
- writel(CFG_CSCR_VAL, CSCR)
+ writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR)
/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
*this.....
@@ -157,9 +157,12 @@ reset:
/* SDRAM Setup */
- writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */
- writel(0x0, 0x08200000) /* Issue Precharge all Command */
- writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */
+ /* Precharge cmd, CAS = 2 */
+ writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
+ /* Issue Precharge all Command */
+ writel(0x0, 0x08200000)
+ /* Autorefresh cmd, CAS = 2 */
+ writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
ldr r0, =0x08000000
ldr r1, =0x0 /* Issue AutoRefresh Command */
@@ -172,8 +175,10 @@ reset:
str r1, [r0]
str r1, [r0]
- writel(0xb10a8300, SDCTL0)
- writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
- writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */
+ writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
+ /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
+ writel(0x0, 0x08223000)
+ /* Set to Normal Mode CAS 2 */
+ writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
b board_init_lowlevel_return
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index 1a85554..fd2758c 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -69,8 +69,8 @@ static int scb9328_devices_init(void)
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
- FMCR = 0x1;
+ /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+ writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR);
imx1_setup_eimcs(0, 0x000F2000, 0x11110d01);
imx1_setup_eimcs(1, 0x000F0a00, 0x11110601);
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index 5d9de1a..df6ede5 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -59,26 +59,25 @@
#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
-/* SYSCTRL Registers */
-#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */
-#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */
-#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */
+/* SYSCTRL Registers (base MX1_SCM_BASE_ADDR) */
+#define MX1_SIDR 0x4 /* Silicon ID Register */
+#define MX1_FMCR 0x8 /* Function Multiplex Control Register */
+#define MX1_GPCR 0xC /* Function Multiplex Control Register */
-/* SDRAM controller registers */
+/* SDRAM controller registers (base MX1_SDRAMC_BASE_ADDR) */
+#define MX1_SDCTL0 0x0 /* SDRAM 0 Control Register */
+#define MX1_SDCTL1 0x4 /* SDRAM 1 Control Register */
+#define MX1_SDMISC 0x14 /* Miscellaneous Register */
+#define MX1_SDRST 0x18 /* SDRAM Reset Register */
-#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */
-#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */
-#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
+/* PLL registers (base MX1_CCM_BASE_ADDR) */
+#define MX1_CSCR 0x0 /* Clock Source Control Register */
+#define MX1_MPCTL0 0x4 /* MCU PLL Control Register 0 */
+#define MX1_MPCTL1 0x8 /* MCU PLL and System Clock Register 1 */
+#define MX1_SPCTL0 0xc /* System PLL Control Register 0 */
+#define MX1_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX1_PCDR 0x20 /* Peripheral Clock Divider Register */
-/* PLL registers */
-#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */
-#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */
-
-#define CSCR_MPLL_RESTART (1<<21)
+#define MX1_CSCR_MPLL_RESTART (1<<21)
#endif /* _IMX1_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 09/13] ARM i.MX21: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (7 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 08/13] ARM i.MX1: Cleanup remaining unprefixed registers Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 10/13] ARM i.MX27: " Sascha Hauer
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/imx21ads/imx21ads.c | 4 +-
arch/arm/boards/imx21ads/lowlevel_init.S | 18 ++--
arch/arm/mach-imx/include/mach/imx21-regs.h | 130 +++++++++++++--------------
3 files changed, 76 insertions(+), 76 deletions(-)
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 26604a9..c4f44e9 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -95,10 +95,10 @@ static int imx21ads_timing_init(void)
imx21_setup_eimcs(4, 0x0, 0x0);
imx21_setup_eimcs(5, 0x0, 0x0);
- temp = PCDR0;
+ temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0);
temp &= ~0xF000;
temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */
- PCDR0 = temp;
+ writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0);
return 0;
}
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index 0cb8aaf..be1199b 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -30,17 +30,17 @@ reset:
* on chip peripherals) as described in section 7.2 of rev3 of the i.MX21
* reference manual.
*/
- ldr r0, =AIPI1_PSR0
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0
ldr r1, =0x00040304
str r1, [r0]
- ldr r0, =AIPI1_PSR1
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1
ldr r1, =0xfffbfcfb
str r1, [r0]
- ldr r0, =AIPI2_PSR0
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0
ldr r1, =0x3ffc0000
str r1, [r0]
- ldr r0, =AIPI2_PSR1
+ ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1
ldr r1, =0xffffffff
str r1, [r0]
@@ -48,11 +48,11 @@ reset:
* Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable
* the clock to peripherals.
*/
- ldr r0, =CSCR
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR
ldr r1, =0x17180607
str r1, [r0]
- ldr r0, =PCCR1
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1
ldr r1, =0x0e000000
str r1, [r0]
@@ -65,7 +65,7 @@ reset:
* CSD1 not required, because the MX21ADS board only contains 64Mbyte.
* CS3 can therefore be made available.
*/
- ldr r0, =FMCR
+ ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR
ldr r1, =0xffffffc9
str r1, [r0]
@@ -79,7 +79,7 @@ reset:
1:
/* Precharge */
- ldr r0, =SDCTL0
+ ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0
ldr r1, =0x92120300
str r1, [r0]
ldr r2, =0xc0200000
@@ -113,7 +113,7 @@ reset:
str r1, [r0]
/* Set NFC_CLK to 24MHz */
- ldr r0, =PCDR0
+ ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0
ldr r1, =0x6419a007
str r1, [r0]
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 0b8ff22..1c4b550 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -71,70 +71,70 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
-/* AIPI */
-#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00)
-#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04)
-#define AIPI2_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x00)
-#define AIPI2_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x04)
-
-/* System Control */
-#define SUID0 __REG(MX21_SYSCTRL_BASE_ADDR + 0x4) /* Silicon ID Register (12 bytes) */
-#define SUID1 __REG(MX21_SYSCTRL_BASE_ADDR + 0x8) /* Silicon ID Register (12 bytes) */
-#define CID __REG(MX21_SYSCTRL_BASE_ADDR + 0xC) /* Silicon ID Register (12 bytes) */
-#define FMCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
-
-#define GPCR_BOOT_SHIFT 16
-#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
-#define GPCR_BOOT_UART_USB 0
-#define GPCR_BOOT_8BIT_NAND_2k 2
-#define GPCR_BOOT_16BIT_NAND_2k 3
-#define GPCR_BOOT_16BIT_NAND_512 4
-#define GPCR_BOOT_16BIT_CS0 5
-#define GPCR_BOOT_32BIT_CS0 6
-#define GPCR_BOOT_8BIT_NAND_512 7
-
-/* SDRAM Controller registers bitfields */
-#define SDCTL0 __REG(MX21_X_MEMC_BASE_ADDR + 0x00) /* SDRAM 0 Control Register */
-#define SDCTL1 __REG(MX21_X_MEMC_BASE_ADDR + 0x04) /* SDRAM 0 Control Register */
-#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
-#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */
-
-/* PLL registers */
-#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(MX21_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(MX21_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(MX21_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(MX21_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(MX21_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(MX21_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
-
-#define CSCR_MPEN (1 << 0)
-#define CSCR_SPEN (1 << 1)
-#define CSCR_FPM_EN (1 << 2)
-#define CSCR_OSC26M_DIS (1 << 3)
-#define CSCR_OSC26M_DIV1P5 (1 << 4)
-#define CSCR_MCU_SEL (1 << 16)
-#define CSCR_SP_SEL (1 << 17)
-#define CSCR_SD_CNT(d) (((d) & 0x3) << 24)
-#define CSCR_USB_DIV(d) (((d) & 0x7) << 26)
-#define CSCR_PRESC(d) (((d) & 0x7) << 29)
-
-#define MPCTL1_BRMO (1 << 6)
-#define MPCTL1_LF (1 << 15)
-
-#define PCCR0_PERCLK3_EN (1 << 18)
-#define PCCR0_NFC_EN (1 << 19)
-#define PCCR0_HCLK_LCDC_EN (1 << 26)
-
-#define PCCR1_GPT1_EN (1 << 25)
-
-#define CCSR_32K_SR (1 << 15)
+/* AIPI (base MX21_AIPI_BASE_ADDR) */
+#define MX21_AIPI1_PSR0 0x00
+#define MX21_AIPI1_PSR1 0x04
+#define MX21_AIPI2_PSR0 (0x20000 + 0x00)
+#define MX21_AIPI2_PSR1 (0x20000 + 0x04)
+
+/* System Control (base: MX21_SYSCTRL_BASE_ADDR) */
+#define MX21_SUID0 0x4 /* Silicon ID Register (12 bytes) */
+#define MX21_SUID1 0x8 /* Silicon ID Register (12 bytes) */
+#define MX21_CID 0xC /* Silicon ID Register (12 bytes) */
+#define MX21_FMCR 0x14 /* Function Multeplexing Control Register */
+#define MX21_GPCR 0x18 /* Global Peripheral Control Register */
+#define MX21_WBCR 0x1C /* Well Bias Control Register */
+#define MX21_DSCR(x) 0x1C + ((x) << 2) /* Driving Strength Control Register 1 - 13 */
+
+#define MX21_GPCR_BOOT_SHIFT 16
+#define MX21_GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
+#define MX21_GPCR_BOOT_UART_USB 0
+#define MX21_GPCR_BOOT_8BIT_NAND_2k 2
+#define MX21_GPCR_BOOT_16BIT_NAND_2k 3
+#define MX21_GPCR_BOOT_16BIT_NAND_512 4
+#define MX21_GPCR_BOOT_16BIT_CS0 5
+#define MX21_GPCR_BOOT_32BIT_CS0 6
+#define MX21_GPCR_BOOT_8BIT_NAND_512 7
+
+/* SDRAM Controller registers bitfields (base: MX21_X_MEMC_BASE_ADDR) */
+#define MX21_SDCTL0 0x00 /* SDRAM 0 Control Register */
+#define MX21_SDCTL1 0x04 /* SDRAM 0 Control Register */
+#define MX21_SDRST 0x18 /* SDRAM Reset Register */
+#define MX21_SDMISC 0x14 /* SDRAM Miscellaneous Register */
+
+/* PLL registers (base: MX21_CCM_BASE_ADDR) */
+#define MX21_CSCR 0x00 /* Clock Source Control Register */
+#define MX21_MPCTL0 0x04 /* MCU PLL Control Register 0 */
+#define MX21_MPCTL1 0x08 /* MCU PLL Control Register 1 */
+#define MX21_SPCTL0 0x0c /* System PLL Control Register 0 */
+#define MX21_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX21_OSC26MCTL 0x14 /* Oscillator 26M Register */
+#define MX21_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */
+#define MX21_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */
+#define MX21_PCCR0 0x20 /* Peripheral Clock Control Register 0 */
+#define MX21_PCCR1 0x24 /* Peripheral Clock Control Register 1 */
+#define MX21_CCSR 0x28 /* Clock Control Status Register */
+
+#define MX21_CSCR_MPEN (1 << 0)
+#define MX21_CSCR_SPEN (1 << 1)
+#define MX21_CSCR_FPM_EN (1 << 2)
+#define MX21_CSCR_OSC26M_DIS (1 << 3)
+#define MX21_CSCR_OSC26M_DIV1P5 (1 << 4)
+#define MX21_CSCR_MCU_SEL (1 << 16)
+#define MX21_CSCR_SP_SEL (1 << 17)
+#define MX21_CSCR_SD_CNT(d) (((d) & 0x3) << 24)
+#define MX21_CSCR_USB_DIV(d) (((d) & 0x7) << 26)
+#define MX21_CSCR_PRESC(d) (((d) & 0x7) << 29)
+
+#define MX21_MPCTL1_BRMO (1 << 6)
+#define MX21_MPCTL1_LF (1 << 15)
+
+#define MX21_PCCR0_PERCLK3_EN (1 << 18)
+#define MX21_PCCR0_NFC_EN (1 << 19)
+#define MX21_PCCR0_HCLK_LCDC_EN (1 << 26)
+
+#define MX21_PCCR1_GPT1_EN (1 << 25)
+
+#define MX21_CCSR_32K_SR (1 << 15)
#endif /* _IMX21_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 10/13] ARM i.MX27: Cleanup remaining unprefixed registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (8 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 09/13] ARM i.MX21: " Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 11/13] ARM i.MX27: move PCCR gate registers to its only user Sascha Hauer
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 7 +-
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 42 ++++----
arch/arm/boards/guf-neso/board.c | 6 +-
arch/arm/boards/guf-neso/lowlevel.c | 19 ++--
arch/arm/boards/guf-neso/pll_init.S | 37 +++----
arch/arm/boards/imx27ads/lowlevel_init.S | 28 +++---
arch/arm/boards/pcm038/lowlevel.c | 26 ++---
arch/arm/boards/pcm038/pcm038.c | 15 +--
arch/arm/boards/pcm038/pcm970.c | 23 +++--
arch/arm/boards/pcm038/pll.h | 54 +++++------
arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 40 ++++----
arch/arm/mach-imx/include/mach/imx27-regs.h | 107 ++++++++++-----------
12 files changed, 216 insertions(+), 188 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 57c04c4..4667e62 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -222,11 +222,16 @@ device_initcall(eukrea_cpuimx27_devices_init);
static int eukrea_cpuimx27_console_init(void)
{
+ uint32_t val;
+
#ifdef CONFIG_DRIVER_SERIAL_IMX
imx27_add_uart0();
#endif
/* configure 8 bit UART on cs3 */
- FMCR &= ~0x2;
+ val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
+ val &= ~0x2;
+ writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR);
+
imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
#ifdef CONFIG_DRIVER_SERIAL_NS16550
add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index eac9ecc..bab5c8c 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -25,11 +25,12 @@
/* Enable DDR SDRAM operation */
writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
- writel(0x55555555, DSCR(3)) /* Set the driving strength */
- writel(0x55555555, DSCR(5))
- writel(0x55555555, DSCR(6))
- writel(0x00005005, DSCR(7))
- writel(0x15555555, DSCR(8))
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
@@ -75,23 +76,26 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* disable mpll/spll */
- ldr r0, =CSCR
+ ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
-
+
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
- writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */
- writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */
- writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ /* MPLL = 399 MHz */
+ writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 240 MHz */
+ writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0)
+ writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
/* add some delay here */
mov r1, #0x1000
@@ -99,12 +103,14 @@ reset:
bne 1b
/* clock gating enable */
- writel(0x00050f08, GPCR)
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
/* peripheral clock divider */
- writel(0x130400c3, PCDR0) /* FIXME */
- writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */
- /* PERDIV1=04 @266 MHz */
+ /* FIXME */
+ writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0)
+ /* PERDIV1=08 @133 MHz */
+ writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1)
+ /* PERDIV1=04 @266 MHz */
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 7adee92..1b8db26 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -320,10 +320,10 @@ static int neso_pll(void)
pllfunc();
/* clock gating enable */
- GPCR = 0x00050f08;
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
+ writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
+ writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index eff1f8d..4c1cfeb 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -58,10 +58,10 @@ void __bare_init __naked reset(void)
common_reset();
/* ahb lite ip interface */
- AIPI1_PSR0 = 0x20040304;
- AIPI1_PSR1 = 0xDFFBFCFB;
- AIPI2_PSR0 = 0x00000000;
- AIPI2_PSR1 = 0xFFFFFFFF;
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -74,11 +74,12 @@ void __bare_init __naked reset(void)
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
- DSCR(3) = 0x55555555; /* Set the driving strength */
- DSCR(5) = 0x55555555;
- DSCR(6) = 0x55555555;
- DSCR(7) = 0x00005005;
- DSCR(8) = 0x15555555;
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S
index 87e5312..13df4a3 100644
--- a/arch/arm/boards/guf-neso/pll_init.S
+++ b/arch/arm/boards/guf-neso/pll_init.S
@@ -8,34 +8,37 @@
ldr r1, =val; \
str r1, [r0];
-#define CSCR_VAL CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_MCU_SEL | \
- CSCR_ARM_SRC_MPLL | \
- CSCR_SP_SEL | \
- CSCR_ARM_DIV(0) | \
- CSCR_FPM_EN | \
- CSCR_SPEN | \
- CSCR_MPEN | \
- CSCR_AHB_DIV(1)
+#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_MCU_SEL | \
+ MX27_CSCR_ARM_SRC_MPLL | \
+ MX27_CSCR_SP_SEL | \
+ MX27_CSCR_ARM_DIV(0) | \
+ MX27_CSCR_FPM_EN | \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN | \
+ MX27_CSCR_AHB_DIV(1)
ENTRY(neso_pll_init)
+ /* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
+ IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
+ IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
- writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
ldr r2, =16000
1:
diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S
index 1bebb1d..7c01558 100644
--- a/arch/arm/boards/imx27ads/lowlevel_init.S
+++ b/arch/arm/boards/imx27ads/lowlevel_init.S
@@ -118,13 +118,13 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* disable mpll/spll */
- ldr r0, =CSCR
+ ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
@@ -136,15 +136,16 @@ reset:
* with 1.2 V core voltage! Find out if this is
* documented somewhere.
*/
- writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */
- writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */
+ writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */
+ writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */
/*
* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
* System clock (HCLK) = 133 MHz
*/
- writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
+ writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
+ MX27_CCM_BASE_ADDR + MX27_CSCR)
/* add some delay here */
mov r1, #0x1000
@@ -152,13 +153,14 @@ reset:
bne 1b
/* clock gating enable */
- writel(0x00050f08, GPCR)
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
/* peripheral clock divider */
- writel(0x23C8F403, PCDR0) /* FIXME */
- writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */
- /* PERDIV1=04 @266 MHz *
- * /
+ /* FIXME */
+ writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0)
+ /* PERDIV1=08 @133 MHz */
+ /* PERDIV1=04 @266 MHz */
+ writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1)
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
bls 1f
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 2211e42..13639bc 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -58,10 +58,10 @@ void __bare_init __naked reset(void)
common_reset();
/* ahb lite ip interface */
- AIPI1_PSR0 = 0x20040304;
- AIPI1_PSR1 = 0xDFFBFCFB;
- AIPI2_PSR0 = 0x00000000;
- AIPI2_PSR1 = 0xFFFFFFFF;
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
@@ -69,9 +69,10 @@ void __bare_init __naked reset(void)
board_init_lowlevel_return();
/* re-program the PLL prior(!) starting the SDRAM controller */
- MPCTL0 = MPCTL0_VAL;
- SPCTL0 = SPCTL0_VAL;
- CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
+ writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0);
+ writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+ writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART |
+ MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR);
/*
* DDR on CSD0
@@ -79,11 +80,12 @@ void __bare_init __naked reset(void)
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
- DSCR(3) = 0x55555555; /* Set the driving strength */
- DSCR(5) = 0x55555555;
- DSCR(6) = 0x55555555;
- DSCR(7) = 0x00005005;
- DSCR(8) = 0x15555555;
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 7677bea..d6d1d01 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -112,8 +112,8 @@ static inline uint32_t get_pll_spctl10(void)
{
uint32_t reg;
- reg = SPCTL0;
- SPCTL0 = reg;
+ reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+ writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0);
return reg;
}
@@ -127,7 +127,8 @@ static int pcm038_power_init(void)
struct mc13xxx *mc13xxx = mc13xxx_get();
/* PLL registers already set to their final values? */
- if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
+ if (spctl0 == SPCTL0_VAL &&
+ readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) {
console_flush();
if (mc13xxx) {
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
@@ -162,9 +163,9 @@ static int pcm038_power_init(void)
/* wait for required power level to run the CPU at 400 MHz */
udelay(100000);
- CSCR = CSCR_VAL_FINAL;
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
+ writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR);
+ writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
+ writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
@@ -174,7 +175,7 @@ static int pcm038_power_init(void)
}
/* clock gating enable */
- GPCR = 0x00050f08;
+ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
return 0;
}
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index 5723fb3..8caed11 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -112,35 +112,38 @@ static void pcm970_ide_init(void)
mdelay(10);
/* Reset PCMCIA Status Change Register */
- writel(0x00000fff, PCMCIA_PSCR);
+ writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR);
mdelay(10);
/* Check PCMCIA Input Pins Register for Card Detect & Power */
- if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) {
+ if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) &
+ ((1 << 8) | (3 << 3))) != (1 << 8)) {
printf("CompactFlash card not found. Driver not enabled.\n");
return;
}
/* Disable all interrupts */
- writel(0, PCMCIA_PER);
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER);
/* Disable all PCMCIA banks */
for (i = 0; i < 5; i++)
- writel(0, PCMCIA_POR(i));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i));
/* Not use internal PCOE */
- writel(0, PCMCIA_PGCR);
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR);
/* Setup PCMCIA bank0 for Common memory mode */
- writel(0, PCMCIA_PBR(0));
- writel(0, PCMCIA_POFR(0));
- writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0));
+ writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0));
+ writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf,
+ MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
/* Clear PCMCIA General Status Register */
- writel(0x0000001f, PCMCIA_PGSR);
+ writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR);
/* Make PCMCIA bank0 valid */
- writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0));
+ writel(readl(MX27_PCMCIA_POR(0)) | (1 << 29),
+ MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
platform_device_register(&pcm970_ide_device);
}
diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h
index a7da4a4..8bdb76d 100644
--- a/arch/arm/boards/pcm038/pll.h
+++ b/arch/arm/boards/pcm038/pll.h
@@ -22,35 +22,35 @@
/* define the PLL setting we want to run the system */
/* main clock divider settings immediately after reset (at 1.25 V core supply) */
-#define CSCR_VAL (CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_SP_SEL | /* 26 MHz reference */ \
- CSCR_MCU_SEL | /* 26 MHz reference */ \
- CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
- CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
- CSCR_FPM_EN | \
- CSCR_SPEN | \
- CSCR_MPEN)
+#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_SP_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
+ MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ MX27_CSCR_FPM_EN | \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN)
/* main clock divider settings after core voltage increases to 1.45 V */
-#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_SP_SEL | /* 26 MHz reference */ \
- CSCR_MCU_SEL | /* 26 MHz reference */ \
- CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
- CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
- CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
- CSCR_FPM_EN | /* do not disable it! */ \
- CSCR_SPEN | \
- CSCR_MPEN)
+#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \
+ MX27_CSCR_SD_CNT(3) | \
+ MX27_CSCR_MSHC_SEL | \
+ MX27_CSCR_H264_SEL | \
+ MX27_CSCR_SSI1_SEL | \
+ MX27_CSCR_SSI2_SEL | \
+ MX27_CSCR_SP_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \
+ MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
+ MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
+ MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ MX27_CSCR_FPM_EN | /* do not disable it! */ \
+ MX27_CSCR_SPEN | \
+ MX27_CSCR_MPEN)
/* MPLL should provide a 399 MHz clock from the 26 MHz reference */
#define MPCTL0_VAL (IMX_PLL_PD(0) | \
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index 4b9add9..60393c6 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -24,11 +24,12 @@
/* Enable DDR SDRAM operation */
writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
- writel(0x55555555, DSCR(3)) /* Set the driving strength */
- writel(0x55555555, DSCR(5))
- writel(0x55555555, DSCR(6))
- writel(0x00005005, DSCR(7))
- writel(0x15555555, DSCR(8))
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
/* Initial reset */
writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
@@ -69,10 +70,10 @@ reset:
common_reset r0
/* ahb lite ip interface */
- writel(0x20040304, AIPI1_PSR0)
- writel(0xDFFBFCFB, AIPI1_PSR1)
- writel(0x00000000, AIPI2_PSR0)
- writel(0xFFFFFFFF, AIPI2_PSR1)
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
+ writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
+ writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
@@ -83,21 +84,26 @@ reset:
b board_init_lowlevel_return
1:
+ /* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
+ IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
+ /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
-
- writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL |
- CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN |
- CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) |
- CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL |
- CSCR_MSHC_SEL, CSCR)
+ IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
+
+ writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
+ MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
+ MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
+ MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
+ MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
+ MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
+ MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
+ MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR)
sdram_init
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index a9658fa..ff8d509 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -101,65 +101,66 @@
/* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
-#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00)
-#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04)
-#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08)
-#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2))
-#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2))
-#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2))
-#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60)
-#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64)
+/* PCMCIA (base: MX27_PCMCIA_CTL_BASE_ADDR) */
+#define MX27_PCMCIA_PIPR 0x00
+#define MX27_PCMCIA_PSCR 0x04
+#define MX27_PCMCIA_PER 0x08
+#define MX27_PCMCIA_PBR(x) (0x0c + ((x) << 2))
+#define MX27_PCMCIA_POR(x) (0x28 + ((x) << 2))
+#define MX27_PCMCIA_POFR(x) (0x44 + ((x) << 2))
+#define MX27_PCMCIA_PGCR 0x60
+#define MX27_PCMCIA_PGSR 0x64
-/* AIPI */
-#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00)
-#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04)
-#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00)
-#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04)
+/* AIPI (base: MX27_AIPI_BASE_ADDR) */
+#define MX27_AIPI1_PSR0 0x00
+#define MX27_AIPI1_PSR1 0x04
+#define MX27_AIPI2_PSR0 (0x20000 + 0x00)
+#define MX27_AIPI2_PSR1 (0x20000 + 0x04)
-/* System Control */
-#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */
-#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
-#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
-#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
-#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
+/* System Control (base: MX27_SYSCTRL_BASE_ADDR) */
+#define MX27_CID 0x0 /* Chip ID Register */
+#define MX27_FMCR 0x14 /* Function Multeplexing Control Register */
+#define MX27_GPCR 0x18 /* Global Peripheral Control Register */
+#define MX27_WBCR 0x1C /* Well Bias Control Register */
+#define MX27_DSCR(x) (0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
#include "esdctl.h"
-/* PLL registers */
-#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
-#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
-#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
-#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
-#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
-#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
-#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
-#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
-#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
-#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
+/* PLL registers (base: MX27_CCM_BASE_ADDR) */
+#define MX27_CSCR 0x00 /* Clock Source Control Register */
+#define MX27_MPCTL0 0x04 /* MCU PLL Control Register 0 */
+#define MX27_MPCTL1 0x08 /* MCU PLL Control Register 1 */
+#define MX27_SPCTL0 0x0c /* System PLL Control Register 0 */
+#define MX27_SPCTL1 0x10 /* System PLL Control Register 1 */
+#define MX27_OSC26MCTL 0x14 /* Oscillator 26M Register */
+#define MX27_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */
+#define MX27_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */
+#define MX27_PCCR0 0x20 /* Peripheral Clock Control Register 0 */
+#define MX27_PCCR1 0x24 /* Peripheral Clock Control Register 1 */
+#define MX27_CCSR 0x28 /* Clock Control Status Register */
-#define CSCR_MPEN (1 << 0)
-#define CSCR_SPEN (1 << 1)
-#define CSCR_FPM_EN (1 << 2)
-#define CSCR_OSC26M_DIS (1 << 3)
-#define CSCR_OSC26M_DIV1P5 (1 << 4)
-#define CSCR_AHB_DIV(d) (((d) & 0x3) << 8)
-#define CSCR_ARM_DIV(d) (((d) & 0x3) << 12)
-#define CSCR_ARM_SRC_MPLL (1 << 15)
-#define CSCR_MCU_SEL (1 << 16)
-#define CSCR_SP_SEL (1 << 17)
-#define CSCR_MPLL_RESTART (1 << 18)
-#define CSCR_SPLL_RESTART (1 << 19)
-#define CSCR_MSHC_SEL (1 << 20)
-#define CSCR_H264_SEL (1 << 21)
-#define CSCR_SSI1_SEL (1 << 22)
-#define CSCR_SSI2_SEL (1 << 23)
-#define CSCR_SD_CNT(d) (((d) & 0x3) << 24)
-#define CSCR_USB_DIV(d) (((d) & 0x7) << 28)
-#define CSCR_UPDATE_DIS (1 << 31)
+#define MX27_CSCR_MPEN (1 << 0)
+#define MX27_CSCR_SPEN (1 << 1)
+#define MX27_CSCR_FPM_EN (1 << 2)
+#define MX27_CSCR_OSC26M_DIS (1 << 3)
+#define MX27_CSCR_OSC26M_DIV1P5 (1 << 4)
+#define MX27_CSCR_AHB_DIV(d) (((d) & 0x3) << 8)
+#define MX27_CSCR_ARM_DIV(d) (((d) & 0x3) << 12)
+#define MX27_CSCR_ARM_SRC_MPLL (1 << 15)
+#define MX27_CSCR_MCU_SEL (1 << 16)
+#define MX27_CSCR_SP_SEL (1 << 17)
+#define MX27_CSCR_MPLL_RESTART (1 << 18)
+#define MX27_CSCR_SPLL_RESTART (1 << 19)
+#define MX27_CSCR_MSHC_SEL (1 << 20)
+#define MX27_CSCR_H264_SEL (1 << 21)
+#define MX27_CSCR_SSI1_SEL (1 << 22)
+#define MX27_CSCR_SSI2_SEL (1 << 23)
+#define MX27_CSCR_SD_CNT(d) (((d) & 0x3) << 24)
+#define MX27_CSCR_USB_DIV(d) (((d) & 0x7) << 28)
+#define MX27_CSCR_UPDATE_DIS (1 << 31)
-#define MPCTL1_BRMO (1 << 6)
-#define MPCTL1_LF (1 << 15)
+#define MX27_MPCTL1_BRMO (1 << 6)
+#define MX27_MPCTL1_LF (1 << 15)
#define PCCR0_SSI2_EN (1 << 0)
#define PCCR0_SSI1_EN (1 << 1)
@@ -224,8 +225,6 @@
#define PCCR1_UART2_EN (1 << 30)
#define PCCR1_UART1_EN (1 << 31)
-#define CCSR_32K_SR (1 << 15)
-
/* SDRAM Controller registers bitfields */
#define ESDCTL_PRCT(x) (((x) & 3f) << 0)
#define ESDCTL_BL (1 << 7)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 11/13] ARM i.MX27: move PCCR gate registers to its only user
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (9 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 10/13] ARM i.MX27: " Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 12/13] ARM i.MX27: remove duplicate ESDCTL registers Sascha Hauer
2012-10-11 7:13 ` [PATCH 13/13] ARM i.MX: get rid of imx-regs.h Sascha Hauer
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx27.c | 63 +++++++++++++++++++++++++++
arch/arm/mach-imx/include/mach/imx27-regs.h | 63 ---------------------------
2 files changed, 63 insertions(+), 63 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index cb42585..222d2a6 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -27,6 +27,69 @@
#define CCM_PMCOUNT 0x30
#define CCM_WKGDCTL 0x34
+#define PCCR0_SSI2_EN (1 << 0)
+#define PCCR0_SSI1_EN (1 << 1)
+#define PCCR0_SLCDC_EN (1 << 2)
+#define PCCR0_SDHC3_EN (1 << 3)
+#define PCCR0_SDHC2_EN (1 << 4)
+#define PCCR0_SDHC1_EN (1 << 5)
+#define PCCR0_SDC_EN (1 << 6)
+#define PCCR0_SAHARA_EN (1 << 7)
+#define PCCR0_RTIC_EN (1 << 8)
+#define PCCR0_RTC_EN (1 << 9)
+#define PCCR0_PWM_EN (1 << 11)
+#define PCCR0_OWIRE_EN (1 << 12)
+#define PCCR0_MSHC_EN (1 << 13)
+#define PCCR0_LCDC_EN (1 << 14)
+#define PCCR0_KPP_EN (1 << 15)
+#define PCCR0_IIM_EN (1 << 16)
+#define PCCR0_I2C2_EN (1 << 17)
+#define PCCR0_I2C1_EN (1 << 18)
+#define PCCR0_GPT6_EN (1 << 19)
+#define PCCR0_GPT5_EN (1 << 20)
+#define PCCR0_GPT4_EN (1 << 21)
+#define PCCR0_GPT3_EN (1 << 22)
+#define PCCR0_GPT2_EN (1 << 23)
+#define PCCR0_GPT1_EN (1 << 24)
+#define PCCR0_GPIO_EN (1 << 25)
+#define PCCR0_FEC_EN (1 << 26)
+#define PCCR0_EMMA_EN (1 << 27)
+#define PCCR0_DMA_EN (1 << 28)
+#define PCCR0_CSPI3_EN (1 << 29)
+#define PCCR0_CSPI2_EN (1 << 30)
+#define PCCR0_CSPI1_EN (1 << 31)
+
+#define PCCR1_MSHC_BAUDEN (1 << 2)
+#define PCCR1_NFC_BAUDEN (1 << 3)
+#define PCCR1_SSI2_BAUDEN (1 << 4)
+#define PCCR1_SSI1_BAUDEN (1 << 5)
+#define PCCR1_H264_BAUDEN (1 << 6)
+#define PCCR1_PERCLK4_EN (1 << 7)
+#define PCCR1_PERCLK3_EN (1 << 8)
+#define PCCR1_PERCLK2_EN (1 << 9)
+#define PCCR1_PERCLK1_EN (1 << 10)
+#define PCCR1_HCLK_USB (1 << 11)
+#define PCCR1_HCLK_SLCDC (1 << 12)
+#define PCCR1_HCLK_SAHARA (1 << 13)
+#define PCCR1_HCLK_RTIC (1 << 14)
+#define PCCR1_HCLK_LCDC (1 << 15)
+#define PCCR1_HCLK_H264 (1 << 16)
+#define PCCR1_HCLK_FEC (1 << 17)
+#define PCCR1_HCLK_EMMA (1 << 18)
+#define PCCR1_HCLK_EMI (1 << 19)
+#define PCCR1_HCLK_DMA (1 << 20)
+#define PCCR1_HCLK_CSI (1 << 21)
+#define PCCR1_HCLK_BROM (1 << 22)
+#define PCCR1_HCLK_ATA (1 << 23)
+#define PCCR1_WDT_EN (1 << 24)
+#define PCCR1_USB_EN (1 << 25)
+#define PCCR1_UART6_EN (1 << 26)
+#define PCCR1_UART5_EN (1 << 27)
+#define PCCR1_UART4_EN (1 << 28)
+#define PCCR1_UART3_EN (1 << 29)
+#define PCCR1_UART2_EN (1 << 30)
+#define PCCR1_UART1_EN (1 << 31)
+
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index ff8d509..1f4a743 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -162,69 +162,6 @@
#define MX27_MPCTL1_BRMO (1 << 6)
#define MX27_MPCTL1_LF (1 << 15)
-#define PCCR0_SSI2_EN (1 << 0)
-#define PCCR0_SSI1_EN (1 << 1)
-#define PCCR0_SLCDC_EN (1 << 2)
-#define PCCR0_SDHC3_EN (1 << 3)
-#define PCCR0_SDHC2_EN (1 << 4)
-#define PCCR0_SDHC1_EN (1 << 5)
-#define PCCR0_SDC_EN (1 << 6)
-#define PCCR0_SAHARA_EN (1 << 7)
-#define PCCR0_RTIC_EN (1 << 8)
-#define PCCR0_RTC_EN (1 << 9)
-#define PCCR0_PWM_EN (1 << 11)
-#define PCCR0_OWIRE_EN (1 << 12)
-#define PCCR0_MSHC_EN (1 << 13)
-#define PCCR0_LCDC_EN (1 << 14)
-#define PCCR0_KPP_EN (1 << 15)
-#define PCCR0_IIM_EN (1 << 16)
-#define PCCR0_I2C2_EN (1 << 17)
-#define PCCR0_I2C1_EN (1 << 18)
-#define PCCR0_GPT6_EN (1 << 19)
-#define PCCR0_GPT5_EN (1 << 20)
-#define PCCR0_GPT4_EN (1 << 21)
-#define PCCR0_GPT3_EN (1 << 22)
-#define PCCR0_GPT2_EN (1 << 23)
-#define PCCR0_GPT1_EN (1 << 24)
-#define PCCR0_GPIO_EN (1 << 25)
-#define PCCR0_FEC_EN (1 << 26)
-#define PCCR0_EMMA_EN (1 << 27)
-#define PCCR0_DMA_EN (1 << 28)
-#define PCCR0_CSPI3_EN (1 << 29)
-#define PCCR0_CSPI2_EN (1 << 30)
-#define PCCR0_CSPI1_EN (1 << 31)
-
-#define PCCR1_MSHC_BAUDEN (1 << 2)
-#define PCCR1_NFC_BAUDEN (1 << 3)
-#define PCCR1_SSI2_BAUDEN (1 << 4)
-#define PCCR1_SSI1_BAUDEN (1 << 5)
-#define PCCR1_H264_BAUDEN (1 << 6)
-#define PCCR1_PERCLK4_EN (1 << 7)
-#define PCCR1_PERCLK3_EN (1 << 8)
-#define PCCR1_PERCLK2_EN (1 << 9)
-#define PCCR1_PERCLK1_EN (1 << 10)
-#define PCCR1_HCLK_USB (1 << 11)
-#define PCCR1_HCLK_SLCDC (1 << 12)
-#define PCCR1_HCLK_SAHARA (1 << 13)
-#define PCCR1_HCLK_RTIC (1 << 14)
-#define PCCR1_HCLK_LCDC (1 << 15)
-#define PCCR1_HCLK_H264 (1 << 16)
-#define PCCR1_HCLK_FEC (1 << 17)
-#define PCCR1_HCLK_EMMA (1 << 18)
-#define PCCR1_HCLK_EMI (1 << 19)
-#define PCCR1_HCLK_DMA (1 << 20)
-#define PCCR1_HCLK_CSI (1 << 21)
-#define PCCR1_HCLK_BROM (1 << 22)
-#define PCCR1_HCLK_ATA (1 << 23)
-#define PCCR1_WDT_EN (1 << 24)
-#define PCCR1_USB_EN (1 << 25)
-#define PCCR1_UART6_EN (1 << 26)
-#define PCCR1_UART5_EN (1 << 27)
-#define PCCR1_UART4_EN (1 << 28)
-#define PCCR1_UART3_EN (1 << 29)
-#define PCCR1_UART2_EN (1 << 30)
-#define PCCR1_UART1_EN (1 << 31)
-
/* SDRAM Controller registers bitfields */
#define ESDCTL_PRCT(x) (((x) & 3f) << 0)
#define ESDCTL_BL (1 << 7)
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 12/13] ARM i.MX27: remove duplicate ESDCTL registers
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (10 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 11/13] ARM i.MX27: move PCCR gate registers to its only user Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
2012-10-11 7:13 ` [PATCH 13/13] ARM i.MX: get rid of imx-regs.h Sascha Hauer
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 5 ++--
arch/arm/mach-imx/include/mach/imx27-regs.h | 36 -----------------------
2 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index bab5c8c..be9a4f4 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -1,6 +1,7 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
#include <mach/imx-regs.h>
+#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
#define writel(val, reg) \
@@ -9,10 +10,10 @@
str r1, [r0];
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
-#define ROWS0 ESDCTL_ROW14
+#define ROWS0 ESDCTL0_ROW14
#define CFG0 0x0029572D
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
-#define ROWS0 ESDCTL_ROW13
+#define ROWS0 ESDCTL0_ROW13
#define CFG0 0x00095728
#endif
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 1f4a743..90b4614 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -162,40 +162,4 @@
#define MX27_MPCTL1_BRMO (1 << 6)
#define MX27_MPCTL1_LF (1 << 15)
-/* SDRAM Controller registers bitfields */
-#define ESDCTL_PRCT(x) (((x) & 3f) << 0)
-#define ESDCTL_BL (1 << 7)
-#define ESDCTL_FP (1 << 8)
-#define ESDCTL_PWDT(x) (((x) & 3) << 10)
-#define ESDCTL_SREFR(x) (((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER (0 << 16)
-#define ESDCTL_DSIZ_16_LOWER (0 << 16)
-#define ESDCTL_DSIZ_32 (0 << 16)
-#define ESDCTL_COL8 (0 << 20)
-#define ESDCTL_COL9 (1 << 20)
-#define ESDCTL_COL10 (2 << 20)
-#define ESDCTL_ROW11 (0 << 24)
-#define ESDCTL_ROW12 (1 << 24)
-#define ESDCTL_ROW13 (2 << 24)
-#define ESDCTL_ROW14 (3 << 24)
-#define ESDCTL_ROW15 (4 << 24)
-#define ESDCTL_SP (1 << 27)
-#define ESDCTL_SMODE_NORMAL (0 << 28)
-#define ESDCTL_SMODE_PRECHAGRE (1 << 28)
-#define ESDCTL_SMODE_AUTO_REF (2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
-#define ESDCTL_SMODE_MAN_REF (4 << 28)
-#define ESDCTL_SDE (1 << 31)
-
-#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
-#define ESDCFG_TWR (1 << 15)
-#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
-#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
-#define ESDCFG_TWTR (1 << 20)
-#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
-
#endif /* _IMX27_REGS_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 13/13] ARM i.MX: get rid of imx-regs.h
2012-10-11 7:13 [PATCH] Final i.MX register cleanup Sascha Hauer
` (11 preceding siblings ...)
2012-10-11 7:13 ` [PATCH 12/13] ARM i.MX27: remove duplicate ESDCTL registers Sascha Hauer
@ 2012-10-11 7:13 ` Sascha Hauer
12 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-10-11 7:13 UTC (permalink / raw)
To: barebox
- remove now unused __REG definitions
- include individual SoC register files instead of imx-regs.h
- move IMX_GPIO_NR to generic.h
- finally remove imx-regs.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/ccxmx51/ccxmx51.c | 2 +-
arch/arm/boards/ccxmx51/ccxmx51js.c | 2 +-
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 2 +-
| 2 +-
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 2 +-
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 2 +-
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 2 +-
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c | 2 +-
| 2 +-
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 2 +-
arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 2 +-
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 2 +-
.../boards/freescale-mx25-3-stack/lowlevel_init.S | 2 +-
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 2 +-
| 2 +-
.../boards/freescale-mx35-3-stack/lowlevel_init.S | 2 +-
arch/arm/boards/freescale-mx51-pdk/board.c | 2 +-
arch/arm/boards/freescale-mx53-loco/board.c | 2 +-
arch/arm/boards/freescale-mx53-smd/board.c | 2 +-
arch/arm/boards/freescale-mx6-arm2/board.c | 2 +-
arch/arm/boards/freescale-mx6-sabrelite/board.c | 2 +-
arch/arm/boards/guf-cupid/board.c | 2 +-
arch/arm/boards/guf-cupid/lowlevel.c | 2 +-
arch/arm/boards/guf-neso/board.c | 2 +-
arch/arm/boards/guf-neso/lowlevel.c | 2 +-
arch/arm/boards/guf-neso/pll_init.S | 2 +-
arch/arm/boards/imx21ads/imx21ads.c | 2 +-
arch/arm/boards/imx21ads/lowlevel_init.S | 2 +-
arch/arm/boards/imx27ads/imx27ads.c | 2 +-
arch/arm/boards/imx27ads/lowlevel_init.S | 2 +-
arch/arm/boards/karo-tx25/board.c | 2 +-
arch/arm/boards/karo-tx25/lowlevel.c | 2 +-
arch/arm/boards/karo-tx51/tx51.c | 2 +-
arch/arm/boards/karo-tx53/board.c | 2 +-
arch/arm/boards/pcm037/lowlevel_init.S | 2 +-
arch/arm/boards/pcm037/pcm037.c | 2 +-
arch/arm/boards/pcm038/lowlevel.c | 2 +-
arch/arm/boards/pcm038/pcm038.c | 2 +-
arch/arm/boards/pcm038/pcm970.c | 2 +-
arch/arm/boards/pcm043/lowlevel.c | 2 +-
arch/arm/boards/pcm043/pcm043.c | 2 +-
arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 2 +-
arch/arm/boards/phycard-i.MX27/pca100.c | 2 +-
arch/arm/boards/scb9328/lowlevel_init.S | 2 +-
arch/arm/boards/scb9328/scb9328.c | 2 +-
arch/arm/boards/tqma53/board.c | 2 +-
arch/arm/mach-imx/clk-imx5.c | 3 +-
arch/arm/mach-imx/clk-pllv2.c | 1 -
arch/arm/mach-imx/clk-pllv3.c | 1 -
arch/arm/mach-imx/clocksource.c | 1 -
arch/arm/mach-imx/external-nand-boot.c | 6 +-
arch/arm/mach-imx/gpio.c | 1 -
arch/arm/mach-imx/imx1.c | 2 +-
arch/arm/mach-imx/imx21.c | 2 +-
arch/arm/mach-imx/imx25.c | 2 +-
arch/arm/mach-imx/imx31.c | 2 +-
arch/arm/mach-imx/imx35.c | 2 +-
arch/arm/mach-imx/imx51.c | 2 +-
arch/arm/mach-imx/imx53.c | 2 +-
arch/arm/mach-imx/include/mach/devices-imx31.h | 2 +-
arch/arm/mach-imx/include/mach/generic.h | 4 ++
arch/arm/mach-imx/include/mach/imx-regs.h | 64 --------------------
arch/arm/mach-imx/iomux-v3.c | 1 -
arch/arm/mach-imx/nand.c | 5 +-
drivers/mtd/nand/nand_imx.c | 1 -
drivers/net/fec_imx.c | 1 -
drivers/serial/serial_imx.c | 1 -
drivers/video/imx-ipu-fb.c | 2 +-
drivers/video/imx.c | 1 -
69 files changed, 70 insertions(+), 131 deletions(-)
delete mode 100644 arch/arm/mach-imx/include/mach/imx-regs.h
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index b391df1..a8d172c 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -23,7 +23,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c
index f04615d..c947a1e 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51js.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51js.c
@@ -20,7 +20,7 @@
#include <init.h>
#include <mci.h>
#include <asm/armlinux.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
#include <generated/mach-types.h>
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 39ed3b0..92e8df2 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -22,7 +22,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm/barebox-arm.h>
#include <asm-generic/sections.h>
--git a/arch/arm/boards/eukrea_cpuimx25/flash_header.c b/arch/arm/boards/eukrea_cpuimx25/flash_header.c
index 344c7ff..9102c2a 100644
--- a/arch/arm/boards/eukrea_cpuimx25/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx25/flash_header.c
@@ -23,7 +23,7 @@
*/
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index 61105a7..303da29 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -19,7 +19,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <io.h>
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 4667e62..c89ce8a 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -21,7 +21,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <notifier.h>
#include <mach/gpio.h>
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index be9a4f4..4ee6efb 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -1,6 +1,6 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 5d8830b..fdbc26a 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -41,7 +41,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/imx-ipu-fb.h>
--git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 26752d1..6fa9c8b 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index c6ab3be..e38a0b5 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index 1279f89..ab0ff81 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -19,7 +19,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index 8b3c43d..5ce2f8e 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -21,7 +21,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index 6635571..fb98099 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -18,7 +18,7 @@
*/
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 4c79317..7da031a 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -41,7 +41,7 @@
#include <mach/gpio.h>
#include <mach/weim.h>
#include <mach/imx-nand.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/imx-ipu-fb.h>
--git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
index 66763db..076b816 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <mach/imx-flash-header.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index bd3dd7f..dada5f3 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -17,7 +17,7 @@
*
*/
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index 61e635a..0adceac 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -17,7 +17,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index 8e9b030..0678e0a 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -27,7 +27,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index 0483103..a5ad009 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -27,7 +27,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c
index ccc7318..ce9874d 100644
--- a/arch/arm/boards/freescale-mx6-arm2/board.c
+++ b/arch/arm/boards/freescale-mx6-arm2/board.c
@@ -15,7 +15,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx6-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c
index cbfa3b4..da37e17 100644
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@@ -17,7 +17,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx6-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index e36fee8..5b17326 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -25,7 +25,7 @@
#include <driver.h>
#include <environment.h>
#include <fs.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <io.h>
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index 22ebaa0..5d6dfc5 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 1b8db26..200a2ef 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -35,7 +35,7 @@
#include <mach/gpio.h>
#include <mach/spi.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/iomux-mx27.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index 4c1cfeb..8c351f6 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S
index 13df4a3..4c6cb67 100644
--- a/arch/arm/boards/guf-neso/pll_init.S
+++ b/arch/arm/boards/guf-neso/pll_init.S
@@ -1,5 +1,5 @@
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <linux/linkage.h>
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index c4f44e9..ca566c8 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -21,7 +21,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index be1199b..e52cac1 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -15,7 +15,7 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <asm/barebox-arm-head.h>
.section ".text_bare_init","ax"
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index 22c6e40..f41b155 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <asm/armlinux.h>
#include <io.h>
#include <fec.h>
diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S
index 7c01558..2dc34b5 100644
--- a/arch/arm/boards/imx27ads/lowlevel_init.S
+++ b/arch/arm/boards/imx27ads/lowlevel_init.S
@@ -5,7 +5,7 @@
*/
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <asm/barebox-arm-head.h>
#define writel(val, reg) \
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 5c7b28b..1ffd890 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -21,7 +21,7 @@
#include <init.h>
#include <driver.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 0689f83..4250cc7 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/esdctl.h>
#include <io.h>
#include <mach/imx-nand.h>
diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c
index 3ee0ebd..dd377c1 100644
--- a/arch/arm/boards/karo-tx51/tx51.c
+++ b/arch/arm/boards/karo-tx51/tx51.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c
index c8509be..9829a8f 100644
--- a/arch/arm/boards/karo-tx53/board.c
+++ b/arch/arm/boards/karo-tx53/board.c
@@ -25,7 +25,7 @@
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index 283ea54..f9ecce1 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -17,7 +17,7 @@
*
*/
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/imx-pll.h>
#include <asm/barebox-arm-head.h>
#include <mach/esdctl.h>
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 79ea1dc..ff4089a 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -24,7 +24,7 @@
#include <fs.h>
#include <environment.h>
#include <usb/ulpi.h>
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/iomux-mx31.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 13639bc..a2da3cb 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <io.h>
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index d6d1d01..715d604 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <notifier.h>
#include <mach/gpio.h>
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
index 8caed11..93a1839 100644
--- a/arch/arm/boards/pcm038/pcm970.c
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -16,7 +16,7 @@
#include <init.h>
#include <sizes.h>
#include <platform_ide.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/iomux-mx27.h>
#include <mach/weim.h>
#include <mach/gpio.h>
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 58c0840..3db0f8c 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -18,7 +18,7 @@
*/
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index b0d48ba..abfeaf1 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -26,7 +26,7 @@
#include <environment.h>
#include <fs.h>
#include <sizes.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <io.h>
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index 60393c6..8f0000f 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -5,7 +5,7 @@
*/
#include <config.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
#include <asm/barebox-arm-head.h>
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index b8abd1b..0b66b04 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -18,7 +18,7 @@
#include <net.h>
#include <init.h>
#include <environment.h>
-#include <mach/imx-regs.h>
+#include <mach/imx27-regs.h>
#include <fec.h>
#include <mach/gpio.h>
#include <asm/armlinux.h>
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index c303d2d..cefac84 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <asm/barebox-arm-head.h>
#define CPU200
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index fd2758c..c70852c 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -19,7 +19,7 @@
#include <init.h>
#include <environment.h>
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <mach/weim.h>
diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 8c3d855..77535b5 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -30,7 +30,7 @@
#include <asm/mmu.h>
#include <generated/mach-types.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index 03a1843..050842d 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -13,7 +13,8 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
+#include <mach/imx53-regs.h>
#include "clk.h"
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index 6907269..7e087c1 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -17,7 +17,6 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
#include <malloc.h>
#include <asm-generic/div64.h>
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index a99eec5..e337e87 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -17,7 +17,6 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
#include <malloc.h>
#include <clock.h>
#include <asm-generic/div64.h>
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index cc7c38f..e18685e 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -32,7 +32,6 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <notifier.h>
-#include <mach/imx-regs.h>
#include <io.h>
/* Part 1: Registers */
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index d3f2637..2e9e475 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -17,7 +17,11 @@
#include <linux/mtd/nand.h>
#include <mach/imx-nand.h>
#include <mach/generic.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
+#include <mach/imx25-regs.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx31-regs.h>
+#include <mach/imx35-regs.h>
static void __bare_init noinline imx_nandboot_wait_op_done(void *regs)
{
diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c
index cd7655a..1bf4100 100644
--- a/arch/arm/mach-imx/gpio.c
+++ b/arch/arm/mach-imx/gpio.c
@@ -23,7 +23,6 @@
#include <common.h>
#include <errno.h>
#include <io.h>
-#include <mach/imx-regs.h>
#include <gpio.h>
#include <init.h>
diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c
index 966a8c2..18901ea 100644
--- a/arch/arm/mach-imx/imx1.c
+++ b/arch/arm/mach-imx/imx1.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx1-regs.h>
#include <mach/weim.h>
#include <mach/iomux-v1.h>
#include <reset_source.h>
diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c
index 417ada3..cddf3c0 100644
--- a/arch/arm/mach-imx/imx21.c
+++ b/arch/arm/mach-imx/imx21.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
#include <mach/weim.h>
#include <mach/iomux-v1.h>
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 0f92b17..3bd95c1 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <init.h>
-#include <mach/imx-regs.h>
+#include <mach/imx25-regs.h>
#include <mach/iim.h>
#include <io.h>
#include <mach/weim.h>
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 71b4c33..b2f0724 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -15,7 +15,7 @@
#include <init.h>
#include <sizes.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/weim.h>
void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 5560157..737eb3a 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -16,7 +16,7 @@
#include <init.h>
#include <io.h>
#include <mach/weim.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <mach/iim.h>
#include <mach/revision.h>
#include <mach/generic.h>
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 60c8885..cf6230b 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -17,7 +17,7 @@
#include <environment.h>
#include <io.h>
#include <mach/imx5.h>
-#include <mach/imx-regs.h>
+#include <mach/imx51-regs.h>
#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 0a4de83..38b94fc 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -17,7 +17,7 @@
#include <notifier.h>
#include <sizes.h>
#include <mach/imx5.h>
-#include <mach/imx-regs.h>
+#include <mach/imx53-regs.h>
#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
index 72167b0..fe71930 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx31.h
@@ -1,5 +1,5 @@
-#include <mach/imx-regs.h>
+#include <mach/imx31-regs.h>
#include <mach/devices.h>
static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata)
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 7fe5810..86966e4 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -19,6 +19,10 @@ int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type);
void imx_27_boot_save_loc(void __iomem *sysctrl_base);
int imx51_boot_save_loc(void __iomem *src_base);
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
+
#ifdef CONFIG_ARCH_IMX1
#define cpu_is_mx1() (1)
#else
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
deleted file mode 100644
index 4acee24..0000000
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-/* ------------------------------------------------------------------------
- * Motorola IMX system registers
- * ------------------------------------------------------------------------
- */
-
-# ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 *)(x)))
-# define __REG16(x) (*(volatile u16 *)(x))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# define __REG16(x) (x)
-# define __REG2(x,y) ((x)+(y))
-#endif
-
-#ifdef CONFIG_ARCH_IMX1
-# include <mach/imx1-regs.h>
-#elif defined CONFIG_ARCH_IMX21
-# include <mach/imx21-regs.h>
-#elif defined CONFIG_ARCH_IMX27
-# include <mach/imx27-regs.h>
-#elif defined CONFIG_ARCH_IMX31
-# include <mach/imx31-regs.h>
-#elif defined CONFIG_ARCH_IMX35
-# include <mach/imx35-regs.h>
-#elif defined CONFIG_ARCH_IMX25
-# include <mach/imx25-regs.h>
-#elif defined CONFIG_ARCH_IMX51
-# include <mach/imx51-regs.h>
-#elif defined CONFIG_ARCH_IMX53
-# include <mach/imx53-regs.h>
-#elif defined CONFIG_ARCH_IMX6
-# include <mach/imx6-regs.h>
-#else
-# error "unknown i.MX soc type"
-#endif
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-
-#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9153ead..8a6064d 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -18,7 +18,6 @@
#include <init.h>
#include <io.h>
#include <mach/iomux-v3.h>
-#include <mach/imx-regs.h>
static void __iomem *base;
diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c
index e793015..f298a36 100644
--- a/arch/arm/mach-imx/nand.c
+++ b/arch/arm/mach-imx/nand.c
@@ -13,7 +13,10 @@
#include <common.h>
#include <mach/generic.h>
-#include <mach/imx-regs.h>
+#include <mach/imx21-regs.h>
+#include <mach/imx25-regs.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx35-regs.h>
#include <io.h>
#define RCSR_NFC_FMS (1 << 8)
diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c
index 0489d09..58dbd70 100644
--- a/drivers/mtd/nand/nand_imx.c
+++ b/drivers/mtd/nand/nand_imx.c
@@ -26,7 +26,6 @@
#include <linux/mtd/nand.h>
#include <mach/generic.h>
#include <mach/imx-nand.h>
-#include <mach/imx-regs.h>
#include <io.h>
#include <errno.h>
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 3432d04..3b8b5f4 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -30,7 +30,6 @@
#include <asm/mmu.h>
#include <mach/generic.h>
-#include <mach/imx-regs.h>
#include <mach/clock.h>
#ifndef CONFIG_ARCH_MXS
# include <mach/iim.h>
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index e3fe6ad..694eac2 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -15,7 +15,6 @@
*/
#include <common.h>
-#include <mach/imx-regs.h>
#include <driver.h>
#include <init.h>
#include <malloc.h>
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 5b9d7d5..a29920d 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -20,7 +20,7 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/imx-regs.h>
+#include <mach/imx35-regs.h>
#include <fb.h>
#include <mach/imxfb.h>
#include <malloc.h>
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index ae4c671..39ecf6a 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -24,7 +24,6 @@
#include <init.h>
#include <linux/clk.h>
#include <linux/err.h>
-#include <mach/imx-regs.h>
#include <asm-generic/div64.h>
#define LCDC_SSA 0x00
--
1.7.10.4
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