* [PATCH 1/6] ArchosG9: changed serial port and env
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 0:22 ` [PATCH 2/6] ARM: add rename PSR bits to match linux names Vicente Bergas
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
arch/arm/boards/archosg9/env/config | 4 +++-
arch/arm/boards/archosg9/env/init/usbboot | 9 +++++----
arch/arm/configs/archosg9_defconfig | 2 +-
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boards/archosg9/env/config b/arch/arm/boards/archosg9/env/config
index 38fc51c..8f3edb0 100644
--- a/arch/arm/boards/archosg9/env/config
+++ b/arch/arm/boards/archosg9/env/config
@@ -1 +1,3 @@
-global.linux.bootargs.base="earlyprintk=serial console=ttyO1,1000000n8 keep_bootcon pm_disable initcall_debug ignore_loglevel no_console_suspend=1 root=/dev/ram0 init=/linuxrc"
+global.bootm.image="${TARGET_ROOT}/boot/zImage"
+global.bootm.initrd="${TARGET_ROOT}/boot/initrd"
+global.linux.bootargs.base="console=ttyO0,115200n8 root=/dev/ram0"
diff --git a/arch/arm/boards/archosg9/env/init/usbboot b/arch/arm/boards/archosg9/env/init/usbboot
index 25536e2..83dd19a 100644
--- a/arch/arm/boards/archosg9/env/init/usbboot
+++ b/arch/arm/boards/archosg9/env/init/usbboot
@@ -1,5 +1,6 @@
-mkdir /usb
-mount -t omap4_usbbootfs omap4_usbboot /usb
+TARGET_ROOT="/mnt/usb"
+mkdir ${TARGET_ROOT}
+mount -t omap4_usbbootfs omap4_usbboot ${TARGET_ROOT}
. /env/config
-. /usb/boot/config
-bootm -r /usb/boot/initrd /usb/boot/zImage
+. ${TARGET_ROOT}/boot/config
+bootm
diff --git a/arch/arm/configs/archosg9_defconfig b/arch/arm/configs/archosg9_defconfig
index e598258..2a20dd7 100644
--- a/arch/arm/configs/archosg9_defconfig
+++ b/arch/arm/configs/archosg9_defconfig
@@ -55,7 +55,7 @@ CONFIG_CMD_I2C=y
CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
-CONFIG_BAUDRATE=1000000
+CONFIG_BAUDRATE=115200
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_I2C_OMAP=y
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/6] ARM: add rename PSR bits to match linux names
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
2012-10-15 0:22 ` [PATCH 1/6] ArchosG9: changed serial port and env Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 0:22 ` [PATCH 3/6] ARM: ensure irqs are disabled at barebox exit Vicente Bergas
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
arch/arm/cpu/exceptions.S | 1 -
arch/arm/cpu/interrupts.c | 6 ++---
arch/arm/include/asm/ptrace.h | 55 +++++++++++++++++++++++--------------------
3 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S
index fe63a37..115c4e5 100644
--- a/arch/arm/cpu/exceptions.S
+++ b/arch/arm/cpu/exceptions.S
@@ -35,7 +35,6 @@
#define S_R0 0
#define MODE_SVC 0x13
-#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c
index 4ed562f..6e60adc 100644
--- a/arch/arm/cpu/interrupts.c
+++ b/arch/arm/cpu/interrupts.c
@@ -57,9 +57,9 @@ void show_regs (struct pt_regs *regs)
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
printf ("Flags: %c%c%c%c",
- flags & CC_N_BIT ? 'N' : 'n',
- flags & CC_Z_BIT ? 'Z' : 'z',
- flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ flags & PSR_N_BIT ? 'N' : 'n',
+ flags & PSR_Z_BIT ? 'Z' : 'z',
+ flags & PSR_C_BIT ? 'C' : 'c', flags & PSR_V_BIT ? 'V' : 'v');
printf (" IRQs %s FIQs %s Mode %s%s\n",
interrupts_enabled (regs) ? "on" : "off",
fast_interrupts_enabled (regs) ? "on" : "off",
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index b384369..e0695bb 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -23,25 +23,30 @@
/*
* PSR bits
*/
-#define USR26_MODE 0x00
-#define FIQ26_MODE 0x01
-#define IRQ26_MODE 0x02
-#define SVC26_MODE 0x03
-#define USR_MODE 0x10
-#define FIQ_MODE 0x11
-#define IRQ_MODE 0x12
-#define SVC_MODE 0x13
-#define ABT_MODE 0x17
-#define UND_MODE 0x1b
-#define SYSTEM_MODE 0x1f
-#define MODE_MASK 0x1f
-#define T_BIT 0x20
-#define F_BIT 0x40
-#define I_BIT 0x80
-#define CC_V_BIT (1 << 28)
-#define CC_C_BIT (1 << 29)
-#define CC_Z_BIT (1 << 30)
-#define CC_N_BIT (1 << 31)
+#define USR26_MODE 0x00000000
+#define FIQ26_MODE 0x00000001
+#define IRQ26_MODE 0x00000002
+#define SVC26_MODE 0x00000003
+#define USR_MODE 0x00000010
+#define FIQ_MODE 0x00000011
+#define IRQ_MODE 0x00000012
+#define SVC_MODE 0x00000013
+#define ABT_MODE 0x00000017
+#define UND_MODE 0x0000001b
+#define SYSTEM_MODE 0x0000001f
+#define MODE32_BIT 0x00000010
+#define MODE_MASK 0x0000001f
+#define PSR_T_BIT 0x00000020
+#define PSR_F_BIT 0x00000040
+#define PSR_I_BIT 0x00000080
+#define PSR_A_BIT 0x00000100
+#define PSR_E_BIT 0x00000200
+#define PSR_J_BIT 0x01000000
+#define PSR_Q_BIT 0x08000000
+#define PSR_V_BIT 0x10000000
+#define PSR_C_BIT 0x20000000
+#define PSR_Z_BIT 0x40000000
+#define PSR_N_BIT 0x80000000
#define PCMASK 0
#ifndef __ASSEMBLY__
@@ -79,7 +84,7 @@ struct pt_regs {
#ifdef CONFIG_ARM_THUMB
#define thumb_mode(regs) \
- (((regs)->ARM_cpsr & T_BIT))
+ (((regs)->ARM_cpsr & PSR_T_BIT))
#else
#define thumb_mode(regs) (0)
#endif
@@ -88,13 +93,13 @@ struct pt_regs {
((regs)->ARM_cpsr & MODE_MASK)
#define interrupts_enabled(regs) \
- (!((regs)->ARM_cpsr & I_BIT))
+ (!((regs)->ARM_cpsr & PSR_I_BIT))
#define fast_interrupts_enabled(regs) \
- (!((regs)->ARM_cpsr & F_BIT))
+ (!((regs)->ARM_cpsr & PSR_F_BIT))
#define condition_codes(regs) \
- ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+ ((regs)->ARM_cpsr & (PSR_V_BIT | PSR_C_BIT | PSR_Z_BIT | PSR_N_BIT))
/* Are the current registers suitable for user mode?
* (used to maintain security in signal handlers)
@@ -102,13 +107,14 @@ struct pt_regs {
static inline int valid_user_regs(struct pt_regs *regs)
{
if ((regs->ARM_cpsr & 0xf) == 0 &&
- (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+ (regs->ARM_cpsr & (PSR_F_BIT | PSR_I_BIT)) == 0)
return 1;
/*
* Force CPSR to something logical...
*/
- regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+ regs->ARM_cpsr &= (PSR_V_BIT | PSR_C_BIT | PSR_Z_BIT | PSR_N_BIT |
+ 0x10);
return 0;
}
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/6] ARM: ensure irqs are disabled at barebox exit
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
2012-10-15 0:22 ` [PATCH 1/6] ArchosG9: changed serial port and env Vicente Bergas
2012-10-15 0:22 ` [PATCH 2/6] ARM: add rename PSR bits to match linux names Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 0:22 ` [PATCH 4/6] UIMAGE: improve transfer speed Vicente Bergas
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
arch/arm/cpu/cpu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 51da3b5..4cf4efa 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -31,6 +31,7 @@
#include <asm/system_info.h>
#include <asm/cputype.h>
#include <asm/cache.h>
+#include <asm/ptrace.h>
/**
* Enable processor's instruction cache
@@ -74,10 +75,20 @@ int icache_status(void)
*/
void arch_shutdown(void)
{
+ uint32_t r;
+
#ifdef CONFIG_MMU
mmu_disable();
#endif
flush_icache();
+ /*
+ * barebox normally does not use interrupts, but some functionalities
+ * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
+ * disabled before exiting.
+ */
+ __asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
+ r |= PSR_I_BIT;
+ __asm__ __volatile__("msr cpsr, %0" : : "r"(r));
}
#ifdef CONFIG_THUMB2_BAREBOX
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/6] UIMAGE: improve transfer speed
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
` (2 preceding siblings ...)
2012-10-15 0:22 ` [PATCH 3/6] ARM: ensure irqs are disabled at barebox exit Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 0:22 ` [PATCH 5/6] ARM: use arm setup stack function on archosg9 Vicente Bergas
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
common/uimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/uimage.c b/common/uimage.c
index c72db41..b58dff1 100644
--- a/common/uimage.c
+++ b/common/uimage.c
@@ -373,7 +373,7 @@ static int uimage_sdram_flush(void *buf, unsigned int len)
return len;
}
-#define BUFSIZ (PAGE_SIZE * 2)
+#define BUFSIZ (PAGE_SIZE * 32)
struct resource *file_to_sdram(const char *filename, unsigned long adr)
{
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/6] ARM: use arm setup stack function on archosg9
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
` (3 preceding siblings ...)
2012-10-15 0:22 ` [PATCH 4/6] UIMAGE: improve transfer speed Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 0:22 ` [PATCH 6/6] OMAP4: clean voltage switch Vicente Bergas
2012-10-15 7:27 ` [PATCH 0/6] archosg9: improve support for tablet Sascha Hauer
6 siblings, 0 replies; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
arch/arm/boards/archosg9/lowlevel.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index fa5be1d..d0506bb 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -68,12 +68,9 @@ static noinline void archosg9_init_lowlevel(void)
void __naked __bare_init reset(void)
{
- u32 r;
-
common_reset();
- r = 0x4030D000;
- __asm__ __volatile__("mov sp, %0" : : "r"(r));
+ arm_setup_stack(0x4030d000);
archosg9_init_lowlevel();
}
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/6] OMAP4: clean voltage switch
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
` (4 preceding siblings ...)
2012-10-15 0:22 ` [PATCH 5/6] ARM: use arm setup stack function on archosg9 Vicente Bergas
@ 2012-10-15 0:22 ` Vicente Bergas
2012-10-15 7:17 ` Sascha Hauer
2012-10-15 7:27 ` [PATCH 0/6] archosg9: improve support for tablet Sascha Hauer
6 siblings, 1 reply; 10+ messages in thread
From: Vicente Bergas @ 2012-10-15 0:22 UTC (permalink / raw)
To: barebox; +Cc: Vicente Bergas
Modified voltage setting to do a clean switch.
See: http://lists.denx.de/pipermail/u-boot/2012-March/119149.html
Also changed vdd_mpu and VCORE2 to 1.2 volt as in u-boot.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
arch/arm/boards/archosg9/mux.c | 9 +----
arch/arm/mach-omap/include/mach/omap4-clock.h | 2 +-
arch/arm/mach-omap/include/mach/omap4-silicon.h | 2 +-
arch/arm/mach-omap/omap4_clock.c | 37 +++++++++++++++++-
arch/arm/mach-omap/omap4_generic.c | 52 ++++---------------------
5 files changed, 46 insertions(+), 56 deletions(-)
diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c
index 7ca5057..c8695c0 100644
--- a/arch/arm/boards/archosg9/mux.c
+++ b/arch/arm/boards/archosg9/mux.c
@@ -441,7 +441,7 @@ static const struct pad_conf_entry wkup_padconf_array[] = {
/* gpio_wk30 */
{ FREF_CLK3_REQ , M3 },
/* gpio_wk7 */ /* tps62361_vsel0 */
- { FREF_CLK4_REQ , IEN | PTU | M3 },
+ { FREF_CLK4_REQ , M3 },
};
void set_muxconf_regs(void){
@@ -449,11 +449,4 @@ void set_muxconf_regs(void){
core_padconf_array, ARRAY_SIZE(core_padconf_array));
omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP,
wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array));
-
- /* gpio_wk7 is used for controlling TPS on 4460 */
- if (omap4_revision() >= OMAP4460_ES1_0) {
- writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ);
- /* Enable GPIO-1 clocks before TPS initialization */
- omap4_enable_gpio1_wup_clocks();
- }
}
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index e5302d6..8cbc061 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -335,5 +335,5 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
void omap4_enable_gpio1_wup_clocks(void);
void omap4_enable_gpio_clocks(void);
void omap4_enable_all_clocks(void);
-void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
+void omap4_do_scale_tps62361(int vsel0_pin, u32 reg, u32 volt_mv);
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 71ffe39..137cc88 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -196,6 +196,6 @@ struct dpll_param;
void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
void omap4_power_i2c_send(u32);
unsigned int omap4_revision(void);
-noinline int omap4_scale_vcores(unsigned vsel0_pin);
+noinline int omap4_scale_vcores(int vsel0_pin);
#endif
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 1481f16..f7927d2 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -394,9 +394,38 @@ void omap4_enable_all_clocks(void)
sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
}
-void omap4_do_scale_tps62361(u32 reg, u32 volt_mv)
+#define GPIO_MASK 0x1f
+#define GPIO_OE 0x34
+#define GPIO_CLEARDATAOUT 0x90
+#define GPIO_SETDATAOUT 0x94
+
+static void __iomem *omap4_get_gpio_base(unsigned gpio)
+{
+ void __iomem *base;
+
+ if (gpio < 32)
+ base = (void *)0x4a310100;
+ else
+ base = (void *)(0x48053100 + ((gpio & ~GPIO_MASK) << 8));
+
+ return base;
+}
+
+void omap4_do_scale_tps62361(int vsel0_pin, u32 reg, u32 volt_mv)
{
u32 temp, step;
+ void __iomem *base;
+ u32 val;
+
+ /* Pull the GPIO low to select SET0 register, while we program SET1 */
+ if (vsel0_pin >= 0) {
+ base = omap4_get_gpio_base(vsel0_pin);
+ val = 1 << (vsel0_pin & GPIO_MASK);
+ writel(val, base + GPIO_CLEARDATAOUT);
+ val = readl(base + GPIO_OE);
+ val &= (1 << (vsel0_pin & GPIO_MASK));
+ writel(val, base + GPIO_OE);
+ }
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
@@ -411,4 +440,10 @@ void omap4_do_scale_tps62361(u32 reg, u32 volt_mv)
if (!wait_on_value(OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT, 0,
OMAP44XX_PRM_VC_VAL_BYPASS, LDELAY))
puts("Scaling voltage failed for vdd_mpu from TPS\n");
+
+ /* Pull the GPIO high to select SET1 register */
+ if (vsel0_pin >= 0) {
+ val = 1 << (vsel0_pin & GPIO_MASK);
+ writel(val, base + GPIO_SETDATAOUT);
+ }
}
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 765fcb5..8e692ba 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -495,27 +495,11 @@ enum omap_boot_src omap4_bootsrc(void)
return OMAP_BOOTSRC_UNKNOWN;
}
-#define GPIO_MASK 0x1f
-
-static void __iomem *omap4_get_gpio_base(unsigned gpio)
-{
- void __iomem *base;
-
- if (gpio < 32)
- base = (void *)0x4a310000;
- else
- base = (void *)(0x48053000 + ((gpio & ~GPIO_MASK) << 8));
-
- return base;
-}
-
#define I2C_SLAVE 0x12
-noinline int omap4_scale_vcores(unsigned vsel0_pin)
+noinline int omap4_scale_vcores(int vsel0_pin)
{
- void __iomem *base;
unsigned int rev = omap4_revision();
- u32 val = 0;
/* For VC bypass only VCOREx_CGF_FORCE is necessary and
* VCOREx_CFG_VOLTAGE changes can be discarded
@@ -523,33 +507,6 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
- /* TPS - supplies vdd_mpu on 4460 */
- if (rev >= OMAP4460_ES1_0) {
- /*
- * Setup SET1 and SET0 with right values so that kernel
- * can use either of them based on its needs.
- */
- omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
- omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
-
- /*
- * Select SET1 in TPS62361:
- * VSEL1 is grounded on board. So the following selects
- * VSEL1 = 0 and VSEL0 = 1
- */
- base = omap4_get_gpio_base(vsel0_pin);
-
- val = 1 << (vsel0_pin & GPIO_MASK);
- writel(val, base + 0x190);
-
- val = readl(base + 0x134);
- val &= (1 << (vsel0_pin & GPIO_MASK));
- writel(val, base + 0x134);
-
- val = 1 << (vsel0_pin & GPIO_MASK);
- writel(val, base + 0x194);
- }
-
/* set VCORE1 force VSEL */
/*
* 4430 : supplies vdd_mpu
@@ -568,8 +525,13 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
+ /* TPS - supplies vdd_mpu on 4460 */
+ if (rev >= OMAP4460_ES1_0)
+ omap4_do_scale_tps62361(vsel0_pin,
+ TPS62361_REG_ADDR_SET1, 1203);
+
/* FIXME: set VCORE2 force VSEL, Check the reset value */
- omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
+ omap4_power_i2c_send((0x285B << 8) | I2C_SLAVE);
/* set VCORE3 force VSEL */
switch (rev) {
--
1.7.12.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 6/6] OMAP4: clean voltage switch
2012-10-15 0:22 ` [PATCH 6/6] OMAP4: clean voltage switch Vicente Bergas
@ 2012-10-15 7:17 ` Sascha Hauer
0 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2012-10-15 7:17 UTC (permalink / raw)
To: Vicente Bergas; +Cc: barebox
On Mon, Oct 15, 2012 at 02:22:40AM +0200, Vicente Bergas wrote:
> Modified voltage setting to do a clean switch.
> See: http://lists.denx.de/pipermail/u-boot/2012-March/119149.html
Could you include the commit message from the original U-Boot commit?
Having a reference to the mailing list is fine, but we should also have
the reasoning behind this patch in the commit log.
Sascha
>
> Also changed vdd_mpu and VCORE2 to 1.2 volt as in u-boot.
>
> Signed-off-by: Vicente Bergas <vicencb@gmail.com>
> ---
> arch/arm/boards/archosg9/mux.c | 9 +----
> arch/arm/mach-omap/include/mach/omap4-clock.h | 2 +-
> arch/arm/mach-omap/include/mach/omap4-silicon.h | 2 +-
> arch/arm/mach-omap/omap4_clock.c | 37 +++++++++++++++++-
> arch/arm/mach-omap/omap4_generic.c | 52 ++++---------------------
> 5 files changed, 46 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c
> index 7ca5057..c8695c0 100644
> --- a/arch/arm/boards/archosg9/mux.c
> +++ b/arch/arm/boards/archosg9/mux.c
> @@ -441,7 +441,7 @@ static const struct pad_conf_entry wkup_padconf_array[] = {
> /* gpio_wk30 */
> { FREF_CLK3_REQ , M3 },
> /* gpio_wk7 */ /* tps62361_vsel0 */
> - { FREF_CLK4_REQ , IEN | PTU | M3 },
> + { FREF_CLK4_REQ , M3 },
> };
>
> void set_muxconf_regs(void){
> @@ -449,11 +449,4 @@ void set_muxconf_regs(void){
> core_padconf_array, ARRAY_SIZE(core_padconf_array));
> omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP,
> wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array));
> -
> - /* gpio_wk7 is used for controlling TPS on 4460 */
> - if (omap4_revision() >= OMAP4460_ES1_0) {
> - writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ);
> - /* Enable GPIO-1 clocks before TPS initialization */
> - omap4_enable_gpio1_wup_clocks();
> - }
> }
> diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
> index e5302d6..8cbc061 100644
> --- a/arch/arm/mach-omap/include/mach/omap4-clock.h
> +++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
> @@ -335,5 +335,5 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
> void omap4_enable_gpio1_wup_clocks(void);
> void omap4_enable_gpio_clocks(void);
> void omap4_enable_all_clocks(void);
> -void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
> +void omap4_do_scale_tps62361(int vsel0_pin, u32 reg, u32 volt_mv);
>
> diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> index 71ffe39..137cc88 100644
> --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
> +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> @@ -196,6 +196,6 @@ struct dpll_param;
> void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
> void omap4_power_i2c_send(u32);
> unsigned int omap4_revision(void);
> -noinline int omap4_scale_vcores(unsigned vsel0_pin);
> +noinline int omap4_scale_vcores(int vsel0_pin);
>
> #endif
> diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
> index 1481f16..f7927d2 100644
> --- a/arch/arm/mach-omap/omap4_clock.c
> +++ b/arch/arm/mach-omap/omap4_clock.c
> @@ -394,9 +394,38 @@ void omap4_enable_all_clocks(void)
> sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
> }
>
> -void omap4_do_scale_tps62361(u32 reg, u32 volt_mv)
> +#define GPIO_MASK 0x1f
> +#define GPIO_OE 0x34
> +#define GPIO_CLEARDATAOUT 0x90
> +#define GPIO_SETDATAOUT 0x94
> +
> +static void __iomem *omap4_get_gpio_base(unsigned gpio)
> +{
> + void __iomem *base;
> +
> + if (gpio < 32)
> + base = (void *)0x4a310100;
> + else
> + base = (void *)(0x48053100 + ((gpio & ~GPIO_MASK) << 8));
> +
> + return base;
> +}
> +
> +void omap4_do_scale_tps62361(int vsel0_pin, u32 reg, u32 volt_mv)
> {
> u32 temp, step;
> + void __iomem *base;
> + u32 val;
> +
> + /* Pull the GPIO low to select SET0 register, while we program SET1 */
> + if (vsel0_pin >= 0) {
> + base = omap4_get_gpio_base(vsel0_pin);
> + val = 1 << (vsel0_pin & GPIO_MASK);
> + writel(val, base + GPIO_CLEARDATAOUT);
> + val = readl(base + GPIO_OE);
> + val &= (1 << (vsel0_pin & GPIO_MASK));
> + writel(val, base + GPIO_OE);
> + }
>
> step = volt_mv - TPS62361_BASE_VOLT_MV;
> step /= 10;
> @@ -411,4 +440,10 @@ void omap4_do_scale_tps62361(u32 reg, u32 volt_mv)
> if (!wait_on_value(OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT, 0,
> OMAP44XX_PRM_VC_VAL_BYPASS, LDELAY))
> puts("Scaling voltage failed for vdd_mpu from TPS\n");
> +
> + /* Pull the GPIO high to select SET1 register */
> + if (vsel0_pin >= 0) {
> + val = 1 << (vsel0_pin & GPIO_MASK);
> + writel(val, base + GPIO_SETDATAOUT);
> + }
> }
> diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> index 765fcb5..8e692ba 100644
> --- a/arch/arm/mach-omap/omap4_generic.c
> +++ b/arch/arm/mach-omap/omap4_generic.c
> @@ -495,27 +495,11 @@ enum omap_boot_src omap4_bootsrc(void)
> return OMAP_BOOTSRC_UNKNOWN;
> }
>
> -#define GPIO_MASK 0x1f
> -
> -static void __iomem *omap4_get_gpio_base(unsigned gpio)
> -{
> - void __iomem *base;
> -
> - if (gpio < 32)
> - base = (void *)0x4a310000;
> - else
> - base = (void *)(0x48053000 + ((gpio & ~GPIO_MASK) << 8));
> -
> - return base;
> -}
> -
> #define I2C_SLAVE 0x12
>
> -noinline int omap4_scale_vcores(unsigned vsel0_pin)
> +noinline int omap4_scale_vcores(int vsel0_pin)
> {
> - void __iomem *base;
> unsigned int rev = omap4_revision();
> - u32 val = 0;
>
> /* For VC bypass only VCOREx_CGF_FORCE is necessary and
> * VCOREx_CFG_VOLTAGE changes can be discarded
> @@ -523,33 +507,6 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
> writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
> writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
>
> - /* TPS - supplies vdd_mpu on 4460 */
> - if (rev >= OMAP4460_ES1_0) {
> - /*
> - * Setup SET1 and SET0 with right values so that kernel
> - * can use either of them based on its needs.
> - */
> - omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
> - omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
> -
> - /*
> - * Select SET1 in TPS62361:
> - * VSEL1 is grounded on board. So the following selects
> - * VSEL1 = 0 and VSEL0 = 1
> - */
> - base = omap4_get_gpio_base(vsel0_pin);
> -
> - val = 1 << (vsel0_pin & GPIO_MASK);
> - writel(val, base + 0x190);
> -
> - val = readl(base + 0x134);
> - val &= (1 << (vsel0_pin & GPIO_MASK));
> - writel(val, base + 0x134);
> -
> - val = 1 << (vsel0_pin & GPIO_MASK);
> - writel(val, base + 0x194);
> - }
> -
> /* set VCORE1 force VSEL */
> /*
> * 4430 : supplies vdd_mpu
> @@ -568,8 +525,13 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
> /* 0x55: i2c addr, 28: ~ 1200 mvolts*/
> omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
>
> + /* TPS - supplies vdd_mpu on 4460 */
> + if (rev >= OMAP4460_ES1_0)
> + omap4_do_scale_tps62361(vsel0_pin,
> + TPS62361_REG_ADDR_SET1, 1203);
> +
> /* FIXME: set VCORE2 force VSEL, Check the reset value */
> - omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
> + omap4_power_i2c_send((0x285B << 8) | I2C_SLAVE);
>
> /* set VCORE3 force VSEL */
> switch (rev) {
> --
> 1.7.12.3
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/6] archosg9: improve support for tablet
2012-10-15 0:22 [PATCH 0/6] archosg9: improve support for tablet Vicente Bergas
` (5 preceding siblings ...)
2012-10-15 0:22 ` [PATCH 6/6] OMAP4: clean voltage switch Vicente Bergas
@ 2012-10-15 7:27 ` Sascha Hauer
2012-10-18 22:22 ` vj
6 siblings, 1 reply; 10+ messages in thread
From: Sascha Hauer @ 2012-10-15 7:27 UTC (permalink / raw)
To: Vicente Bergas; +Cc: barebox
Hi vj,
On Mon, Oct 15, 2012 at 02:22:34AM +0200, Vicente Bergas wrote:
> This patch series solves/improves/implements:
> ttyOxxx are 0 based, so change ttyO1 to ttyO0
> change speed to 115200, there are some issues at Mbaud speed in linux
> make the archos environment more flexible: initrd and zImage names are overwritable
> added definition of PSR_I_BIT and some others, remaining PSR bits renamed to match the linux ones
> disable interrupts at barebox exit
> speed up initrd transfer
> cleaner voltage switching
I applied up to 4/6.
>
> For the "OMAP4: clean voltage switch" patch I'm not sure if the changes are compatible with other boards.
>
> Vicente Bergas (6):
> ArchosG9: changed serial port and env
> ARM: add rename PSR bits to match linux names
> ARM: ensure irqs are disabled at barebox exit
> UIMAGE: improve transfer speed
> ARM: use arm setup stack function on archosg9
This one has to wait for some time. Currently the branch containing the
Archos patches does not have this function. I try to remember that I
still have to apply it.
> OMAP4: clean voltage switch
I responded to that separately.
BTW please try to add a bit more verbose commit messages next time. For
example for the uImage patch it would have been interesting to know
which workload is affected. Things like this will help us later when
we wish to change the lines along the commit and we wish to know why
they are there anyway.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/6] archosg9: improve support for tablet
2012-10-15 7:27 ` [PATCH 0/6] archosg9: improve support for tablet Sascha Hauer
@ 2012-10-18 22:22 ` vj
0 siblings, 0 replies; 10+ messages in thread
From: vj @ 2012-10-18 22:22 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On Mon, Oct 15, 2012 at 9:27 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi vj,
>
> On Mon, Oct 15, 2012 at 02:22:34AM +0200, Vicente Bergas wrote:
>> This patch series solves/improves/implements:
>> ttyOxxx are 0 based, so change ttyO1 to ttyO0
>> change speed to 115200, there are some issues at Mbaud speed in linux
>> make the archos environment more flexible: initrd and zImage names are overwritable
>> added definition of PSR_I_BIT and some others, remaining PSR bits renamed to match the linux ones
>> disable interrupts at barebox exit
>> speed up initrd transfer
>> cleaner voltage switching
>
> I applied up to 4/6.
>
>>
>> For the "OMAP4: clean voltage switch" patch I'm not sure if the changes are compatible with other boards.
>>
>> Vicente Bergas (6):
>> ArchosG9: changed serial port and env
>> ARM: add rename PSR bits to match linux names
>> ARM: ensure irqs are disabled at barebox exit
>> UIMAGE: improve transfer speed
>> ARM: use arm setup stack function on archosg9
>
> This one has to wait for some time. Currently the branch containing the
> Archos patches does not have this function. I try to remember that I
> still have to apply it.
I think now it's merged into 'next' as per commit
df67c63ad2fced2d1cc57735470cec543590665c.
>
>> OMAP4: clean voltage switch
>
> I responded to that separately.
>
> BTW please try to add a bit more verbose commit messages next time. For
> example for the uImage patch it would have been interesting to know
> which workload is affected. Things like this will help us later when
> we wish to change the lines along the commit and we wish to know why
> they are there anyway.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 10+ messages in thread