* [PATCH 01/10] ARM i.MX31: Fix gpio device names
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 02/10] ARM i.MX31 pcm037: Force internal phy Sascha Hauer
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Has to be imx31-gpio, not imx-gpio.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx31.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index 52be541..2882675 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -34,9 +34,9 @@ static int imx31_init(void)
add_generic_device("imx31-iomux", 0, NULL, MX31_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
- add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
- add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
+ add_generic_device("imx31-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx21-wdt", 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-esdctl", 0, NULL, MX31_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 02/10] ARM i.MX31 pcm037: Force internal phy
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
2012-12-12 20:09 ` [PATCH 01/10] ARM i.MX31: Fix gpio device names Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 03/10] ARM i.MX31 pcm037: make board bootable again Sascha Hauer
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
The smsc911x has a bootstrap pin for detecting an external phy.
Unfortunately this is pulled into the wrong direction on the pcm037
board, so force internal phy with platform data.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/pcm037.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index ff32e35..b8e55a0 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -31,6 +31,7 @@
#include <mach/gpio.h>
#include <mach/weim.h>
#include <io.h>
+#include <smc911x.h>
#include <asm/mmu.h>
#include <partition.h>
#include <generated/mach-types.h>
@@ -153,6 +154,10 @@ static int pcm037_mmu_init(void)
}
postmmu_initcall(pcm037_mmu_init);
+static struct smc911x_plat smsc9217_pdata = {
+ .flags = SMC911X_FORCE_INTERNAL_PHY,
+};
+
static int imx31_devices_init(void)
{
/* CS0: Nor Flash */
@@ -193,7 +198,7 @@ static int imx31_devices_init(void)
* GPIO3, data width is 16 bit
*/
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR,
- MX31_CS1_SIZE, IORESOURCE_MEM, NULL);
+ MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata);
#ifdef CONFIG_USB
pcm037_usb_init();
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 03/10] ARM i.MX31 pcm037: make board bootable again
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
2012-12-12 20:09 ` [PATCH 01/10] ARM i.MX31: Fix gpio device names Sascha Hauer
2012-12-12 20:09 ` [PATCH 02/10] ARM i.MX31 pcm037: Force internal phy Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 04/10] ARM i.MX31 pcm037: remove unused defines Sascha Hauer
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
This enables the di in the IPU_CONF register. Otherwise the board
refuses to start.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/lowlevel_init.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index f9ecce1..9560841 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -47,6 +47,8 @@ reset:
common_reset r0
+ writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR)
+
writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
DELAY 0x40000
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 04/10] ARM i.MX31 pcm037: remove unused defines
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (2 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 03/10] ARM i.MX31 pcm037: make board bootable again Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 05/10] ARM i.MX31 pcm037: rewrite lowlevel init code in C Sascha Hauer
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/pcm037.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index b8e55a0..68a6c8d 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -39,18 +39,6 @@
#include <mach/imx-nand.h>
#include <mach/devices-imx31.h>
-#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
-#define SDRAM0 128
-#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
-#define SDRAM0 256
-#endif
-
-#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
-#define SDRAM1 128
-#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
-#define SDRAM1 256
-#endif
-
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 05/10] ARM i.MX31 pcm037: rewrite lowlevel init code in C
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (3 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 04/10] ARM i.MX31 pcm037: remove unused defines Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 06/10] ARM i.MX31 pcm037: Switch to new environment Sascha Hauer
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Tested with NOR and NAND boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/Makefile | 4 +-
arch/arm/boards/pcm037/lowlevel.c | 162 ++++++++++++++++++++++++++++++
arch/arm/boards/pcm037/lowlevel_init.S | 170 --------------------------------
3 files changed, 164 insertions(+), 172 deletions(-)
create mode 100644 arch/arm/boards/pcm037/lowlevel.c
delete mode 100644 arch/arm/boards/pcm037/lowlevel_init.S
diff --git a/arch/arm/boards/pcm037/Makefile b/arch/arm/boards/pcm037/Makefile
index fcfa40d..859501c 100644
--- a/arch/arm/boards/pcm037/Makefile
+++ b/arch/arm/boards/pcm037/Makefile
@@ -16,6 +16,6 @@
#
#
-obj-y += lowlevel_init.o
-pbl-y += lowlevel_init.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
obj-y += pcm037.o
diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c
new file mode 100644
index 0000000..fda3106
--- /dev/null
+++ b/arch/arm/boards/pcm037/lowlevel.c
@@ -0,0 +1,162 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <mach/imx-nand.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm-generic/memory_layout.h>
+#include <asm-generic/sections.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/imx31-regs.h>
+#include <mach/imx-pll.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/esdctl.h>
+
+#ifdef CONFIG_NAND_IMX_BOOT
+static void __bare_init __naked insdram(void)
+{
+ /* setup a stack to be able to call imx_nand_load_image() */
+ arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
+
+ imx_nand_load_image(_text, barebox_image_size);
+
+ board_init_lowlevel_return();
+}
+#endif
+
+#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+
+void __bare_init __naked reset(void)
+{
+ uint32_t r;
+ int i;
+ volatile int v;
+#ifdef CONFIG_NAND_IMX_BOOT
+ unsigned int *trg, *src;
+#endif
+ common_reset();
+
+ writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
+
+ writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
+
+ for (v = 0; v < 0x4000; v++);
+
+ writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
+ MX31_CCM_CCMR);
+ writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
+ MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
+
+ writel(MX31_PDR0_CSI_PODF(0xff1) | \
+ MX31_PDR0_PER_PODF(7) | \
+ MX31_PDR0_HSP_PODF(3) | \
+ MX31_PDR0_NFC_PODF(5) | \
+ MX31_PDR0_IPG_PODF(1) | \
+ MX31_PDR0_MAX_PODF(3) | \
+ MX31_PDR0_MCU_PODF(0), \
+ MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
+
+ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
+ IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
+ MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
+ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
+ IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
+ MX31_CCM_SPCTL);
+
+ /*
+ * Configure IOMUXC
+ * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched),
+ * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
+ * (behaviour copied by sha, source unknown)
+ */
+ writel(0, 0x43fac26c);
+ writel(0, 0x43fac270);
+ writel(0, 0x43fac274);
+
+ writel(0x1000, 0x43fac27c);
+
+ for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
+ writel(0, r);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0x80000000 && r < 0xa0000000)
+ board_init_lowlevel_return();
+
+#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
+#define ROWS0 ESDCTL0_ROW13
+#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
+#define ROWS0 ESDCTL0_ROW14
+#endif
+ writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+ writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
+ writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writel(0x12344321, MX31_CSD0_BASE_ADDR);
+ writel(0x12344321, MX31_CSD0_BASE_ADDR);
+ writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
+ writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
+ writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+
+#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
+#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
+#define ROWS1 ESDCTL0_ROW13
+#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
+#define ROWS1 ESDCTL0_ROW14
+#endif
+ writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1);
+ writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
+ writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00);
+ writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
+ writel(0x12344321, MX31_CSD1_BASE_ADDR);
+ writel(0x12344321, MX31_CSD1_BASE_ADDR);
+ writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
+ writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33);
+ writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000);
+ writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
+ writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR);
+ writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+#endif
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r = get_pc();
+ if (r < MX31_NFC_BASE_ADDR || r > MX31_NFC_BASE_ADDR + 0x800)
+ board_init_lowlevel_return();
+
+ src = (unsigned int *)MX31_NFC_BASE_ADDR;
+ trg = (unsigned int *)_text;
+
+ /* Move ourselves out of NFC SRAM */
+ for (i = 0; i < 0x800 / sizeof(int); i++)
+ *trg++ = *src++;
+
+ /* Jump to SDRAM */
+ r = (unsigned int)&insdram;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r));
+#else
+ board_init_lowlevel_return();
+#endif
+}
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
deleted file mode 100644
index 9560841..0000000
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/imx31-regs.h>
-#include <mach/imx-pll.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/esdctl.h>
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-#define writeb(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- strb r1, [r0];
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
- .section ".text_bare_init","ax"
-
-.globl reset
-reset:
-
- common_reset r0
-
- writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR)
-
- writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
-
- DELAY 0x40000
-
- writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
- MX31_CCM_CCMR)
- writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
- MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
-
- writel(MX31_PDR0_CSI_PODF(0xff1) | \
- MX31_PDR0_PER_PODF(7) | \
- MX31_PDR0_HSP_PODF(3) | \
- MX31_PDR0_NFC_PODF(5) | \
- MX31_PDR0_IPG_PODF(1) | \
- MX31_PDR0_MAX_PODF(3) | \
- MX31_PDR0_MCU_PODF(0), \
- MX31_CCM_BASE_ADDR + MX31_CCM_PDR0)
-
- writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
- IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
- MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL)
- writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
- IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
- MX31_CCM_SPCTL)
-
- /* Configure IOMUXC
- * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
- * (behaviour copied by sha, source unknown)
- */
- mov r1, #0;
- ldr r0, =0x43FAC26C
- str r1, [r0], #4
- str r1, [r0], #4
- str r1, [r0], #0x10
-
- ldr r2, =0x43FAC2DC
-clear_iomux:
- str r1, [r0], #4
- cmp r0, r2
- bls clear_iomux
- writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */
-
- /* Skip SDRAM initialization if we run from RAM */
- cmp pc, #0x80000000
- blo 1f
- cmp pc, #0x90000000
- bhs 1f
-
- b board_init_lowlevel_return
-1:
-
-#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
-#define ROWS0 ESDCTL0_ROW13
-#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
-#define ROWS0 ESDCTL0_ROW14
-#endif
- writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
- writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
- writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- writel(0x12344321, MX31_CSD0_BASE_ADDR)
- writel(0x12344321, MX31_CSD0_BASE_ADDR)
- writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
- writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
- writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
-
-#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
-#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
-#define ROWS1 ESDCTL0_ROW13
-#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
-#define ROWS1 ESDCTL0_ROW14
-#endif
- writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1)
- writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
- writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
- writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
- writel(0x12344321, MX31_CSD1_BASE_ADDR)
- writel(0x12344321, MX31_CSD1_BASE_ADDR)
- writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
- writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
- writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
- writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
- writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
- writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
-#endif
-
-#ifdef CONFIG_NAND_IMX_BOOT
- ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */
-
- ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */
- ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
-
- /* skip NAND boot if not running from NFC space */
- cmp pc, r0
- blo ret
- cmp pc, r2
- bhs ret
-
- /* Move ourselves out of NFC SRAM */
- ldr r1, =_text
-
-copy_loop:
- ldmia r0!, {r3-r9} /* copy from source address [r0] */
- stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- ble copy_loop
-
- ldr pc, =1f /* Jump to SDRAM */
-1:
- b nand_boot /* Load barebox from NAND Flash */
-ret:
-#endif /* CONFIG_NAND_IMX_BOOT */
-
- b board_init_lowlevel_return
-
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 06/10] ARM i.MX31 pcm037: Switch to new environment
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (4 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 05/10] ARM i.MX31 pcm037: rewrite lowlevel init code in C Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 07/10] ARM i.MX31: sync iomux with kernel Sascha Hauer
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/env/boot/nand-ubi | 10 +++++
arch/arm/boards/pcm037/env/config | 52 -------------------------
arch/arm/boards/pcm037/env/init/config-board | 7 ++++
arch/arm/boards/pcm037/env/init/mtdparts-nand | 11 ++++++
arch/arm/boards/pcm037/env/init/mtdparts-nor | 11 ++++++
arch/arm/configs/pcm037_defconfig | 32 +++++++++++----
arch/arm/mach-imx/Kconfig | 1 +
7 files changed, 65 insertions(+), 59 deletions(-)
create mode 100644 arch/arm/boards/pcm037/env/boot/nand-ubi
delete mode 100644 arch/arm/boards/pcm037/env/config
create mode 100644 arch/arm/boards/pcm037/env/init/config-board
create mode 100644 arch/arm/boards/pcm037/env/init/mtdparts-nand
create mode 100644 arch/arm/boards/pcm037/env/init/mtdparts-nor
diff --git a/arch/arm/boards/pcm037/env/boot/nand-ubi b/arch/arm/boards/pcm037/env/boot/nand-ubi
new file mode 100644
index 0000000..67b0cb4
--- /dev/null
+++ b/arch/arm/boards/pcm037/env/boot/nand-ubi
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "nand (UBI)"
+ exit
+fi
+
+global.bootm.image="/dev/nand0.kernel.bb"
+#global.bootm.oftree="/env/oftree"
+global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config
deleted file mode 100644
index 569bfe4..0000000
--- a/arch/arm/boards/pcm037/env/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-global.hostname=pcm037
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
- kernelimage="$user"-"$kernelimage"
- nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
- rootfsimage="$user"-"$rootfsimage"
-else
- nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nor=3
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nand=7
-nand_device="mxc_nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/pcm037/env/init/config-board b/arch/arm/boards/pcm037/env/init/config-board
new file mode 100644
index 0000000..03f9e97
--- /dev/null
+++ b/arch/arm/boards/pcm037/env/init/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=pcm037
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nand b/arch/arm/boards/pcm037/env/init/mtdparts-nand
new file mode 100644
index 0000000..84220b7
--- /dev/null
+++ b/arch/arm/boards/pcm037/env/init/mtdparts-nand
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "NAND partitions"
+ exit
+fi
+
+mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
+kernelname="mxc_nand"
+
+mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nor b/arch/arm/boards/pcm037/env/init/mtdparts-nor
new file mode 100644
index 0000000..2ef6ead
--- /dev/null
+++ b/arch/arm/boards/pcm037/env/init/mtdparts-nor
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "NOR partitions"
+ exit
+fi
+
+mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
+kernelname="physmap-flash.0"
+
+mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
index 5a527d5..7c630a5 100644
--- a/arch/arm/configs/pcm037_defconfig
+++ b/arch/arm/configs/pcm037_defconfig
@@ -11,25 +11,36 @@ CONFIG_MALLOC_SIZE=0x01000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
-CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
CONFIG_PARTITION=y
CONFIG_PARTITION_DISK=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env"
+CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
@@ -37,23 +48,24 @@ CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
-# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
+CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_CLK=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
-CONFIG_NET_NFS=y
CONFIG_NET_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_SMC911X=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
@@ -65,5 +77,11 @@ CONFIG_NAND_IMX=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ec4f864..33724e9 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -333,6 +333,7 @@ config MACH_PCM037
bool "phyCORE-i.MX31"
select MACH_HAS_LOWLEVEL_INIT
select USB_ULPI if USB
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_HAS_L2X0
help
Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 07/10] ARM i.MX31: sync iomux with kernel
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (5 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 06/10] ARM i.MX31 pcm037: Switch to new environment Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 08/10] ARM i.MX31 pcm037: add more iomux pins Sascha Hauer
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/include/mach/iomux-mx31.h | 253 +++++++++++++++++++++++----
arch/arm/mach-imx/iomux-v2.c | 12 +-
2 files changed, 227 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h
index afb6fba..258ccee 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx31.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h
@@ -12,12 +12,10 @@
* GNU General Public License for more details.
*
*/
-
-#ifndef __MACH_MX31_IOMUX_H__
-#define __MACH_MX31_IOMUX_H__
+#ifndef __MACH_IOMUX_MX3_H__
+#define __MACH_IOMUX_MX3_H__
#include <linux/types.h>
-
/*
* various IOMUX output functions
*/
@@ -30,7 +28,7 @@
#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
-#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
+#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
#define IOMUX_ICONFIG_FUNC 2 /* used as function */
#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
@@ -88,7 +86,7 @@ enum iomux_gp_func {
MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
MUX_TAMPER_DETECT_EN = 1 << 16,
MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGB_USB_COMMON = 1 << 18,
+ MUX_PGP_USB_COMMON = 1 << 18,
MUX_SDHC_MEMSTICK1 = 1 << 19,
MUX_SDHC_MEMSTICK2 = 1 << 20,
MUX_PGP_SPLL_BYP = 1 << 21,
@@ -105,21 +103,23 @@ enum iomux_gp_func {
};
/*
- * This function enables/disables the general purpose function for a particular
- * signal.
+ * setups mutliple pins
+ * convenient way to call the above function with tables
*/
-void iomux_config_gpr(enum iomux_gp_func , int);
+int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count);
/*
- * set the mode for a IOMUX pin.
+ * This function enables/disables the general purpose function for a particular
+ * signal.
*/
-int mxc_iomux_mode(unsigned int);
+void imx_iomux_set_gpr(enum iomux_gp_func, bool en);
/*
- * This function enables/disables the general purpose function for a particular
- * signal.
+ * This function only configures the iomux hardware.
+ * It is called by the setup functions and should not be called directly anymore.
+ * It is here visible for backward compatibility
*/
-void mxc_iomux_set_gpr(enum iomux_gp_func, int);
+int imx_iomux_mode(unsigned int pin_mode);
#define IOMUX_PADNUM_MASK 0x1ff
#define IOMUX_GPIONUM_SHIFT 9
@@ -135,9 +135,6 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, int);
#define IOMUX_TO_GPIO(iomux_pin) \
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-#define IOMUX_TO_IRQ(iomux_pin) \
- (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
- MXC_GPIO_INT_BASE)
/*
* This enumeration is constructed based on the Section
@@ -476,6 +473,9 @@ enum iomux_pins {
MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
};
+#define PIN_MAX 327
+#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
+
/*
* Convenience values for use with mxc_iomux_mode()
*
@@ -483,14 +483,28 @@ enum iomux_pins {
*/
#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
@@ -503,7 +517,9 @@ enum iomux_pins {
#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
@@ -521,29 +537,192 @@ enum iomux_pins {
#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
-/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
- * cspi1_ss1*/
/*
- * This function configures the pad value for a IOMUX pin.
+ * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
+ * cspi2_ss1, cspi1_ss0 cspi1_ss1
*/
-int imx_iomux_mode(unsigned int pin_mode);
-void imx_iomux_set_pad(enum iomux_pins pin, u32 config);
-void imx_iomux_set_gpr(enum iomux_gp_func gp, int en);
-
-#endif
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void imx_iomux_set_pad(enum iomux_pins, u32);
+#endif /* ifndef __MACH_IOMUX_MX3_H__ */
diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c
index dbbb8a2..cef0340 100644
--- a/arch/arm/mach-imx/iomux-v2.c
+++ b/arch/arm/mach-imx/iomux-v2.c
@@ -88,7 +88,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
* This function enables/disables the general purpose function for a particular
* signal.
*/
-void imx_iomux_set_gpr(enum iomux_gp_func gp, int en)
+void imx_iomux_set_gpr(enum iomux_gp_func gp, bool en)
{
u32 l;
@@ -105,6 +105,16 @@ void imx_iomux_set_gpr(enum iomux_gp_func gp, int en)
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
+int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ imx_iomux_mode(pin_list[i]);
+
+ return 0;
+}
+
static int imx_iomux_probe(struct device_d *dev)
{
base = dev_request_mem_region(dev, 0);
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 08/10] ARM i.MX31 pcm037: add more iomux pins
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (6 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 07/10] ARM i.MX31: sync iomux with kernel Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 09/10] ARM i.MX31: Add mmc register convenience functions Sascha Hauer
2012-12-12 20:09 ` [PATCH 10/10] ARM i.MX31 pcm037: add mmc support Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Use imx_iomux_setup_multiple_pins to setup the pinmux and add more
pins.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/pcm037.c | 46 ++++++++++++++++++++++++++++++++++-----
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 68a6c8d..cd911b7 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -202,13 +202,49 @@ static int imx31_devices_init(void)
device_initcall(imx31_devices_init);
+static unsigned int pcm037_iomux[] = {
+ /* UART1 */
+ MX31_PIN_RXD1__RXD1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ /* I2C */
+ MX31_PIN_CSPI2_MOSI__SCL,
+ MX31_PIN_CSPI2_MISO__SDA,
+ MX31_PIN_CSPI2_SS2__I2C3_SDA,
+ MX31_PIN_CSPI2_SCLK__I2C3_SCL,
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+ IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
+ IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
+ /* SPI1 */
+ MX31_PIN_CSPI1_MOSI__MOSI,
+ MX31_PIN_CSPI1_MISO__MISO,
+ MX31_PIN_CSPI1_SCLK__SCLK,
+ MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI1_SS0__SS0,
+ MX31_PIN_CSPI1_SS1__SS1,
+ MX31_PIN_CSPI1_SS2__SS2,
+ /* UART2 */
+ MX31_PIN_TXD2__TXD2,
+ MX31_PIN_RXD2__RXD2,
+ MX31_PIN_CTS2__CTS2,
+ MX31_PIN_RTS2__RTS2,
+ /* UART3 */
+ MX31_PIN_CSPI3_MOSI__RXD3,
+ MX31_PIN_CSPI3_MISO__TXD3,
+ MX31_PIN_CSPI3_SCLK__RTS3,
+ MX31_PIN_CSPI3_SPI_RDY__CTS3,
+};
+
static int imx31_console_init(void)
{
- /* init gpios for serial port */
- imx_iomux_mode(MX31_PIN_RXD1__RXD1);
- imx_iomux_mode(MX31_PIN_TXD1__TXD1);
- imx_iomux_mode(MX31_PIN_CTS1__CTS1);
- imx_iomux_mode(MX31_PIN_RTS1__RTS1);
+ imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux));
imx31_add_uart0();
return 0;
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 09/10] ARM i.MX31: Add mmc register convenience functions
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (7 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 08/10] ARM i.MX31 pcm037: add more iomux pins Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
2012-12-12 20:09 ` [PATCH 10/10] ARM i.MX31 pcm037: add mmc support Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/include/mach/devices-imx31.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h
index fe71930..5a24100 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx31.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx31.h
@@ -51,3 +51,13 @@ static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pda
{
return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata);
}
+
+static inline struct device_d *imx31_add_mmc0(void *pdata)
+{
+ return imx_add_mmc((void *)MX31_SDHC1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx31_add_mmc1(void *pdata)
+{
+ return imx_add_mmc((void *)MX31_SDHC2_BASE_ADDR, 1, pdata);
+}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 10/10] ARM i.MX31 pcm037: add mmc support
2012-12-12 20:09 [PATCH] i.MX31/pcm037 fixes and updates Sascha Hauer
` (8 preceding siblings ...)
2012-12-12 20:09 ` [PATCH 09/10] ARM i.MX31: Add mmc register convenience functions Sascha Hauer
@ 2012-12-12 20:09 ` Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2012-12-12 20:09 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pcm037/pcm037.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index cd911b7..7894ff3 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -163,6 +163,8 @@ static int imx31_devices_init(void)
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
+ imx31_add_mmc0(NULL);
+
/*
* Create partitions that should be
* not touched by any regular user
--
1.7.10.4
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^ permalink raw reply [flat|nested] 11+ messages in thread