[PATCH] ARM OMAP: move lowlevel board code to lowlevel.c

[PATCH] ARM OMAP: move lowlevel board code to lowlevel.c

[Sascha Hauer]

This moves the board specific lowlevel code to a separate file for
the omap (and am33xx) boards. This is just a preparation for the
barebox-arm-entry series which needs the SDRAM setup in lowlevel
code rather than initcalls.
No functional change in this series.

Sascha

----------------------------------------------------------------
Sascha Hauer (6):
      ARM omap3 beagle: move lowlevel code to lowlevel.c
      ARM omap3 phycard-a-l1: move lowlevel code to lowlevel.c
      ARM omap3 omap343xdsp: move lowlevel code to lowlevel.c
      ARM omap3 omap3evm: move lowlevel code to lowlevel.c
      ARM am33xx beaglebone: move lowlevel code to lowlevel.c
      ARM omap3 beagle: Compile xload defconfig in Thumb2 mode

 arch/arm/boards/beagle/Makefile                  |    2 +
 arch/arm/boards/beagle/board.c                   |  169 -------
 arch/arm/boards/beagle/lowlevel.c                |  167 +++++++
 arch/arm/boards/beaglebone/Makefile              |    2 +
 arch/arm/boards/beaglebone/board.c               |  240 ----------
 arch/arm/boards/beaglebone/lowlevel.c            |  248 ++++++++++
 arch/arm/boards/omap343xdsp/Makefile             |    2 +
 arch/arm/boards/omap343xdsp/board.c              |  547 ----------------------
 arch/arm/boards/omap343xdsp/lowlevel.c           |  546 +++++++++++++++++++++
 arch/arm/boards/omap3evm/Makefile                |    2 +
 arch/arm/boards/omap3evm/board.c                 |  158 -------
 arch/arm/boards/omap3evm/lowlevel.c              |  160 +++++++
 arch/arm/boards/phycard-a-l1/Makefile            |    2 +
 arch/arm/boards/phycard-a-l1/lowlevel.c          |  251 ++++++++++
 arch/arm/boards/phycard-a-l1/pca-a-l1.c          |  247 ----------
 arch/arm/configs/omap3530_beagle_xload_defconfig |    2 +-
 16 files changed, 1383 insertions(+), 1362 deletions(-)
 create mode 100644 arch/arm/boards/beagle/lowlevel.c
 create mode 100644 arch/arm/boards/beaglebone/lowlevel.c
 create mode 100644 arch/arm/boards/omap343xdsp/lowlevel.c
 create mode 100644 arch/arm/boards/omap3evm/lowlevel.c
 create mode 100644 arch/arm/boards/phycard-a-l1/lowlevel.c

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[PATCH 1/6] ARM omap3 beagle: move lowlevel code to lowlevel.c

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beagle/Makefile   |    2 +
 arch/arm/boards/beagle/board.c    |  169 -------------------------------------
 arch/arm/boards/beagle/lowlevel.c |  167 ++++++++++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+), 169 deletions(-)
 create mode 100644 arch/arm/boards/beagle/lowlevel.c

diff --git a/arch/arm/boards/beagle/Makefile b/arch/arm/boards/beagle/Makefile
index dcfc293..88c223a 100644
--- a/arch/arm/boards/beagle/Makefile
+++ b/arch/arm/boards/beagle/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index 88096bb..bed4651 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -55,12 +55,6 @@
 #include <ns16550.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
-#include <mach/omap3-silicon.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
-#include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <mach/gpmc_nand.h>
 #include <mach/ehci.h>
@@ -70,169 +64,6 @@
 #include <usb/ehci.h>
 #include <mach/xload.h>
 
-/******************** Board Boot Time *******************/
-
-/**
- * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* SDRAM software reset */
-	/* No idle ack and RESET enable */
-	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
-	sdelay(100);
-	/* No idle ack and RESET disable */
-	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC Registers Configuration --------- */
-	/* SDRC_MCFG0 register */
-	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_RFR_CTRL0 register */
-	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_ACTIM_CTRLA0 register */
-	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_ACTIM_CTRLB0 register */
-	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE due to 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_MANUAL command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register Burst length=4 */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
-
-	/* SDRC DLLA control register */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-	return;
-}
-
-/**
- * @brief Do the pin muxing required for Board operation.
- * We enable ONLY the pins we require to set. OMAP provides pins which do not
- * have alternate modes. Such pins done need to be set.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
-
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
-
-	/* D0-D7 default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
-	/* GPMC_NADV_ALE default mux mode is mode0 */
-	/* GPMC_NOE default mux mode is mode0 */
-	/* GPMC_NWE default mux mode is mode0 */
-	/* GPMC_NBE0_CLE default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
-	/* GPMC_WAIT0 default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
-
-	/* SERIAL INTERFACE */
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
-	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
-	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
-	/* I2C1_SCL default mux mode is mode0 */
-	/* I2C1_SDA default mux mode is mode0 */
-	/* USB EHCI (port 2) */
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/;
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int beagle_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	mux_config();
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(beagle_board_init);
-
-/******************** Board Run Time *******************/
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
new file mode 100644
index 0000000..677f055
--- /dev/null
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -0,0 +1,167 @@
+#include <io.h>
+#include <init.h>
+#include <mach/control.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/syslib.h>
+#include <mach/sys_info.h>
+
+/**
+ * @brief Do the pin muxing required for Board operation.
+ * We enable ONLY the pins we require to set. OMAP provides pins which do not
+ * have alternate modes. Such pins done need to be set.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
+
+	/* D0-D7 default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
+	/* GPMC_NADV_ALE default mux mode is mode0 */
+	/* GPMC_NOE default mux mode is mode0 */
+	/* GPMC_NWE default mux mode is mode0 */
+	/* GPMC_NBE0_CLE default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+	/* GPMC_WAIT0 default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+
+	/* SERIAL INTERFACE */
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
+	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
+	/* I2C1_SCL default mux mode is mode0 */
+	/* I2C1_SDA default mux mode is mode0 */
+	/* USB EHCI (port 2) */
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/;
+}
+
+/**
+ * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* SDRAM software reset */
+	/* No idle ack and RESET enable */
+	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
+	sdelay(100);
+	/* No idle ack and RESET disable */
+	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC Registers Configuration --------- */
+	/* SDRC_MCFG0 register */
+	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_RFR_CTRL0 register */
+	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_ACTIM_CTRLA0 register */
+	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_ACTIM_CTRLB0 register */
+	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE due to 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_MANUAL command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register Burst length=4 */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
+
+	/* SDRC DLLA control register */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	return;
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int beagle_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	mux_config();
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(beagle_board_init);
-- 
1.7.10.4


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[PATCH 2/6] ARM omap3 phycard-a-l1: move lowlevel code to lowlevel.c

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/phycard-a-l1/Makefile   |    2 +
 arch/arm/boards/phycard-a-l1/lowlevel.c |  251 +++++++++++++++++++++++++++++++
 arch/arm/boards/phycard-a-l1/pca-a-l1.c |  247 ------------------------------
 3 files changed, 253 insertions(+), 247 deletions(-)
 create mode 100644 arch/arm/boards/phycard-a-l1/lowlevel.c

diff --git a/arch/arm/boards/phycard-a-l1/Makefile b/arch/arm/boards/phycard-a-l1/Makefile
index 7041e11..5565c3d 100644
--- a/arch/arm/boards/phycard-a-l1/Makefile
+++ b/arch/arm/boards/phycard-a-l1/Makefile
@@ -15,3 +15,5 @@
 #
 
 obj-y += pca-a-l1.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
new file mode 100644
index 0000000..d82c43d
--- /dev/null
+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c
@@ -0,0 +1,251 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+/* Slower full frequency range default timings for x32 operation */
+#define SDP_SDRC_SHARING	0x00000100
+/* Diabling power down mode using CKE pin */
+#define SDP_SDRC_POWER_POP	0x00000081
+/* rkw - need to find of 90/72 degree recommendation for speed like before. */
+#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
+	(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* used to create an array of memory configuartions. */
+struct sdrc_config {
+	u32	cs_cfg;
+	u32	mcfg;
+	u32	mr;
+	u32	actim_ctrla;
+	u32	actim_ctrlb;
+	u32	rfr_ctrl;
+} const sdrc_config[] = {
+/* max cs_size for autodetection, common timing */
+/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
+{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
+/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
+{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
+/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
+{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
+/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
+{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
+};
+
+/*
+ * Boot-time initialization(s)
+ */
+
+/*********************************************************************
+ * init_sdram_ddr() - Init DDR controller.
+ *********************************************************************/
+void init_sdram_ddr(void)
+{
+	/* reset sdrc controller */
+	writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
+	wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
+	writel(0, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* setup sdrc to ball mux */
+	writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
+	writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
+
+	/* set up dll */
+	writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
+	sdelay(0x2000);	/* give time to lock */
+
+}
+/*********************************************************************
+ * config_sdram_ddr() - Init DDR on dev board.
+ *********************************************************************/
+void config_sdram_ddr(u8 cs, u8 cfg)
+{
+
+	writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
+	writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
+	writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
+	writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
+
+	writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+
+	sdelay(5000);
+
+	writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+
+	/* set mr0 */
+	writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
+
+	sdelay(2000);
+}
+
+/**
+ * @brief Initialize the SDRC module
+ * Initialisation for 1x256MByte but normally
+ * done by x-loader.
+ * @return void
+ */
+static void pcaal1_sdrc_init(void)
+{
+	u32 test0, test1;
+	char cfg;
+
+	init_sdram_ddr();
+
+	config_sdram_ddr(0, 0); /* 256MByte at CS0 */
+	config_sdram_ddr(1, 0); /* 256MByte at CS1 */
+
+	test0 = get_ram_size((long *) 0x80000000, SZ_256M);
+	test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
+
+	/* mask out lower nible, its not tested with
+	in common/memsize.c */
+	test1 &= 0xfffffff0;
+
+	if ((test1 > 0) && (test1 != test0))
+		hang();
+
+	cfg = -1; /* illegal configuration found */
+
+	if (test1 == 0) {
+		init_sdram_ddr();
+		writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
+
+		/* 1 x 256MByte */
+		if (test0 == SZ_256M)
+			cfg = 2;
+
+		if (cfg != -1) {
+			config_sdram_ddr(0, cfg);
+			writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
+		}
+		return;
+	}
+
+	/* reinit both cs with correct size */
+	/* 2 x 128MByte */
+	if (test0 == SZ_128M)
+		cfg = 1;
+	/* 2 x 256MByte */
+	if (test0 == SZ_256M)
+		cfg = 3;
+
+	if (cfg != -1) {
+		init_sdram_ddr();
+		writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
+		config_sdram_ddr(0, cfg);
+		config_sdram_ddr(1, cfg);
+	}
+}
+
+/**
+ * @brief Do the necessary pin muxing required for phyCARD-A-L1.
+ * Some pins in OMAP3 do not have alternate modes.
+ * We don't program these pins.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void pcaal1_mux_config(void)
+{
+	/*
+	 * Serial Interface
+	 */
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+
+	/* ETH_PME (GPIO_55) */
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M4));
+	/* #CS5 (Ethernet) */
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0));
+	/* ETH_FIFO_SEL (GPIO_57) */
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | EN  | M4));
+	/* ETH_AMDIX_EN (GPIO_58) */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M4));
+	/* ETH_nRST (GPIO_64) */
+	MUX_VAL(CP(GPMC_WAIT2),		(IDIS | PTU | EN  | M4));
+
+	/* HSMMC1 */
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
+
+	/* USBOTG_nRST (GPIO_63) */
+	MUX_VAL(CP(GPMC_WAIT1),		(IDIS | PTU | EN  | M4));
+
+	/* USBH_nRST (GPIO_65) */
+	MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | EN  | M4));
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int pcaal1_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	pcaal1_mux_config();
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		pcaal1_sdrc_init();
+
+	return 0;
+}
+pure_initcall(pcaal1_board_init);
+
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index db90e0e..234d689 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -51,264 +51,17 @@
 #include <asm/io.h>
 #include <generated/mach-types.h>
 #include <linux/err.h>
-#include <mach/control.h>
 #include <mach/gpmc.h>
 #include <mach/gpmc_nand.h>
 #include <mach/omap_hsmmc.h>
 #include <mach/xload.h>
-#include <mach/omap3-mux.h>
 #include <mach/sdrc.h>
 #include <mach/omap3-silicon.h>
 #include <mach/sys_info.h>
-#include <mach/syslib.h>
 #include <mach/omap3-devices.h>
 
 #define SMC911X_BASE 0x2c000000
 
-/* Slower full frequency range default timings for x32 operation */
-#define SDP_SDRC_SHARING	0x00000100
-/* Diabling power down mode using CKE pin */
-#define SDP_SDRC_POWER_POP	0x00000081
-/* rkw - need to find of 90/72 degree recommendation for speed like before. */
-#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
-	(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
-
-/* used to create an array of memory configuartions. */
-struct sdrc_config {
-	u32	cs_cfg;
-	u32	mcfg;
-	u32	mr;
-	u32	actim_ctrla;
-	u32	actim_ctrlb;
-	u32	rfr_ctrl;
-} const sdrc_config[] = {
-/* max cs_size for autodetection, common timing */
-/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
-{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
-/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
-{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
-/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
-{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
-/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
-{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
-};
-
-/*
- * Boot-time initialization(s)
- */
-
-/*********************************************************************
- * init_sdram_ddr() - Init DDR controller.
- *********************************************************************/
-void init_sdram_ddr(void)
-{
-	/* reset sdrc controller */
-	writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
-	wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
-	writel(0, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* setup sdrc to ball mux */
-	writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
-	writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
-
-	/* set up dll */
-	writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
-	sdelay(0x2000);	/* give time to lock */
-
-}
-/*********************************************************************
- * config_sdram_ddr() - Init DDR on dev board.
- *********************************************************************/
-void config_sdram_ddr(u8 cs, u8 cfg)
-{
-
-	writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
-	writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
-	writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
-	writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
-
-	writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-
-	sdelay(5000);
-
-	writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-
-	/* set mr0 */
-	writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
-
-	sdelay(2000);
-}
-
-/**
- * @brief Initialize the SDRC module
- * Initialisation for 1x256MByte but normally
- * done by x-loader.
- * @return void
- */
-static void pcaal1_sdrc_init(void)
-{
-	u32 test0, test1;
-	char cfg;
-
-	init_sdram_ddr();
-
-	config_sdram_ddr(0, 0); /* 256MByte at CS0 */
-	config_sdram_ddr(1, 0); /* 256MByte at CS1 */
-
-	test0 = get_ram_size((long *) 0x80000000, SZ_256M);
-	test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
-
-	/* mask out lower nible, its not tested with
-	in common/memsize.c */
-	test1 &= 0xfffffff0;
-
-	if ((test1 > 0) && (test1 != test0))
-		hang();
-
-	cfg = -1; /* illegal configuration found */
-
-	if (test1 == 0) {
-		init_sdram_ddr();
-		writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
-
-		/* 1 x 256MByte */
-		if (test0 == SZ_256M)
-			cfg = 2;
-
-		if (cfg != -1) {
-			config_sdram_ddr(0, cfg);
-			writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
-		}
-		return;
-	}
-
-	/* reinit both cs with correct size */
-	/* 2 x 128MByte */
-	if (test0 == SZ_128M)
-		cfg = 1;
-	/* 2 x 256MByte */
-	if (test0 == SZ_256M)
-		cfg = 3;
-
-	if (cfg != -1) {
-		init_sdram_ddr();
-		writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
-		config_sdram_ddr(0, cfg);
-		config_sdram_ddr(1, cfg);
-	}
-}
-
-/**
- * @brief Do the necessary pin muxing required for phyCARD-A-L1.
- * Some pins in OMAP3 do not have alternate modes.
- * We don't program these pins.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void pcaal1_mux_config(void)
-{
-	/*
-	 * Serial Interface
-	 */
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
-
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
-
-	/* ETH_PME (GPIO_55) */
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M4));
-	/* #CS5 (Ethernet) */
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0));
-	/* ETH_FIFO_SEL (GPIO_57) */
-	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | EN  | M4));
-	/* ETH_AMDIX_EN (GPIO_58) */
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M4));
-	/* ETH_nRST (GPIO_64) */
-	MUX_VAL(CP(GPMC_WAIT2),		(IDIS | PTU | EN  | M4));
-
-	/* HSMMC1 */
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
-
-	/* USBOTG_nRST (GPIO_63) */
-	MUX_VAL(CP(GPMC_WAIT1),		(IDIS | PTU | EN  | M4));
-
-	/* USBH_nRST (GPIO_65) */
-	MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | EN  | M4));
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int pcaal1_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	pcaal1_mux_config();
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		pcaal1_sdrc_init();
-
-	return 0;
-}
-pure_initcall(pcaal1_board_init);
-
-/*
- * Run-time initialization(s)
- */
-
 /**
  * @brief Initialize the serial port to be used as console.
  *
-- 
1.7.10.4


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[PATCH 3/6] ARM omap3 omap343xdsp: move lowlevel code to lowlevel.c

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/omap343xdsp/Makefile   |    2 +
 arch/arm/boards/omap343xdsp/board.c    |  547 --------------------------------
 arch/arm/boards/omap343xdsp/lowlevel.c |  546 +++++++++++++++++++++++++++++++
 3 files changed, 548 insertions(+), 547 deletions(-)
 create mode 100644 arch/arm/boards/omap343xdsp/lowlevel.c

diff --git a/arch/arm/boards/omap343xdsp/Makefile b/arch/arm/boards/omap343xdsp/Makefile
index dcfc293..88c223a 100644
--- a/arch/arm/boards/omap343xdsp/Makefile
+++ b/arch/arm/boards/omap343xdsp/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 6dbbc4c..215fe02 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -50,556 +50,9 @@
 #include <asm/armlinux.h>
 #include <mach/omap3-silicon.h>
 #include <mach/omap3-devices.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
-#include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <errno.h>
 
-/******************** Board Boot Time *******************/
-static void sdrc_init(void);
-static void mux_config(void);
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int sdp343x_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	mux_config();
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(sdp343x_board_init);
-
-/**
- * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* Issue SDRC Soft reset  */
-	writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
-    /* Wait until Reset complete */
-    while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
-    /* SDRC to normal mode */
-	writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC_REG(CS0 Configuration --------- */
-	/* SDRC_REG(MCFG0 register */
-	writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_REG(RFR_CTRL0 register */
-	writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_REG(ACTIM_CTRLA0 register */
-	writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_REG(ACTIM_CTRLB0 register */
-	writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_REG(Manual command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register */
-	/* CAS latency = 3 */
-	/* Write Burst = Read Burst */
-	/* Serial Mode */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));	/* Burst length =4 */
-
-    /* SDRC DLLA control register */
-	/* Enable DLL A */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-    /* wait until DLL is locked  */
-    while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
-	return;
-}
-
-/**
- * @brief Do the pin muxing required for Board operation.
- *
- * See @ref MUX_VAL for description of the muxing mode. Since some versions
- * of Linux depend on all pin muxing being done at barebox level, we may need to
- * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/* Essential MUX Settings */
-	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));	/* SDRC_D0 */
-	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));	/* SDRC_D1 */
-	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));	/* SDRC_D2 */
-	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));	/* SDRC_D3 */
-	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));	/* SDRC_D4 */
-	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));	/* SDRC_D5 */
-	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));	/* SDRC_D6 */
-	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));	/* SDRC_D7 */
-	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));	/* SDRC_D8 */
-	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));	/* SDRC_D9 */
-	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));	/* SDRC_D10 */
-	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));	/* SDRC_D11 */
-	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));	/* SDRC_D12 */
-	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));	/* SDRC_D13 */
-	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));	/* SDRC_D14 */
-	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));	/* SDRC_D15 */
-	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));	/* SDRC_D16 */
-	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));	/* SDRC_D17 */
-	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));	/* SDRC_D18 */
-	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));	/* SDRC_D19 */
-	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));	/* SDRC_D20 */
-	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));	/* SDRC_D21 */
-	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));	/* SDRC_D22 */
-	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));	/* SDRC_D23 */
-	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));	/* SDRC_D24 */
-	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));	/* SDRC_D25 */
-	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));	/* SDRC_D26 */
-	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));	/* SDRC_D27 */
-	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));	/* SDRC_D28 */
-	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));	/* SDRC_D29 */
-	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));	/* SDRC_D30 */
-	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));	/* SDRC_D31 */
-	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));	/* SDRC_CLK */
-	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));	/* SDRC_DQS0 */
-	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));	/* SDRC_DQS1 */
-	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));	/* SDRC_DQS2 */
-	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));	/* SDRC_DQS3 */
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));	/* GPMC_A1 */
-	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));	/* GPMC_A2 */
-	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));	/* GPMC_A3 */
-	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));	/* GPMC_A4 */
-	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));	/* GPMC_A5 */
-	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));	/* GPMC_A6 */
-	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));	/* GPMC_A7 */
-	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));	/* GPMC_A8 */
-	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));	/* GPMC_A9 */
-	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));	/* GPMC_A10 */
-	MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0));	/* GPMC_D0 */
-	MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0));	/* GPMC_D1 */
-	MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0));	/* GPMC_D2 */
-	MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0));	/* GPMC_D3 */
-	MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0));	/* GPMC_D4 */
-	MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0));	/* GPMC_D5 */
-	MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0));	/* GPMC_D6 */
-	MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0));	/* GPMC_D7 */
-	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));	/* GPMC_D8 */
-	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));	/* GPMC_D9 */
-	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));	/* GPMC_D10 */
-	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));	/* GPMC_D11 */
-	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));	/* GPMC_D12 */
-	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));	/* GPMC_D13 */
-	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));	/* GPMC_D14 */
-	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));	/* GPMC_D15 */
-	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));	/* GPMC_NCS0 */
-	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));	/* GPMC_NCS1 */
-	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));	/* GPMC_NCS2 */
-	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0));	/* GPMC_NCS3 */
-	/* GPIO_55 - FLASH_DIS */
-	MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
-	/* GPIO_56 - TORCH_EN */
-	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
-	/* GPIO_57 - AGPS SLP */
-	MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
-	/* GPMC_58 - WLAN_IRQ */
-	MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
-	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));	/* GPMC_CLK */
-	/* GPMC_NADV_ALE */
-	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));	/* GPMC_NOE */
-	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));	/* GPMC_NWE */
-	/* GPMC_NBE0_CLE */
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4));	/* GPIO_61 -BT_SHUTDN */
-	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));	/* GPMC_NWP */
-	MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));	/* GPMC_WAIT0 */
-	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));	/* GPMC_WAIT1 */
-	MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4));	/* GPIO_64 */
-	MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));	/* GPIO_65 */
-
-	/* SERIAL INTERFACE */
-	/* UART3_CTS_RCTX */
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
-	/* UART3_RTS_SD */
-	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
-	/* UART3_RX_IRRX */
-	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
-	/* UART3_TX_IRTX */
-	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
-	/* HSUSB0_CLK */
-	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
-	/* HSUSB0_STP */
-	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
-	/* HSUSB0_DIR */
-	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
-	/* HSUSB0_NXT */
-	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA0 */
-	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA1 */
-	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA2 */
-	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA3 */
-	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA4 */
-	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA5 */
-	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA6 */
-	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA7 */
-	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));	/* I2C1_SCL */
-	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));	/* I2C1_SDA */
-#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
-	/* DSS */
-	MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));	/* DSS_PCLK */
-	MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));	/* DSS_HSYNC */
-	MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));	/* DSS_VSYNC */
-	MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));	/* DSS_ACBIAS */
-	MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));	/* DSS_DATA0 */
-	MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));	/* DSS_DATA1 */
-	MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));	/* DSS_DATA2 */
-	MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));	/* DSS_DATA3 */
-	MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));	/* DSS_DATA4 */
-	MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));	/* DSS_DATA5 */
-	MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));	/* DSS_DATA6 */
-	MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));	/* DSS_DATA7 */
-	MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));	/* DSS_DATA8 */
-	MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));	/* DSS_DATA9 */
-	MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));	/* DSS_DATA10 */
-	MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));	/* DSS_DATA11 */
-	MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));	/* DSS_DATA12 */
-	MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));	/* DSS_DATA13 */
-	MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));	/* DSS_DATA14 */
-	MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));	/* DSS_DATA15 */
-	MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));	/* DSS_DATA16 */
-	MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));	/* DSS_DATA17 */
-	MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));	/* DSS_DATA18 */
-	MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));	/* DSS_DATA19 */
-	MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));	/* DSS_DATA20 */
-	MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));	/* DSS_DATA21 */
-	MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));	/* DSS_DATA22 */
-	MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));	/* DSS_DATA23 */
-	/* CAMERA */
-	MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0));	/* CAM_HS */
-	MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0));	/* CAM_VS */
-	MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0));	/* CAM_XCLKA */
-	MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0));	/* CAM_PCLK */
-	/* GPIO_98 - CAM_RESET */
-	MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
-	MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0));	/* CAM_D0 */
-	MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0));	/* CAM_D1 */
-	MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0));	/* CAM_D2 */
-	MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0));	/* CAM_D3 */
-	MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0));	/* CAM_D4 */
-	MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0));	/* CAM_D5 */
-	MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0));	/* CAM_D6 */
-	MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0));	/* CAM_D7 */
-	MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0));	/* CAM_D8 */
-	MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0));	/* CAM_D9 */
-	MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0));	/* CAM_D10 */
-	MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0));	/* CAM_D11 */
-	MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0));	/* CAM_XCLKB */
-	MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4));	/* GPIO_167 */
-	MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0));	/* CAM_STROBE */
-	MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0));	/* CSI2_DX0 */
-	MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0));	/* CSI2_DY0 */
-	MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0));	/* CSI2_DX1 */
-	MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0));	/* CSI2_DY1 */
-	/* AUDIO INTERFACE */
-	MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0));	/* MCBSP2_FSX */
-	/* MCBSP2_CLKX */
-	MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0));	/* MCBSP2_DR */
-	MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0));	/* MCBSP2_DX */
-	/* EXPANSION CARD  */
-	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));	/* MMC1_CLK */
-	MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));	/* MMC1_CMD */
-	MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));	/* MMC1_DAT0 */
-	MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));	/* MMC1_DAT1 */
-	MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));	/* MMC1_DAT2 */
-	MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));	/* MMC1_DAT3 */
-	MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0));	/* MMC1_DAT4 */
-	MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0));	/* MMC1_DAT5 */
-	MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0));	/* MMC1_DAT6 */
-	MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0));	/* MMC1_DAT7 */
-	/* WIRELESS LAN */
-	MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0));	/* MMC2_CLK */
-	MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0));	/* MMC2_CMD */
-	MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0));	/* MMC2_DAT0 */
-	MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0));	/* MMC2_DAT1 */
-	MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0));	/* MMC2_DAT2 */
-	MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0));	/* MMC2_DAT3 */
-	/* MMC2_DIR_DAT0 */
-	MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
-	/* MMC2_DIR_DAT1 */
-	MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
-	/* MMC2_DIR_CMD */
-	MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
-	/* MMC2_CLKIN */
-	MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
-	/* BLUETOOTH */
-	/* MCBSP3_DX */
-	MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
-	/* MCBSP3_DR */
-	MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
-	/* MCBSP3_CLKX */
-	MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
-	/* MCBSP3_FSX */
-	MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0));	/* UART2_CTS */
-	MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0));	/* UART2_RTS */
-	MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0));	/* UART2_TX */
-	MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0));	/* UART2_RX */
-	/* MODEM INTERFACE */
-	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));	/* UART1_TX */
-	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));	/* UART1_RTS */
-	MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));	/* UART1_CTS */
-	MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));	/* UART1_RX */
-	/* SSI1_DAT_RX */
-	MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
-	MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1));	/* SSI1_FLAG_RX */
-	MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1));	/* SSI1_RDY_RX  */
-	MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1));	/* SSI1_WAKE */
-	/* MCBSP1_CLKR  */
-	MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
-	/* GPIO_157 - BT_WKUP */
-	MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
-	/* MCBSP1_DX */
-	MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0));	/* MCBSP1_DR */
-	/* MCBSP_CLKS  */
-	MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
-	/* MCBSP1_FSX */
-	MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
-	/* MCBSP1_CLKX  */
-	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
-	/* SERIAL INTERFACE */
-	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));	/* I2C2_SCL */
-	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));	/* I2C2_SDA */
-	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));	/* I2C3_SCL */
-	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));	/* I2C3_SDA */
-	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));	/* I2C4_SCL */
-	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));	/* I2C4_SDA */
-	MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));	/* HDQ_SIO */
-	/* MCSPI1_CLK */
-	MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
-	/* MCSPI1_SIMO */
-	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
-	/* MCSPI1_SOMI */
-	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
-	/* MCSPI1_CS0 */
-	MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
-	/* MCSPI1_CS1 */
-	MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
-	/* GPIO_176-NOR_DPD */
-	MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
-	/* MCSPI1_CS3 */
-	MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
-	/* MCSPI2_CLK */
-	MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
-	/* MCSPI2_SIMO */
-	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
-	/* MCSPI2_SOMI */
-	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
-	/* MCSPI2_CS0 */
-	MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
-	/* MCSPI2_CS1 */
-	MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
-
-	/* CONTROL AND DEBUG */
-	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));	/* SYS_32K */
-	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));	/* SYS_CLKREQ */
-	MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));	/* SYS_NIRQ */
-	MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4));	/* GPIO_2 - PEN_IRQ */
-	MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4));	/* GPIO_3 */
-	MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4));	/* GPIO_4 - MMC1_WP */
-	MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4));	/* GPIO_5 - LCD_ENVDD */
-	MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4));	/* GPIO_6 - LAN_INTR0 */
-	MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4));	/* GPIO_7 - MMC2_WP */
-	/* GPIO_8-LCD_ENBKL */
-	MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
-	/* SYS_OFF_MODE */
-	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
-	/* SYS_CLKOUT1  */
-	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4));	/* GPIO_186 */
-	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));	/* JTAG_NTRST */
-	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));	/* JTAG_TCK */
-	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));	/* JTAG_TMS */
-	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));	/* JTAG_TDI */
-	MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));	/* JTAG_EMU0 */
-	MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));	/* JTAG_EMU1 */
-	/* HSUSB1_TLL_STP */
-	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
-	/* HSUSB1_TLL_CLK */
-	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA0 */
-	MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
-	/* MCSPI3_CS0 */
-	MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
-	/* HSUSB1_TLL_DATA2 */
-	MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
-	/* HSUSB1_TLL_DATA7 */
-	MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
-	/* HSUSB1_TLL_DATA4 */
-	MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA5 */
-	MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA6 */
-	MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA3 */
-	MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DIR */
-	MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_NXT */
-	MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_CLK */
-	MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_STP */
-	MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DIR */
-	MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_NXT */
-	MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DATA0 */
-	MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DATA1 */
-	MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
-
-	/* DIE TO DIE */
-	MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0));	/* D2D_MCAD0 */
-	MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));	/* D2D_MCAD1 */
-	MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));	/* D2D_MCAD2 */
-	MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));	/* D2D_MCAD3 */
-	MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));	/* D2D_MCAD4 */
-	MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));	/* D2D_MCAD5 */
-	MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));	/* D2D_MCAD6 */
-	MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));	/* D2D_MCAD7 */
-	MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));	/* D2D_MCAD8 */
-	MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));	/* D2D_MCAD9 */
-	MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));	/* D2D_MCAD10 */
-	MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));	/* D2D_MCAD11 */
-	MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));	/* D2D_MCAD12 */
-	MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));	/* D2D_MCAD13 */
-	MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));	/* D2D_MCAD14 */
-	MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));	/* D2D_MCAD15 */
-	MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));	/* D2D_MCAD16 */
-	MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));	/* D2D_MCAD17 */
-	MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));	/* D2D_MCAD18 */
-	MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));	/* D2D_MCAD19 */
-	MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));	/* D2D_MCAD20 */
-	MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));	/* D2D_MCAD21 */
-	MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));	/* D2D_MCAD22 */
-	MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));	/* D2D_MCAD23 */
-	MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));	/* D2D_MCAD24 */
-	MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));	/* D2D_MCAD25 */
-	MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));	/* D2D_MCAD26 */
-	MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));	/* D2D_MCAD27 */
-	MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));	/* D2D_MCAD28 */
-	MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));	/* D2D_MCAD29 */
-	MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));	/* D2D_MCAD30 */
-	MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));	/* D2D_MCAD31 */
-	MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));	/* D2D_MCAD32 */
-	MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));	/* D2D_MCAD33 */
-	MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));	/* D2D_MCAD34 */
-	MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));	/* D2D_MCAD35 */
-	MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));	/* D2D_MCAD36 */
-	/* D2D_CLK26MI  */
-	MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
-	/* D2D_NRESPWRON */
-	MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
-	/* D2D_NRESWARM */
-	MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
-	/* D2D_ARM9NIRQ */
-	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
-	/* D2D_UMA2P6FIQ */
-	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
-	/* D2D_SPINT */
-	MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
-	/* D2D_FRINT */
-	MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
-	/* D2D_DMAREQ0  */
-	MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ1  */
-	MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ2  */
-	MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ3  */
-	MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTRST  */
-	MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTDI */
-	MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTDO */
-	MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTMS */
-	MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTCK */
-	MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
-	/* D2D_N3GRTCK  */
-	MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
-	/* D2D_MSTDBY */
-	MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
-	/* D2D_SWAKEUP */
-	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
-	/* D2D_IDLEREQ */
-	MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
-	/* D2D_IDLEACK */
-	MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
-	/* D2D_MWRITE */
-	MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
-	/* D2D_SWRITE */
-	MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
-	/* D2D_MREAD */
-	MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
-	/* D2D_SREAD */
-	MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
-	/* D2D_MBUSFLAG */
-	MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
-	/* D2D_SBUSFLAG */
-	MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
-	/* SDRC_CKE0 */
-	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
-	/* SDRC_CKE1 NOT USED */
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
-#endif				/* CONFIG_MACH_OMAP_ADVANCED_MUX */
-}
-
-/******************** Board Run Time *******************/
-
 /*-----------------------CONSOLE  Devices -----------------------------------*/
 
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
new file mode 100644
index 0000000..0d2ccd4
--- /dev/null
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -0,0 +1,546 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+/**
+ * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* Issue SDRC Soft reset  */
+	writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* Wait until Reset complete */
+	while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
+	/* SDRC to normal mode */
+	writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC_REG(CS0 Configuration --------- */
+	/* SDRC_REG(MCFG0 register */
+	writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_REG(RFR_CTRL0 register */
+	writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_REG(ACTIM_CTRLA0 register */
+	writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_REG(ACTIM_CTRLB0 register */
+	writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_REG(Manual command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register */
+	/* CAS latency = 3 */
+	/* Write Burst = Read Burst */
+	/* Serial Mode */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));	/* Burst length =4 */
+
+	/* SDRC DLLA control register */
+	/* Enable DLL A */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	/* wait until DLL is locked  */
+	while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
+}
+
+/**
+ * @brief Do the pin muxing required for Board operation.
+ *
+ * See @ref MUX_VAL for description of the muxing mode. Since some versions
+ * of Linux depend on all pin muxing being done at barebox level, we may need to
+ * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/* Essential MUX Settings */
+	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));	/* SDRC_D0 */
+	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));	/* SDRC_D1 */
+	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));	/* SDRC_D2 */
+	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));	/* SDRC_D3 */
+	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));	/* SDRC_D4 */
+	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));	/* SDRC_D5 */
+	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));	/* SDRC_D6 */
+	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));	/* SDRC_D7 */
+	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));	/* SDRC_D8 */
+	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));	/* SDRC_D9 */
+	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));	/* SDRC_D10 */
+	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));	/* SDRC_D11 */
+	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));	/* SDRC_D12 */
+	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));	/* SDRC_D13 */
+	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));	/* SDRC_D14 */
+	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));	/* SDRC_D15 */
+	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));	/* SDRC_D16 */
+	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));	/* SDRC_D17 */
+	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));	/* SDRC_D18 */
+	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));	/* SDRC_D19 */
+	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));	/* SDRC_D20 */
+	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));	/* SDRC_D21 */
+	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));	/* SDRC_D22 */
+	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));	/* SDRC_D23 */
+	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));	/* SDRC_D24 */
+	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));	/* SDRC_D25 */
+	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));	/* SDRC_D26 */
+	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));	/* SDRC_D27 */
+	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));	/* SDRC_D28 */
+	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));	/* SDRC_D29 */
+	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));	/* SDRC_D30 */
+	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));	/* SDRC_D31 */
+	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));	/* SDRC_CLK */
+	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));	/* SDRC_DQS0 */
+	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));	/* SDRC_DQS1 */
+	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));	/* SDRC_DQS2 */
+	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));	/* SDRC_DQS3 */
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));	/* GPMC_A1 */
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));	/* GPMC_A2 */
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));	/* GPMC_A3 */
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));	/* GPMC_A4 */
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));	/* GPMC_A5 */
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));	/* GPMC_A6 */
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));	/* GPMC_A7 */
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));	/* GPMC_A8 */
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));	/* GPMC_A9 */
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));	/* GPMC_A10 */
+	MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0));	/* GPMC_D0 */
+	MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0));	/* GPMC_D1 */
+	MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0));	/* GPMC_D2 */
+	MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0));	/* GPMC_D3 */
+	MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0));	/* GPMC_D4 */
+	MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0));	/* GPMC_D5 */
+	MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0));	/* GPMC_D6 */
+	MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0));	/* GPMC_D7 */
+	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));	/* GPMC_D8 */
+	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));	/* GPMC_D9 */
+	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));	/* GPMC_D10 */
+	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));	/* GPMC_D11 */
+	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));	/* GPMC_D12 */
+	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));	/* GPMC_D13 */
+	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));	/* GPMC_D14 */
+	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));	/* GPMC_D15 */
+	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));	/* GPMC_NCS0 */
+	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));	/* GPMC_NCS1 */
+	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));	/* GPMC_NCS2 */
+	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0));	/* GPMC_NCS3 */
+	/* GPIO_55 - FLASH_DIS */
+	MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
+	/* GPIO_56 - TORCH_EN */
+	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
+	/* GPIO_57 - AGPS SLP */
+	MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
+	/* GPMC_58 - WLAN_IRQ */
+	MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
+	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));	/* GPMC_CLK */
+	/* GPMC_NADV_ALE */
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));	/* GPMC_NOE */
+	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));	/* GPMC_NWE */
+	/* GPMC_NBE0_CLE */
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4));	/* GPIO_61 -BT_SHUTDN */
+	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));	/* GPMC_NWP */
+	MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));	/* GPMC_WAIT0 */
+	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));	/* GPMC_WAIT1 */
+	MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4));	/* GPIO_64 */
+	MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));	/* GPIO_65 */
+
+	/* SERIAL INTERFACE */
+	/* UART3_CTS_RCTX */
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
+	/* UART3_RTS_SD */
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
+	/* UART3_RX_IRRX */
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+	/* UART3_TX_IRTX */
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+	/* HSUSB0_CLK */
+	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
+	/* HSUSB0_STP */
+	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
+	/* HSUSB0_DIR */
+	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
+	/* HSUSB0_NXT */
+	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA0 */
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA1 */
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA2 */
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA3 */
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA4 */
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA5 */
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA6 */
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA7 */
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));	/* I2C1_SCL */
+	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));	/* I2C1_SDA */
+#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
+	/* DSS */
+	MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));	/* DSS_PCLK */
+	MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));	/* DSS_HSYNC */
+	MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));	/* DSS_VSYNC */
+	MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));	/* DSS_ACBIAS */
+	MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));	/* DSS_DATA0 */
+	MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));	/* DSS_DATA1 */
+	MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));	/* DSS_DATA2 */
+	MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));	/* DSS_DATA3 */
+	MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));	/* DSS_DATA4 */
+	MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));	/* DSS_DATA5 */
+	MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));	/* DSS_DATA6 */
+	MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));	/* DSS_DATA7 */
+	MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));	/* DSS_DATA8 */
+	MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));	/* DSS_DATA9 */
+	MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));	/* DSS_DATA10 */
+	MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));	/* DSS_DATA11 */
+	MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));	/* DSS_DATA12 */
+	MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));	/* DSS_DATA13 */
+	MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));	/* DSS_DATA14 */
+	MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));	/* DSS_DATA15 */
+	MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));	/* DSS_DATA16 */
+	MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));	/* DSS_DATA17 */
+	MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));	/* DSS_DATA18 */
+	MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));	/* DSS_DATA19 */
+	MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));	/* DSS_DATA20 */
+	MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));	/* DSS_DATA21 */
+	MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));	/* DSS_DATA22 */
+	MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));	/* DSS_DATA23 */
+	/* CAMERA */
+	MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0));	/* CAM_HS */
+	MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0));	/* CAM_VS */
+	MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0));	/* CAM_XCLKA */
+	MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0));	/* CAM_PCLK */
+	/* GPIO_98 - CAM_RESET */
+	MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
+	MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0));	/* CAM_D0 */
+	MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0));	/* CAM_D1 */
+	MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0));	/* CAM_D2 */
+	MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0));	/* CAM_D3 */
+	MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0));	/* CAM_D4 */
+	MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0));	/* CAM_D5 */
+	MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0));	/* CAM_D6 */
+	MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0));	/* CAM_D7 */
+	MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0));	/* CAM_D8 */
+	MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0));	/* CAM_D9 */
+	MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0));	/* CAM_D10 */
+	MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0));	/* CAM_D11 */
+	MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0));	/* CAM_XCLKB */
+	MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4));	/* GPIO_167 */
+	MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0));	/* CAM_STROBE */
+	MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0));	/* CSI2_DX0 */
+	MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0));	/* CSI2_DY0 */
+	MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0));	/* CSI2_DX1 */
+	MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0));	/* CSI2_DY1 */
+	/* AUDIO INTERFACE */
+	MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0));	/* MCBSP2_FSX */
+	/* MCBSP2_CLKX */
+	MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0));	/* MCBSP2_DR */
+	MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0));	/* MCBSP2_DX */
+	/* EXPANSION CARD  */
+	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));	/* MMC1_CLK */
+	MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));	/* MMC1_CMD */
+	MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));	/* MMC1_DAT0 */
+	MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));	/* MMC1_DAT1 */
+	MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));	/* MMC1_DAT2 */
+	MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));	/* MMC1_DAT3 */
+	MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0));	/* MMC1_DAT4 */
+	MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0));	/* MMC1_DAT5 */
+	MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0));	/* MMC1_DAT6 */
+	MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0));	/* MMC1_DAT7 */
+	/* WIRELESS LAN */
+	MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0));	/* MMC2_CLK */
+	MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0));	/* MMC2_CMD */
+	MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0));	/* MMC2_DAT0 */
+	MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0));	/* MMC2_DAT1 */
+	MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0));	/* MMC2_DAT2 */
+	MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0));	/* MMC2_DAT3 */
+	/* MMC2_DIR_DAT0 */
+	MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
+	/* MMC2_DIR_DAT1 */
+	MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
+	/* MMC2_DIR_CMD */
+	MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
+	/* MMC2_CLKIN */
+	MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
+	/* BLUETOOTH */
+	/* MCBSP3_DX */
+	MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
+	/* MCBSP3_DR */
+	MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
+	/* MCBSP3_CLKX */
+	MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
+	/* MCBSP3_FSX */
+	MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0));	/* UART2_CTS */
+	MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0));	/* UART2_RTS */
+	MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0));	/* UART2_TX */
+	MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0));	/* UART2_RX */
+	/* MODEM INTERFACE */
+	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));	/* UART1_TX */
+	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));	/* UART1_RTS */
+	MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));	/* UART1_CTS */
+	MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));	/* UART1_RX */
+	/* SSI1_DAT_RX */
+	MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
+	MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1));	/* SSI1_FLAG_RX */
+	MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1));	/* SSI1_RDY_RX  */
+	MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1));	/* SSI1_WAKE */
+	/* MCBSP1_CLKR  */
+	MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
+	/* GPIO_157 - BT_WKUP */
+	MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
+	/* MCBSP1_DX */
+	MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0));	/* MCBSP1_DR */
+	/* MCBSP_CLKS  */
+	MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
+	/* MCBSP1_FSX */
+	MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
+	/* MCBSP1_CLKX  */
+	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
+	/* SERIAL INTERFACE */
+	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));	/* I2C2_SCL */
+	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));	/* I2C2_SDA */
+	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));	/* I2C3_SCL */
+	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));	/* I2C3_SDA */
+	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));	/* I2C4_SCL */
+	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));	/* I2C4_SDA */
+	MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));	/* HDQ_SIO */
+	/* MCSPI1_CLK */
+	MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
+	/* MCSPI1_SIMO */
+	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
+	/* MCSPI1_SOMI */
+	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
+	/* MCSPI1_CS0 */
+	MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
+	/* MCSPI1_CS1 */
+	MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
+	/* GPIO_176-NOR_DPD */
+	MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
+	/* MCSPI1_CS3 */
+	MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
+	/* MCSPI2_CLK */
+	MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
+	/* MCSPI2_SIMO */
+	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
+	/* MCSPI2_SOMI */
+	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
+	/* MCSPI2_CS0 */
+	MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
+	/* MCSPI2_CS1 */
+	MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
+
+	/* CONTROL AND DEBUG */
+	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));	/* SYS_32K */
+	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));	/* SYS_CLKREQ */
+	MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));	/* SYS_NIRQ */
+	MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4));	/* GPIO_2 - PEN_IRQ */
+	MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4));	/* GPIO_3 */
+	MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4));	/* GPIO_4 - MMC1_WP */
+	MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4));	/* GPIO_5 - LCD_ENVDD */
+	MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4));	/* GPIO_6 - LAN_INTR0 */
+	MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4));	/* GPIO_7 - MMC2_WP */
+	/* GPIO_8-LCD_ENBKL */
+	MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
+	/* SYS_OFF_MODE */
+	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+	/* SYS_CLKOUT1  */
+	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4));	/* GPIO_186 */
+	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));	/* JTAG_NTRST */
+	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));	/* JTAG_TCK */
+	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));	/* JTAG_TMS */
+	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));	/* JTAG_TDI */
+	MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));	/* JTAG_EMU0 */
+	MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));	/* JTAG_EMU1 */
+	/* HSUSB1_TLL_STP */
+	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+	/* HSUSB1_TLL_CLK */
+	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA0 */
+	MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
+	/* MCSPI3_CS0 */
+	MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
+	/* HSUSB1_TLL_DATA2 */
+	MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
+	/* HSUSB1_TLL_DATA7 */
+	MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
+	/* HSUSB1_TLL_DATA4 */
+	MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA5 */
+	MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA6 */
+	MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA3 */
+	MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DIR */
+	MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_NXT */
+	MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_CLK */
+	MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_STP */
+	MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DIR */
+	MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_NXT */
+	MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DATA0 */
+	MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DATA1 */
+	MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+
+	/* DIE TO DIE */
+	MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0));	/* D2D_MCAD0 */
+	MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));	/* D2D_MCAD1 */
+	MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));	/* D2D_MCAD2 */
+	MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));	/* D2D_MCAD3 */
+	MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));	/* D2D_MCAD4 */
+	MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));	/* D2D_MCAD5 */
+	MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));	/* D2D_MCAD6 */
+	MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));	/* D2D_MCAD7 */
+	MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));	/* D2D_MCAD8 */
+	MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));	/* D2D_MCAD9 */
+	MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));	/* D2D_MCAD10 */
+	MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));	/* D2D_MCAD11 */
+	MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));	/* D2D_MCAD12 */
+	MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));	/* D2D_MCAD13 */
+	MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));	/* D2D_MCAD14 */
+	MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));	/* D2D_MCAD15 */
+	MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));	/* D2D_MCAD16 */
+	MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));	/* D2D_MCAD17 */
+	MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));	/* D2D_MCAD18 */
+	MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));	/* D2D_MCAD19 */
+	MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));	/* D2D_MCAD20 */
+	MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));	/* D2D_MCAD21 */
+	MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));	/* D2D_MCAD22 */
+	MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));	/* D2D_MCAD23 */
+	MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));	/* D2D_MCAD24 */
+	MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));	/* D2D_MCAD25 */
+	MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));	/* D2D_MCAD26 */
+	MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));	/* D2D_MCAD27 */
+	MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));	/* D2D_MCAD28 */
+	MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));	/* D2D_MCAD29 */
+	MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));	/* D2D_MCAD30 */
+	MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));	/* D2D_MCAD31 */
+	MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));	/* D2D_MCAD32 */
+	MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));	/* D2D_MCAD33 */
+	MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));	/* D2D_MCAD34 */
+	MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));	/* D2D_MCAD35 */
+	MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));	/* D2D_MCAD36 */
+	/* D2D_CLK26MI  */
+	MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+	/* D2D_NRESPWRON */
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+	/* D2D_NRESWARM */
+	MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+	/* D2D_ARM9NIRQ */
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+	/* D2D_UMA2P6FIQ */
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+	/* D2D_SPINT */
+	MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+	/* D2D_FRINT */
+	MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+	/* D2D_DMAREQ0  */
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ1  */
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ2  */
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ3  */
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTRST  */
+	MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTDI */
+	MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTDO */
+	MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTMS */
+	MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTCK */
+	MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+	/* D2D_N3GRTCK  */
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+	/* D2D_MSTDBY */
+	MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+	/* D2D_SWAKEUP */
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+	/* D2D_IDLEREQ */
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+	/* D2D_IDLEACK */
+	MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+	/* D2D_MWRITE */
+	MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+	/* D2D_SWRITE */
+	MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+	/* D2D_MREAD */
+	MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+	/* D2D_SREAD */
+	MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+	/* D2D_MBUSFLAG */
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+	/* D2D_SBUSFLAG */
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+	/* SDRC_CKE0 */
+	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+	/* SDRC_CKE1 NOT USED */
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+#endif				/* CONFIG_MACH_OMAP_ADVANCED_MUX */
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int sdp343x_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	mux_config();
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(sdp343x_board_init);
-- 
1.7.10.4


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[PATCH 4/6] ARM omap3 omap3evm: move lowlevel code to lowlevel.c

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/omap3evm/Makefile   |    2 +
 arch/arm/boards/omap3evm/board.c    |  158 ----------------------------------
 arch/arm/boards/omap3evm/lowlevel.c |  160 +++++++++++++++++++++++++++++++++++
 3 files changed, 162 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/boards/omap3evm/lowlevel.c

diff --git a/arch/arm/boards/omap3evm/Makefile b/arch/arm/boards/omap3evm/Makefile
index dcfc293..88c223a 100644
--- a/arch/arm/boards/omap3evm/Makefile
+++ b/arch/arm/boards/omap3evm/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c
index f636fe3..7585541 100644
--- a/arch/arm/boards/omap3evm/board.c
+++ b/arch/arm/boards/omap3evm/board.c
@@ -47,170 +47,12 @@
 #include <ns16550.h>
 #include <asm/armlinux.h>
 #include <mach/omap3-silicon.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
 #include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <errno.h>
 #include <generated/mach-types.h>
 #include <mach/omap3-devices.h>
 
-
-/*
- * Boot-time initialization(s)
- */
-
-/**
- * @brief Initialize the SDRC module
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* SDRAM software reset */
-	/* No idle ack and RESET enable */
-	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
-	sdelay(100);
-	/* No idle ack and RESET disable */
-	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC Registers Configuration --------- */
-	/* SDRC_MCFG0 register */
-	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_RFR_CTRL0 register */
-	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_ACTIM_CTRLA0 register */
-	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_ACTIM_CTRLB0 register */
-	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE due to 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_MANUAL command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register Burst length=4 */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
-
-	/* SDRC DLLA control register */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-	return;
-}
-
-/**
- * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
- * do not have alternate modes. We don't program these pins.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/*
-	 * SDRC
-	 * - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
-	 */
-
-	/*
-	 * GPMC
-	 * - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
-	 * - GPMC_NADV_ALE: Default MUX mode is mode0.
-	 * - GPMC_NOE: Default MUX mode is mode0.
-	 * - GPMC_NWE: Default MUX mode is mode0.
-	 * - GPMC_WAIT0: Default MUX mode is mode0.
-	 */
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
-
-	/*
-	 * Serial Interface
-	 */
-#if defined(CONFIG_OMAP3EVM_UART1)
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
-#elif defined(CONFIG_OMAP3EVM_UART3)
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
-#endif
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int omap3_evm_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	omap3_core_init();
-
-	mux_config();
-
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(omap3_evm_board_init);
-
-/*
- * Run-time initialization(s)
- */
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
new file mode 100644
index 0000000..9050c09
--- /dev/null
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -0,0 +1,160 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+
+/*
+ * Boot-time initialization(s)
+ */
+
+/**
+ * @brief Initialize the SDRC module
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* SDRAM software reset */
+	/* No idle ack and RESET enable */
+	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
+	sdelay(100);
+	/* No idle ack and RESET disable */
+	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC Registers Configuration --------- */
+	/* SDRC_MCFG0 register */
+	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_RFR_CTRL0 register */
+	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_ACTIM_CTRLA0 register */
+	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_ACTIM_CTRLB0 register */
+	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE due to 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_MANUAL command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register Burst length=4 */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
+
+	/* SDRC DLLA control register */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	return;
+}
+
+/**
+ * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
+ * do not have alternate modes. We don't program these pins.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/*
+	 * SDRC
+	 * - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
+	 */
+
+	/*
+	 * GPMC
+	 * - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
+	 * - GPMC_NADV_ALE: Default MUX mode is mode0.
+	 * - GPMC_NOE: Default MUX mode is mode0.
+	 * - GPMC_NWE: Default MUX mode is mode0.
+	 * - GPMC_WAIT0: Default MUX mode is mode0.
+	 */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
+
+	/*
+	 * Serial Interface
+	 */
+#if defined(CONFIG_OMAP3EVM_UART1)
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
+#elif defined(CONFIG_OMAP3EVM_UART3)
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
+#endif
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int omap3_evm_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	omap3_core_init();
+
+	mux_config();
+
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(omap3_evm_board_init);
-- 
1.7.10.4


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[PATCH 5/6] ARM am33xx beaglebone: move lowlevel code to lowlevel.c

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beaglebone/Makefile   |    2 +
 arch/arm/boards/beaglebone/board.c    |  240 -------------------------------
 arch/arm/boards/beaglebone/lowlevel.c |  248 +++++++++++++++++++++++++++++++++
 3 files changed, 250 insertions(+), 240 deletions(-)
 create mode 100644 arch/arm/boards/beaglebone/lowlevel.c

diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
index dcfc293..88c223a 100644
--- a/arch/arm/boards/beaglebone/Makefile
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index f9ac7a4..6eb2c0a 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -48,246 +48,6 @@
 #include <mach/am33xx-mux.h>
 #include <mach/wdt.h>
 
-/* UART Defines */
-#define UART_SYSCFG_OFFSET  (0x54)
-#define UART_SYSSTS_OFFSET  (0x58)
-
-#define UART_RESET      (0x1 << 1)
-#define UART_CLK_RUNNING_MASK   0x1
-#define UART_SMART_IDLE_EN  (0x1 << 0x3)
-
-/* AM335X EMIF Register values */
-#define EMIF_SDMGT		0x80000000
-#define EMIF_SDRAM		0x00004650
-#define EMIF_PHYCFG		0x2
-#define DDR_PHY_RESET		(0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN	0x1
-#define DDR_PHY_READY		(0x1 << 2)
-#define	VTP_CTRL_READY		(0x1 << 5)
-#define VTP_CTRL_ENABLE		(0x1 << 6)
-#define VTP_CTRL_LOCK_EN	(0x1 << 4)
-#define VTP_CTRL_START_EN	(0x1)
-#define DDR2_RATIO		0x80	/* for mDDR */
-#define CMD_FORCE		0x00	/* common #def */
-#define CMD_DELAY		0x00
-
-#define EMIF_READ_LATENCY	0x05
-#define EMIF_TIM1		0x0666B3D6
-#define EMIF_TIM2		0x143731DA
-#define	EMIF_TIM3		0x00000347
-#define EMIF_SDCFG		0x43805332
-#define EMIF_SDREF		0x0000081a
-#define DDR2_DLL_LOCK_DIFF	0x0
-#define DDR2_RD_DQS		0x12
-#define DDR2_PHY_FIFO_WE	0x80
-
-#define	DDR2_INVERT_CLKOUT	0x00
-#define	DDR2_WR_DQS		0x00
-#define	DDR2_PHY_WRLVL		0x00
-#define	DDR2_PHY_GATELVL	0x00
-#define	DDR2_PHY_WR_DATA	0x40
-#define	PHY_RANK0_DELAY		0x01
-#define PHY_DLL_LOCK_DIFF	0x0
-#define DDR_IOCTRL_VALUE	0x18B
-
-static void beaglebone_data_macro_config(int dataMacroNum)
-{
-	u32 BaseAddrOffset = 0x00;;
-
-	if (dataMacroNum == 1)
-		BaseAddrOffset = 0xA4;
-
-	__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-		|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_RD_DQS>>2,
-		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-		|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_WR_DQS>>2,
-		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-		|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-		(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_WRLVL>>2,
-		(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-		|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-		(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_GATELVL>>2,
-		(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-		|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_FIFO_WE>>2,
-		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-		|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_WR_DATA>>2,
-		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(PHY_DLL_LOCK_DIFF,
-		(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
-}
-
-static void beaglebone_cmd_macro_config(void)
-{
-	__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
-
-	__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
-
-	__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
-}
-
-static void beaglebone_config_vtp(void)
-{
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
-		AM33XX_VTP0_CTRL_REG);
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
-		AM33XX_VTP0_CTRL_REG);
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
-		AM33XX_VTP0_CTRL_REG);
-
-	/* Poll for READY */
-	while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
-}
-
-static void beaglebone_config_emif_ddr2(void)
-{
-	u32 i;
-
-	/*Program EMIF0 CFG Registers*/
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
-	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
-	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
-	for (i = 0; i < 5000; i++) {
-
-	}
-
-	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
-	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-}
-
-static void beaglebone_config_ddr(void)
-{
-	enable_ddr_clocks();
-
-	beaglebone_config_vtp();
-
-	beaglebone_cmd_macro_config();
-	beaglebone_data_macro_config(0);
-	beaglebone_data_macro_config(1);
-
-	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
-	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
-
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
-
-	__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
-	__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
-
-	beaglebone_config_emif_ddr2();
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void beaglebone_sram_init(void)
-{
-	u32 regVal, uart_base;
-
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	beaglebone_config_ddr();
-
-	/* UART softreset */
-	uart_base = AM33XX_UART0_BASE;
-
-	regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
-	regVal |= UART_RESET;
-	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
-	while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
-
-	/* Disable smart idle */
-	regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
-	regVal |= UART_SMART_IDLE_EN;
-	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
-}
-
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int beaglebone_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		beaglebone_sram_init();
-
-	/* Enable pin mux */
-	enable_uart0_pin_mux();
-
-	return 0;
-}
-pure_initcall(beaglebone_board_init);
-
-/******************** Board Run Time *******************/
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
new file mode 100644
index 0000000..d446e8d
--- /dev/null
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -0,0 +1,248 @@
+#include <init.h>
+#include <sizes.h>
+#include <io.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/am33xx-mux.h>
+#include <mach/wdt.h>
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET  (0x54)
+#define UART_SYSSTS_OFFSET  (0x58)
+
+#define UART_RESET      (0x1 << 1)
+#define UART_CLK_RUNNING_MASK   0x1
+#define UART_SMART_IDLE_EN  (0x1 << 0x3)
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT		0x80000000
+#define EMIF_SDRAM		0x00004650
+#define EMIF_PHYCFG		0x2
+#define DDR_PHY_RESET		(0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN	0x1
+#define DDR_PHY_READY		(0x1 << 2)
+#define	VTP_CTRL_READY		(0x1 << 5)
+#define VTP_CTRL_ENABLE		(0x1 << 6)
+#define VTP_CTRL_LOCK_EN	(0x1 << 4)
+#define VTP_CTRL_START_EN	(0x1)
+#define DDR2_RATIO		0x80	/* for mDDR */
+#define CMD_FORCE		0x00	/* common #def */
+#define CMD_DELAY		0x00
+
+#define EMIF_READ_LATENCY	0x05
+#define EMIF_TIM1		0x0666B3D6
+#define EMIF_TIM2		0x143731DA
+#define	EMIF_TIM3		0x00000347
+#define EMIF_SDCFG		0x43805332
+#define EMIF_SDREF		0x0000081a
+#define DDR2_DLL_LOCK_DIFF	0x0
+#define DDR2_RD_DQS		0x12
+#define DDR2_PHY_FIFO_WE	0x80
+
+#define	DDR2_INVERT_CLKOUT	0x00
+#define	DDR2_WR_DQS		0x00
+#define	DDR2_PHY_WRLVL		0x00
+#define	DDR2_PHY_GATELVL	0x00
+#define	DDR2_PHY_WR_DATA	0x40
+#define	PHY_RANK0_DELAY		0x01
+#define PHY_DLL_LOCK_DIFF	0x0
+#define DDR_IOCTRL_VALUE	0x18B
+
+static void beaglebone_data_macro_config(int dataMacroNum)
+{
+	u32 BaseAddrOffset = 0x00;;
+
+	if (dataMacroNum == 1)
+		BaseAddrOffset = 0xA4;
+
+	__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+		|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_RD_DQS>>2,
+		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+		|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_WR_DQS>>2,
+		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+		|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+		(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_WRLVL>>2,
+		(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+		|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+		(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_GATELVL>>2,
+		(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+		|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_FIFO_WE>>2,
+		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+		|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_WR_DATA>>2,
+		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(PHY_DLL_LOCK_DIFF,
+		(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
+}
+
+static void beaglebone_cmd_macro_config(void)
+{
+	__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
+
+	__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
+
+	__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
+}
+
+static void beaglebone_config_vtp(void)
+{
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
+		AM33XX_VTP0_CTRL_REG);
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
+		AM33XX_VTP0_CTRL_REG);
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
+		AM33XX_VTP0_CTRL_REG);
+
+	/* Poll for READY */
+	while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
+}
+
+static void beaglebone_config_emif_ddr2(void)
+{
+	u32 i;
+
+	/*Program EMIF0 CFG Registers*/
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
+	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
+	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
+	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
+	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
+	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
+	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+
+	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+	for (i = 0; i < 5000; i++) {
+
+	}
+
+	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+}
+
+static void beaglebone_config_ddr(void)
+{
+	enable_ddr_clocks();
+
+	beaglebone_config_vtp();
+
+	beaglebone_cmd_macro_config();
+	beaglebone_data_macro_config(0);
+	beaglebone_data_macro_config(1);
+
+	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
+	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
+
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
+
+	__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
+	__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
+
+	beaglebone_config_emif_ddr2();
+}
+
+/*
+ * early system init of muxing and clocks.
+ */
+void beaglebone_sram_init(void)
+{
+	u32 regVal, uart_base;
+
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	beaglebone_config_ddr();
+
+	/* UART softreset */
+	uart_base = AM33XX_UART0_BASE;
+
+	regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
+	regVal |= UART_RESET;
+	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
+	while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
+
+	/* Disable smart idle */
+	regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
+	regVal |= UART_SMART_IDLE_EN;
+	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
+}
+
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int beaglebone_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
+	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
+	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		beaglebone_sram_init();
+
+	/* Enable pin mux */
+	enable_uart0_pin_mux();
+
+	return 0;
+}
+pure_initcall(beaglebone_board_init);
-- 
1.7.10.4


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[PATCH 6/6] ARM omap3 beagle: Compile xload defconfig in Thumb2 mode

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/omap3530_beagle_xload_defconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig
index d951b1c..383ea28 100644
--- a/arch/arm/configs/omap3530_beagle_xload_defconfig
+++ b/arch/arm/configs/omap3530_beagle_xload_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARCH_OMAP=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_BEAGLE=y
-CONFIG_AEABI=y
+CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 # CONFIG_ARM_EXCEPTIONS is not set
 CONFIG_TEXT_BASE=0x40200000
-- 
1.7.10.4


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