* [PATCH 1/7] tegra: move address map to tegra20-silicon.h
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 9:22 ` [PATCH 2/7] tegra: remove debug_ll Lucas Stach
` (6 subsequent siblings)
7 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
The address map is specific to the Tegra20 SoC. Move it to a
file with an appropriate name. While at it clarify and fix
the definitions.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/boards/toshiba-ac100/board.c | 2 +-
arch/arm/boards/toshiba-ac100/serial.c | 2 +-
arch/arm/mach-tegra/clock.c | 2 +-
arch/arm/mach-tegra/include/mach/debug_ll.h | 2 +-
arch/arm/mach-tegra/include/mach/iomap.h | 292 ---------------------
arch/arm/mach-tegra/include/mach/tegra20-silicon.h | 229 ++++++++++++++++
arch/arm/mach-tegra/reset.c | 2 +-
7 files changed, 234 insertions(+), 297 deletions(-)
delete mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
create mode 100644 arch/arm/mach-tegra/include/mach/tegra20-silicon.h
diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c
index 0eb85c5..af397cc 100644
--- a/arch/arm/boards/toshiba-ac100/board.c
+++ b/arch/arm/boards/toshiba-ac100/board.c
@@ -21,7 +21,7 @@
#include <asm/armlinux.h>
#include <sizes.h>
#include <usb/ehci.h>
-#include <mach/iomap.h>
+#include <mach/tegra20-silicon.h>
static int ac100_mem_init(void)
{
diff --git a/arch/arm/boards/toshiba-ac100/serial.c b/arch/arm/boards/toshiba-ac100/serial.c
index 880270d..cdd47ab 100644
--- a/arch/arm/boards/toshiba-ac100/serial.c
+++ b/arch/arm/boards/toshiba-ac100/serial.c
@@ -21,7 +21,7 @@
#include <ns16550.h>
#include <asm/io.h>
#include <asm/common.h>
-#include <mach/iomap.h>
+#include <mach/tegra20-silicon.h>
static struct NS16550_plat serial_plat = {
.clock = 0x75 * 115200 * 16 /* MODE_X_DIV */,
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 82065ee..8a7525d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -26,7 +26,7 @@
#include <linux/clk.h>
#include <init.h>
#include <asm/io.h>
-#include <mach/iomap.h>
+#include <mach/tegra20-silicon.h>
static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
index 290ad58..4a54e44 100644
--- a/arch/arm/mach-tegra/include/mach/debug_ll.h
+++ b/arch/arm/mach-tegra/include/mach/debug_ll.h
@@ -22,7 +22,7 @@
#define __INCLUDE_ARCH_DEBUG_LL_H__
#include <asm/io.h>
-#include <mach/iomap.h>
+#include <mach/tegra20-silicon.h>
#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
#define DEBUG_LL_UART_RSHFT 2
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
deleted file mode 100644
index ba478e7..0000000
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/iomap.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- * Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IOMAP_H
-#define __MACH_TEGRA_IOMAP_H
-
-#include <sizes.h>
-
-#define TEGRA_IRAM_BASE 0x40000000
-#define TEGRA_IRAM_SIZE SZ_256K
-
-#define TEGRA_HOST1X_BASE 0x50000000
-#define TEGRA_HOST1X_SIZE 0x24000
-
-#define TEGRA_ARM_PERIF_BASE 0x50040000
-#define TEGRA_ARM_PERIF_SIZE SZ_8K
-
-#define TEGRA_ARM_PL310_BASE 0x50043000
-#define TEGRA_ARM_PL310_SIZE SZ_4K
-
-#define TEGRA_ARM_INT_DIST_BASE 0x50041000
-#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
-
-#define TEGRA_MPE_BASE 0x54040000
-#define TEGRA_MPE_SIZE SZ_256K
-
-#define TEGRA_VI_BASE 0x54080000
-#define TEGRA_VI_SIZE SZ_256K
-
-#define TEGRA_ISP_BASE 0x54100000
-#define TEGRA_ISP_SIZE SZ_256K
-
-#define TEGRA_DISPLAY_BASE 0x54200000
-#define TEGRA_DISPLAY_SIZE SZ_256K
-
-#define TEGRA_DISPLAY2_BASE 0x54240000
-#define TEGRA_DISPLAY2_SIZE SZ_256K
-
-#define TEGRA_HDMI_BASE 0x54280000
-#define TEGRA_HDMI_SIZE SZ_256K
-
-#define TEGRA_GART_BASE 0x58000000
-#define TEGRA_GART_SIZE SZ_32M
-
-#define TEGRA_RES_SEMA_BASE 0x60001000
-#define TEGRA_RES_SEMA_SIZE SZ_4K
-
-#define TEGRA_HDMI_BASE 0x54280000
-#define TEGRA_HDMI_SIZE SZ_256K
-
-#define TEGRA_GART_BASE 0x58000000
-#define TEGRA_GART_SIZE SZ_32M
-
-#define TEGRA_RES_SEMA_BASE 0x60001000
-#define TEGRA_RES_SEMA_SIZE SZ_4K
-
-#define TEGRA_ARB_SEMA_BASE 0x60002000
-#define TEGRA_ARB_SEMA_SIZE SZ_4K
-
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE 64
-
-#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
-#define TEGRA_ARBGNT_ICTLR_SIZE 192
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE 64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE 64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE 64
-
-#define TEGRA_TMR1_BASE 0x60005000
-#define TEGRA_TMR1_SIZE 8
-
-#define TEGRA_TMR2_BASE 0x60005008
-#define TEGRA_TMR2_SIZE 8
-
-#define TEGRA_TMRUS_BASE 0x60005010
-#define TEGRA_TMRUS_SIZE 64
-
-#define TEGRA_TMR3_BASE 0x60005050
-#define TEGRA_TMR3_SIZE 8
-
-#define TEGRA_TMR4_BASE 0x60005058
-#define TEGRA_TMR4_SIZE 8
-
-#define TEGRA_CLK_RESET_BASE 0x60006000
-#define TEGRA_CLK_RESET_SIZE SZ_4K
-
-#define TEGRA_FLOW_CTRL_BASE 0x60007000
-#define TEGRA_FLOW_CTRL_SIZE 20
-
-#define TEGRA_AHB_DMA_BASE 0x60008000
-#define TEGRA_AHB_DMA_SIZE SZ_4K
-
-#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
-#define TEGRA_AHB_DMA_CH0_SIZE 32
-
-#define TEGRA_APB_DMA_BASE 0x6000A000
-#define TEGRA_APB_DMA_SIZE SZ_4K
-
-#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
-#define TEGRA_APB_DMA_CH0_SIZE 32
-
-#define TEGRA_AHB_GIZMO_BASE 0x6000C004
-#define TEGRA_AHB_GIZMO_SIZE 0x10C
-
-#define TEGRA_STATMON_BASE 0x6000C400
-#define TEGRA_STATMON_SIZE SZ_1K
-
-#define TEGRA_GPIO_BASE 0x6000D000
-#define TEGRA_GPIO_SIZE SZ_4K
-
-#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
-#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
-
-#define TEGRA_VDE_BASE 0x6001A000
-#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256)
-
-#define TEGRA_APB_MISC_BASE 0x70000000
-#define TEGRA_APB_MISC_SIZE SZ_4K
-
-#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
-#define TEGRA_APB_MISC_DAS_SIZE SZ_128
-
-#define TEGRA_AC97_BASE 0x70002000
-#define TEGRA_AC97_SIZE SZ_512
-
-#define TEGRA_SPDIF_BASE 0x70002400
-#define TEGRA_SPDIF_SIZE SZ_512
-
-#define TEGRA_I2S1_BASE 0x70002800
-#define TEGRA_I2S1_SIZE SZ_256
-
-#define TEGRA_I2S2_BASE 0x70002A00
-#define TEGRA_I2S2_SIZE SZ_256
-
-#define TEGRA_UARTA_BASE 0x70006000
-#define TEGRA_UARTA_SIZE 64
-
-#define TEGRA_UARTB_BASE 0x70006040
-#define TEGRA_UARTB_SIZE 64
-
-#define TEGRA_UARTC_BASE 0x70006200
-#define TEGRA_UARTC_SIZE SZ_256
-
-#define TEGRA_UARTD_BASE 0x70006300
-#define TEGRA_UARTD_SIZE SZ_256
-
-#define TEGRA_UARTE_BASE 0x70006400
-#define TEGRA_UARTE_SIZE SZ_256
-
-#define TEGRA_NAND_BASE 0x70008000
-#define TEGRA_NAND_SIZE SZ_256
-
-#define TEGRA_HSMMC_BASE 0x70008500
-#define TEGRA_HSMMC_SIZE SZ_256
-
-#define TEGRA_SNOR_BASE 0x70009000
-#define TEGRA_SNOR_SIZE SZ_4K
-
-#define TEGRA_PWFM_BASE 0x7000A000
-#define TEGRA_PWFM_SIZE SZ_256
-
-#define TEGRA_PWFM0_BASE 0x7000A000
-#define TEGRA_PWFM0_SIZE 4
-
-#define TEGRA_PWFM1_BASE 0x7000A010
-#define TEGRA_PWFM1_SIZE 4
-
-#define TEGRA_PWFM2_BASE 0x7000A020
-#define TEGRA_PWFM2_SIZE 4
-
-#define TEGRA_PWFM3_BASE 0x7000A030
-#define TEGRA_PWFM3_SIZE 4
-
-#define TEGRA_MIPI_BASE 0x7000B000
-#define TEGRA_MIPI_SIZE SZ_256
-
-#define TEGRA_I2C_BASE 0x7000C000
-#define TEGRA_I2C_SIZE SZ_256
-
-#define TEGRA_TWC_BASE 0x7000C100
-#define TEGRA_TWC_SIZE SZ_256
-
-#define TEGRA_SPI_BASE 0x7000C380
-#define TEGRA_SPI_SIZE 48
-
-#define TEGRA_I2C2_BASE 0x7000C400
-#define TEGRA_I2C2_SIZE SZ_256
-
-#define TEGRA_I2C3_BASE 0x7000C500
-#define TEGRA_I2C3_SIZE SZ_256
-
-#define TEGRA_OWR_BASE 0x7000C600
-#define TEGRA_OWR_SIZE 80
-
-#define TEGRA_DVC_BASE 0x7000D000
-#define TEGRA_DVC_SIZE SZ_512
-
-#define TEGRA_SPI1_BASE 0x7000D400
-#define TEGRA_SPI1_SIZE SZ_512
-
-#define TEGRA_SPI2_BASE 0x7000D600
-#define TEGRA_SPI2_SIZE SZ_512
-
-#define TEGRA_SPI3_BASE 0x7000D800
-#define TEGRA_SPI3_SIZE SZ_512
-
-#define TEGRA_SPI4_BASE 0x7000DA00
-#define TEGRA_SPI4_SIZE SZ_512
-
-#define TEGRA_RTC_BASE 0x7000E000
-#define TEGRA_RTC_SIZE SZ_256
-
-#define TEGRA_KBC_BASE 0x7000E200
-#define TEGRA_KBC_SIZE SZ_256
-
-#define TEGRA_PMC_BASE 0x7000E400
-#define TEGRA_PMC_SIZE SZ_256
-
-#define TEGRA_MC_BASE 0x7000F000
-#define TEGRA_MC_SIZE SZ_1K
-
-#define TEGRA_EMC_BASE 0x7000F400
-#define TEGRA_EMC_SIZE SZ_1K
-
-#define TEGRA_FUSE_BASE 0x7000F800
-#define TEGRA_FUSE_SIZE SZ_1K
-
-#define TEGRA_KFUSE_BASE 0x7000FC00
-#define TEGRA_KFUSE_SIZE SZ_1K
-
-#define TEGRA_CSITE_BASE 0x70040000
-#define TEGRA_CSITE_SIZE SZ_256K
-
-#define TEGRA_USB_BASE 0xC5000000
-#define TEGRA_USB_SIZE SZ_16K
-
-#define TEGRA_USB2_BASE 0xC5004000
-#define TEGRA_USB2_SIZE SZ_16K
-
-#define TEGRA_USB3_BASE 0xC5008000
-#define TEGRA_USB3_SIZE SZ_16K
-
-#define TEGRA_SDMMC1_BASE 0xC8000000
-#define TEGRA_SDMMC1_SIZE SZ_512
-
-#define TEGRA_SDMMC2_BASE 0xC8000200
-#define TEGRA_SDMMC2_SIZE SZ_512
-
-#define TEGRA_SDMMC3_BASE 0xC8000400
-#define TEGRA_SDMMC3_SIZE SZ_512
-
-#define TEGRA_SDMMC4_BASE 0xC8000600
-#define TEGRA_SDMMC4_SIZE SZ_512
-
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-silicon.h b/arch/arm/mach-tegra/include/mach/tegra20-silicon.h
new file mode 100644
index 0000000..d7140fb
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra20-silicon.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2012 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ * Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <sizes.h>
+
+#define TEGRA_EMEM_BASE 0x0
+#define TEGRA_EMEM_SIZE SZ_1G
+
+#define TEGRA_IRAM_BASE 0x40000000
+#define TEGRA_IRAM_SIZE SZ_256K
+
+#define TEGRA_ARM_PERIPHBASE 0x50040000
+#define TEGRA_ARM_PERIPHSIZE SZ_8K
+
+#define TEGRA_ARM_INT_DIST_BASE TEGRA_ARM_PERIPHBASE + 0x1000
+#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
+
+#define TEGRA_ARM_PL310_BASE TEGRA_ARM_PERIPHBASE + 0x3000
+#define TEGRA_ARM_PL310_SIZE SZ_4K
+
+#define TEGRA_HOST1X_BASE 0x50000000
+#define TEGRA_HOST1X_SIZE SZ_64M
+
+#define TEGRA_MPE_BASE TEGRA_HOST1X_BASE + 0x40000
+#define TEGRA_MPE_SIZE SZ_256K
+
+#define TEGRA_VI_BASE TEGRA_HOST1X_BASE + 0x80000
+#define TEGRA_VI_SIZE SZ_256K
+
+#define TEGRA_ISP_BASE TEGRA_HOST1X_BASE + 0x100000
+#define TEGRA_ISP_SIZE SZ_256K
+
+#define TEGRA_DISPLAY_BASE TEGRA_HOST1X_BASE + 0x200000
+#define TEGRA_DISPLAY_SIZE SZ_256K
+
+#define TEGRA_DISPLAY2_BASE TEGRA_HOST1X_BASE + 0x240000
+#define TEGRA_DISPLAY2_SIZE SZ_256K
+
+#define TEGRA_HDMI_BASE TEGRA_HOST1X_BASE + 0x280000
+#define TEGRA_HDMI_SIZE SZ_256K
+
+#define TEGRA_TVO_BASE TEGRA_HOST1X_BASE + 0x2C0000
+#define TGERA_TVO_SIZE SZ_256K
+
+#define TEGRA_DSI_BASE TEGRA_HOST1X_BASE + 0x300000
+#define TEGRA_DSI_SIZE SZ_256K
+
+#define TEGRA_GART_BASE 0x58000000
+#define TEGRA_GART_SIZE SZ_32M
+
+#define TEGRA_PPSB_BASE 0x60000000
+#define TEGRA_PPSB_SIZE SZ_256M
+
+#define TEGRA_RES_SEMA_BASE TEGRA_PPSB_BASE + 0x1000
+#define TEGRA_RES_SEMA_SIZE SZ_4K
+
+#define TEGRA_ARB_SEMA_BASE TEGRA_PPSB_BASE + 0x2000
+#define TEGRA_ARB_SEMA_SIZE SZ_4K
+
+#define TEGRA_PRIMARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4000
+#define TEGRA_PRIMARY_ICTLR_SIZE 64
+
+#define TEGRA_ARBGNT_ICTLR_BASE TEGRA_PPSB_BASE + 0x4040
+#define TEGRA_ARBGNT_ICTLR_SIZE 192
+
+#define TEGRA_SECONDARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4100
+#define TEGRA_SECONDARY_ICTLR_SIZE 64
+
+#define TEGRA_TERTIARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4200
+#define TEGRA_TERTIARY_ICTLR_SIZE 64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4300
+#define TEGRA_QUATERNARY_ICTLR_SIZE 64
+
+#define TEGRA_TMR1_BASE TEGRA_PPSB_BASE + 0x5000
+#define TEGRA_TMR1_SIZE 8
+
+#define TEGRA_TMR2_BASE TEGRA_PPSB_BASE + 0x5008
+#define TEGRA_TMR2_SIZE 8
+
+#define TEGRA_TMRUS_BASE TEGRA_PPSB_BASE + 0x5010
+#define TEGRA_TMRUS_SIZE 64
+
+#define TEGRA_TMR3_BASE TEGRA_PPSB_BASE + 0x5050
+#define TEGRA_TMR3_SIZE 8
+
+#define TEGRA_TMR4_BASE TEGRA_PPSB_BASE + 0x5058
+#define TEGRA_TMR4_SIZE 8
+
+#define TEGRA_CLK_RESET_BASE TEGRA_PPSB_BASE + 0x6000
+#define TEGRA_CLK_RESET_SIZE SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE TEGRA_PPSB_BASE + 0x7000
+#define TEGRA_FLOW_CTRL_SIZE 20
+
+#define TEGRA_AHB_DMA_BASE TEGRA_PPSB_BASE + 0x8000
+#define TEGRA_AHB_DMA_SIZE SZ_4K
+
+#define TEGRA_GPIO_BASE TEGRA_PPSB_BASE + 0xD000
+#define TEGRA_GPIO_SIZE SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE TEGRA_PPSB_BASE + 0xF000
+#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
+
+#define TEGRA_APB_BASE 0x70000000
+#define TEGRA_APB_SIZE SZ_256M
+
+#define TEGRA_UARTA_BASE TEGRA_APB_BASE + 0x6000
+#define TEGRA_UARTA_SIZE 64
+
+#define TEGRA_UARTB_BASE TEGRA_APB_BASE + 0x6040
+#define TEGRA_UARTB_SIZE 64
+
+#define TEGRA_UARTC_BASE TEGRA_APB_BASE + 0x6200
+#define TEGRA_UARTC_SIZE 256
+
+#define TEGRA_UARTD_BASE TEGRA_APB_BASE + 0x6300
+#define TEGRA_UARTD_SIZE 256
+
+#define TEGRA_UARTE_BASE TEGRA_APB_BASE + 0x6400
+#define TEGRA_UARTE_SIZE 256
+
+#define TEGRA_NAND_BASE TEGRA_APB_BASE + 0x8000
+#define TEGRA_NAND_SIZE 256
+
+#define TEGRA_SNOR_BASE TEGRA_APB_BASE + 0x9000
+#define TEGRA_SNOR_SIZE SZ_4K
+
+#define TEGRA_I2C_BASE TEGRA_APB_BASE + 0xC000
+#define TEGRA_I2C_SIZE 256
+
+#define TEGRA_TWC_BASE TEGRA_APB_BASE + 0xC100
+#define TEGRA_TWC_SIZE 256
+
+#define TEGRA_SPI_BASE TEGRA_APB_BASE + 0xC380
+#define TEGRA_SPI_SIZE 48
+
+#define TEGRA_I2C2_BASE TEGRA_APB_BASE + 0xC400
+#define TEGRA_I2C2_SIZE 256
+
+#define TEGRA_I2C3_BASE TEGRA_APB_BASE + 0xC500
+#define TEGRA_I2C3_SIZE 256
+
+#define TEGRA_OWR_BASE TEGRA_APB_BASE + 0xC600
+#define TEGRA_OWR_SIZE 80
+
+#define TEGRA_DVC_BASE TEGRA_APB_BASE + 0xD000
+#define TEGRA_DVC_SIZE 512
+
+#define TEGRA_SPI1_BASE TEGRA_APB_BASE + 0xD400
+#define TEGRA_SPI1_SIZE 512
+
+#define TEGRA_SPI2_BASE TEGRA_APB_BASE + 0xD600
+#define TEGRA_SPI2_SIZE 512
+
+#define TEGRA_SPI3_BASE TEGRA_APB_BASE + 0xD800
+#define TEGRA_SPI3_SIZE 512
+
+#define TEGRA_SPI4_BASE TEGRA_APB_BASE + 0xDA00
+#define TEGRA_SPI4_SIZE 512
+
+#define TEGRA_RTC_BASE TEGRA_APB_BASE + 0xE000
+#define TEGRA_RTC_SIZE 256
+
+#define TEGRA_KBC_BASE TEGRA_APB_BASE + 0xE200
+#define TEGRA_KBC_SIZE 256
+
+#define TEGRA_PMC_BASE TEGRA_APB_BASE + 0xE400
+#define TEGRA_PMC_SIZE 256
+
+#define TEGRA_MC_BASE TEGRA_APB_BASE + 0xF000
+#define TEGRA_MC_SIZE SZ_1K
+
+#define TEGRA_EMC_BASE TEGRA_APB_BASE + 0xF400
+#define TEGRA_EMC_SIZE SZ_1K
+
+#define TEGRA_FUSE_BASE TEGRA_APB_BASE + 0xF800
+#define TEGRA_FUSE_SIZE SZ_1K
+
+#define TEGRA_KFUSE_BASE TEGRA_APB_BASE + 0xFC00
+#define TEGRA_KFUSE_SIZE SZ_1K
+
+#define TEGRA_CSITE_BASE TEGRA_APB_BASE + 0x40000
+#define TEGRA_CSITE_SIZE SZ_256K
+
+#define TEGRA_AHB_BASE 0xC0000000
+#define TEGRA_AHB_SIZE SZ_256M
+
+#define TEGRA_USB_BASE TEGRA_AHB_BASE + 0x5000000
+#define TEGRA_USB_SIZE SZ_16K
+
+#define TEGRA_USB2_BASE TEGRA_AHB_BASE + 0x5004000
+#define TEGRA_USB2_SIZE SZ_16K
+
+#define TEGRA_USB3_BASE TEGRA_AHB_BASE + 0x5008000
+#define TEGRA_USB3_SIZE SZ_16K
+
+#define TEGRA_SDMMC1_BASE TEGRA_AHB_BASE + 0x8000000
+#define TEGRA_SDMMC1_SIZE 512
+
+#define TEGRA_SDMMC2_BASE TEGRA_AHB_BASE + 0x8000200
+#define TEGRA_SDMMC2_SIZE 512
+
+#define TEGRA_SDMMC3_BASE TEGRA_AHB_BASE + 0x8000400
+#define TEGRA_SDMMC3_SIZE 512
+
+#define TEGRA_SDMMC4_BASE TEGRA_AHB_BASE + 0x8000600
+#define TEGRA_SDMMC4_SIZE 512
+
+#endif
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 91f9b3b..73d7ca2 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -22,7 +22,7 @@
#include <common.h>
#include <asm/io.h>
-#include <mach/iomap.h>
+#include <mach/tegra20-silicon.h>
#define PRM_RSTCTRL TEGRA_PMC_BASE
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 1/7] tegra: move address map to tegra20-silicon.h
2013-03-01 9:22 ` [PATCH 1/7] tegra: move address map to tegra20-silicon.h Lucas Stach
@ 2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-02 23:25 ` Lucas Stach
0 siblings, 1 reply; 41+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-01 13:17 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 10:22 Fri 01 Mar , Lucas Stach wrote:
> The address map is specific to the Tegra20 SoC. Move it to a
> file with an appropriate name. While at it clarify and fix
> the definitions.
folloow the kernel
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/boards/toshiba-ac100/board.c | 2 +-
> arch/arm/boards/toshiba-ac100/serial.c | 2 +-
> arch/arm/mach-tegra/clock.c | 2 +-
> arch/arm/mach-tegra/include/mach/debug_ll.h | 2 +-
> arch/arm/mach-tegra/include/mach/iomap.h | 292 ---------------------
> arch/arm/mach-tegra/include/mach/tegra20-silicon.h | 229 ++++++++++++++++
> arch/arm/mach-tegra/reset.c | 2 +-
> 7 files changed, 234 insertions(+), 297 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
> create mode 100644 arch/arm/mach-tegra/include/mach/tegra20-silicon.h
>
> diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c
> index 0eb85c5..af397cc 100644
> --- a/arch/arm/boards/toshiba-ac100/board.c
> +++ b/arch/arm/boards/toshiba-ac100/board.c
> @@ -21,7 +21,7 @@
> #include <asm/armlinux.h>
> #include <sizes.h>
> #include <usb/ehci.h>
> -#include <mach/iomap.h>
> +#include <mach/tegra20-silicon.h>
>
> static int ac100_mem_init(void)
> {
> diff --git a/arch/arm/boards/toshiba-ac100/serial.c b/arch/arm/boards/toshiba-ac100/serial.c
> index 880270d..cdd47ab 100644
> --- a/arch/arm/boards/toshiba-ac100/serial.c
> +++ b/arch/arm/boards/toshiba-ac100/serial.c
> @@ -21,7 +21,7 @@
> #include <ns16550.h>
> #include <asm/io.h>
> #include <asm/common.h>
> -#include <mach/iomap.h>
> +#include <mach/tegra20-silicon.h>
>
> static struct NS16550_plat serial_plat = {
> .clock = 0x75 * 115200 * 16 /* MODE_X_DIV */,
> diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
> index 82065ee..8a7525d 100644
> --- a/arch/arm/mach-tegra/clock.c
> +++ b/arch/arm/mach-tegra/clock.c
> @@ -26,7 +26,7 @@
> #include <linux/clk.h>
> #include <init.h>
> #include <asm/io.h>
> -#include <mach/iomap.h>
> +#include <mach/tegra20-silicon.h>
>
> static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
>
> diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
> index 290ad58..4a54e44 100644
> --- a/arch/arm/mach-tegra/include/mach/debug_ll.h
> +++ b/arch/arm/mach-tegra/include/mach/debug_ll.h
> @@ -22,7 +22,7 @@
> #define __INCLUDE_ARCH_DEBUG_LL_H__
>
> #include <asm/io.h>
> -#include <mach/iomap.h>
> +#include <mach/tegra20-silicon.h>
>
> #define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
> #define DEBUG_LL_UART_RSHFT 2
> diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
> deleted file mode 100644
> index ba478e7..0000000
> --- a/arch/arm/mach-tegra/include/mach/iomap.h
> +++ /dev/null
> @@ -1,292 +0,0 @@
> -/*
> - * arch/arm/mach-tegra/include/mach/iomap.h
> - *
> - * Copyright (C) 2010 Google, Inc.
> - *
> - * Author:
> - * Colin Cross <ccross@google.com>
> - * Erik Gilling <konkers@google.com>
> - *
> - * This software is licensed under the terms of the GNU General Public
> - * License version 2, as published by the Free Software Foundation, and
> - * may be copied, distributed, and modified under those terms.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -#ifndef __MACH_TEGRA_IOMAP_H
> -#define __MACH_TEGRA_IOMAP_H
> -
> -#include <sizes.h>
> -
> -#define TEGRA_IRAM_BASE 0x40000000
> -#define TEGRA_IRAM_SIZE SZ_256K
> -
> -#define TEGRA_HOST1X_BASE 0x50000000
> -#define TEGRA_HOST1X_SIZE 0x24000
> -
> -#define TEGRA_ARM_PERIF_BASE 0x50040000
> -#define TEGRA_ARM_PERIF_SIZE SZ_8K
> -
> -#define TEGRA_ARM_PL310_BASE 0x50043000
> -#define TEGRA_ARM_PL310_SIZE SZ_4K
> -
> -#define TEGRA_ARM_INT_DIST_BASE 0x50041000
> -#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
> -
> -#define TEGRA_MPE_BASE 0x54040000
> -#define TEGRA_MPE_SIZE SZ_256K
> -
> -#define TEGRA_VI_BASE 0x54080000
> -#define TEGRA_VI_SIZE SZ_256K
> -
> -#define TEGRA_ISP_BASE 0x54100000
> -#define TEGRA_ISP_SIZE SZ_256K
> -
> -#define TEGRA_DISPLAY_BASE 0x54200000
> -#define TEGRA_DISPLAY_SIZE SZ_256K
> -
> -#define TEGRA_DISPLAY2_BASE 0x54240000
> -#define TEGRA_DISPLAY2_SIZE SZ_256K
> -
> -#define TEGRA_HDMI_BASE 0x54280000
> -#define TEGRA_HDMI_SIZE SZ_256K
> -
> -#define TEGRA_GART_BASE 0x58000000
> -#define TEGRA_GART_SIZE SZ_32M
> -
> -#define TEGRA_RES_SEMA_BASE 0x60001000
> -#define TEGRA_RES_SEMA_SIZE SZ_4K
> -
> -#define TEGRA_HDMI_BASE 0x54280000
> -#define TEGRA_HDMI_SIZE SZ_256K
> -
> -#define TEGRA_GART_BASE 0x58000000
> -#define TEGRA_GART_SIZE SZ_32M
> -
> -#define TEGRA_RES_SEMA_BASE 0x60001000
> -#define TEGRA_RES_SEMA_SIZE SZ_4K
> -
> -#define TEGRA_ARB_SEMA_BASE 0x60002000
> -#define TEGRA_ARB_SEMA_SIZE SZ_4K
> -
> -#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
> -#define TEGRA_PRIMARY_ICTLR_SIZE 64
> -
> -#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
> -#define TEGRA_ARBGNT_ICTLR_SIZE 192
> -
> -#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
> -#define TEGRA_SECONDARY_ICTLR_SIZE 64
> -
> -#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
> -#define TEGRA_TERTIARY_ICTLR_SIZE 64
> -
> -#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
> -#define TEGRA_QUATERNARY_ICTLR_SIZE 64
> -
> -#define TEGRA_TMR1_BASE 0x60005000
> -#define TEGRA_TMR1_SIZE 8
> -
> -#define TEGRA_TMR2_BASE 0x60005008
> -#define TEGRA_TMR2_SIZE 8
> -
> -#define TEGRA_TMRUS_BASE 0x60005010
> -#define TEGRA_TMRUS_SIZE 64
> -
> -#define TEGRA_TMR3_BASE 0x60005050
> -#define TEGRA_TMR3_SIZE 8
> -
> -#define TEGRA_TMR4_BASE 0x60005058
> -#define TEGRA_TMR4_SIZE 8
> -
> -#define TEGRA_CLK_RESET_BASE 0x60006000
> -#define TEGRA_CLK_RESET_SIZE SZ_4K
> -
> -#define TEGRA_FLOW_CTRL_BASE 0x60007000
> -#define TEGRA_FLOW_CTRL_SIZE 20
> -
> -#define TEGRA_AHB_DMA_BASE 0x60008000
> -#define TEGRA_AHB_DMA_SIZE SZ_4K
> -
> -#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
> -#define TEGRA_AHB_DMA_CH0_SIZE 32
> -
> -#define TEGRA_APB_DMA_BASE 0x6000A000
> -#define TEGRA_APB_DMA_SIZE SZ_4K
> -
> -#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
> -#define TEGRA_APB_DMA_CH0_SIZE 32
> -
> -#define TEGRA_AHB_GIZMO_BASE 0x6000C004
> -#define TEGRA_AHB_GIZMO_SIZE 0x10C
> -
> -#define TEGRA_STATMON_BASE 0x6000C400
> -#define TEGRA_STATMON_SIZE SZ_1K
> -
> -#define TEGRA_GPIO_BASE 0x6000D000
> -#define TEGRA_GPIO_SIZE SZ_4K
> -
> -#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
> -#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
> -
> -#define TEGRA_VDE_BASE 0x6001A000
> -#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256)
> -
> -#define TEGRA_APB_MISC_BASE 0x70000000
> -#define TEGRA_APB_MISC_SIZE SZ_4K
> -
> -#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
> -#define TEGRA_APB_MISC_DAS_SIZE SZ_128
> -
> -#define TEGRA_AC97_BASE 0x70002000
> -#define TEGRA_AC97_SIZE SZ_512
> -
> -#define TEGRA_SPDIF_BASE 0x70002400
> -#define TEGRA_SPDIF_SIZE SZ_512
> -
> -#define TEGRA_I2S1_BASE 0x70002800
> -#define TEGRA_I2S1_SIZE SZ_256
> -
> -#define TEGRA_I2S2_BASE 0x70002A00
> -#define TEGRA_I2S2_SIZE SZ_256
> -
> -#define TEGRA_UARTA_BASE 0x70006000
> -#define TEGRA_UARTA_SIZE 64
> -
> -#define TEGRA_UARTB_BASE 0x70006040
> -#define TEGRA_UARTB_SIZE 64
> -
> -#define TEGRA_UARTC_BASE 0x70006200
> -#define TEGRA_UARTC_SIZE SZ_256
> -
> -#define TEGRA_UARTD_BASE 0x70006300
> -#define TEGRA_UARTD_SIZE SZ_256
> -
> -#define TEGRA_UARTE_BASE 0x70006400
> -#define TEGRA_UARTE_SIZE SZ_256
> -
> -#define TEGRA_NAND_BASE 0x70008000
> -#define TEGRA_NAND_SIZE SZ_256
> -
> -#define TEGRA_HSMMC_BASE 0x70008500
> -#define TEGRA_HSMMC_SIZE SZ_256
> -
> -#define TEGRA_SNOR_BASE 0x70009000
> -#define TEGRA_SNOR_SIZE SZ_4K
> -
> -#define TEGRA_PWFM_BASE 0x7000A000
> -#define TEGRA_PWFM_SIZE SZ_256
> -
> -#define TEGRA_PWFM0_BASE 0x7000A000
> -#define TEGRA_PWFM0_SIZE 4
> -
> -#define TEGRA_PWFM1_BASE 0x7000A010
> -#define TEGRA_PWFM1_SIZE 4
> -
> -#define TEGRA_PWFM2_BASE 0x7000A020
> -#define TEGRA_PWFM2_SIZE 4
> -
> -#define TEGRA_PWFM3_BASE 0x7000A030
> -#define TEGRA_PWFM3_SIZE 4
> -
> -#define TEGRA_MIPI_BASE 0x7000B000
> -#define TEGRA_MIPI_SIZE SZ_256
> -
> -#define TEGRA_I2C_BASE 0x7000C000
> -#define TEGRA_I2C_SIZE SZ_256
> -
> -#define TEGRA_TWC_BASE 0x7000C100
> -#define TEGRA_TWC_SIZE SZ_256
> -
> -#define TEGRA_SPI_BASE 0x7000C380
> -#define TEGRA_SPI_SIZE 48
> -
> -#define TEGRA_I2C2_BASE 0x7000C400
> -#define TEGRA_I2C2_SIZE SZ_256
> -
> -#define TEGRA_I2C3_BASE 0x7000C500
> -#define TEGRA_I2C3_SIZE SZ_256
> -
> -#define TEGRA_OWR_BASE 0x7000C600
> -#define TEGRA_OWR_SIZE 80
> -
> -#define TEGRA_DVC_BASE 0x7000D000
> -#define TEGRA_DVC_SIZE SZ_512
> -
> -#define TEGRA_SPI1_BASE 0x7000D400
> -#define TEGRA_SPI1_SIZE SZ_512
> -
> -#define TEGRA_SPI2_BASE 0x7000D600
> -#define TEGRA_SPI2_SIZE SZ_512
> -
> -#define TEGRA_SPI3_BASE 0x7000D800
> -#define TEGRA_SPI3_SIZE SZ_512
> -
> -#define TEGRA_SPI4_BASE 0x7000DA00
> -#define TEGRA_SPI4_SIZE SZ_512
> -
> -#define TEGRA_RTC_BASE 0x7000E000
> -#define TEGRA_RTC_SIZE SZ_256
> -
> -#define TEGRA_KBC_BASE 0x7000E200
> -#define TEGRA_KBC_SIZE SZ_256
> -
> -#define TEGRA_PMC_BASE 0x7000E400
> -#define TEGRA_PMC_SIZE SZ_256
> -
> -#define TEGRA_MC_BASE 0x7000F000
> -#define TEGRA_MC_SIZE SZ_1K
> -
> -#define TEGRA_EMC_BASE 0x7000F400
> -#define TEGRA_EMC_SIZE SZ_1K
> -
> -#define TEGRA_FUSE_BASE 0x7000F800
> -#define TEGRA_FUSE_SIZE SZ_1K
> -
> -#define TEGRA_KFUSE_BASE 0x7000FC00
> -#define TEGRA_KFUSE_SIZE SZ_1K
> -
> -#define TEGRA_CSITE_BASE 0x70040000
> -#define TEGRA_CSITE_SIZE SZ_256K
> -
> -#define TEGRA_USB_BASE 0xC5000000
> -#define TEGRA_USB_SIZE SZ_16K
> -
> -#define TEGRA_USB2_BASE 0xC5004000
> -#define TEGRA_USB2_SIZE SZ_16K
> -
> -#define TEGRA_USB3_BASE 0xC5008000
> -#define TEGRA_USB3_SIZE SZ_16K
> -
> -#define TEGRA_SDMMC1_BASE 0xC8000000
> -#define TEGRA_SDMMC1_SIZE SZ_512
> -
> -#define TEGRA_SDMMC2_BASE 0xC8000200
> -#define TEGRA_SDMMC2_SIZE SZ_512
> -
> -#define TEGRA_SDMMC3_BASE 0xC8000400
> -#define TEGRA_SDMMC3_SIZE SZ_512
> -
> -#define TEGRA_SDMMC4_BASE 0xC8000600
> -#define TEGRA_SDMMC4_SIZE SZ_512
> -
> -#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
> -# define TEGRA_DEBUG_UART_BASE 0
> -#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
> -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
> -#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
> -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
> -#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
> -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
> -#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
> -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
> -#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
> -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
> -#endif
> -
> -#endif
> diff --git a/arch/arm/mach-tegra/include/mach/tegra20-silicon.h b/arch/arm/mach-tegra/include/mach/tegra20-silicon.h
> new file mode 100644
> index 0000000..d7140fb
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/tegra20-silicon.h
> @@ -0,0 +1,229 @@
> +/*
> + * Copyright (C) 2010 Google, Inc.
> + * Copyright (C) 2012 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * Author:
> + * Colin Cross <ccross@google.com>
> + * Erik Gilling <konkers@google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_IOMAP_H
> +#define __MACH_TEGRA_IOMAP_H
> +
> +#include <sizes.h>
> +
> +#define TEGRA_EMEM_BASE 0x0
> +#define TEGRA_EMEM_SIZE SZ_1G
> +
> +#define TEGRA_IRAM_BASE 0x40000000
> +#define TEGRA_IRAM_SIZE SZ_256K
> +
> +#define TEGRA_ARM_PERIPHBASE 0x50040000
> +#define TEGRA_ARM_PERIPHSIZE SZ_8K
> +
> +#define TEGRA_ARM_INT_DIST_BASE TEGRA_ARM_PERIPHBASE + 0x1000
> +#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
> +
> +#define TEGRA_ARM_PL310_BASE TEGRA_ARM_PERIPHBASE + 0x3000
> +#define TEGRA_ARM_PL310_SIZE SZ_4K
> +
> +#define TEGRA_HOST1X_BASE 0x50000000
> +#define TEGRA_HOST1X_SIZE SZ_64M
> +
> +#define TEGRA_MPE_BASE TEGRA_HOST1X_BASE + 0x40000
> +#define TEGRA_MPE_SIZE SZ_256K
> +
> +#define TEGRA_VI_BASE TEGRA_HOST1X_BASE + 0x80000
> +#define TEGRA_VI_SIZE SZ_256K
> +
> +#define TEGRA_ISP_BASE TEGRA_HOST1X_BASE + 0x100000
> +#define TEGRA_ISP_SIZE SZ_256K
> +
> +#define TEGRA_DISPLAY_BASE TEGRA_HOST1X_BASE + 0x200000
> +#define TEGRA_DISPLAY_SIZE SZ_256K
> +
> +#define TEGRA_DISPLAY2_BASE TEGRA_HOST1X_BASE + 0x240000
> +#define TEGRA_DISPLAY2_SIZE SZ_256K
> +
> +#define TEGRA_HDMI_BASE TEGRA_HOST1X_BASE + 0x280000
> +#define TEGRA_HDMI_SIZE SZ_256K
> +
> +#define TEGRA_TVO_BASE TEGRA_HOST1X_BASE + 0x2C0000
> +#define TGERA_TVO_SIZE SZ_256K
> +
> +#define TEGRA_DSI_BASE TEGRA_HOST1X_BASE + 0x300000
> +#define TEGRA_DSI_SIZE SZ_256K
> +
> +#define TEGRA_GART_BASE 0x58000000
> +#define TEGRA_GART_SIZE SZ_32M
> +
> +#define TEGRA_PPSB_BASE 0x60000000
> +#define TEGRA_PPSB_SIZE SZ_256M
> +
> +#define TEGRA_RES_SEMA_BASE TEGRA_PPSB_BASE + 0x1000
> +#define TEGRA_RES_SEMA_SIZE SZ_4K
> +
> +#define TEGRA_ARB_SEMA_BASE TEGRA_PPSB_BASE + 0x2000
> +#define TEGRA_ARB_SEMA_SIZE SZ_4K
> +
> +#define TEGRA_PRIMARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4000
> +#define TEGRA_PRIMARY_ICTLR_SIZE 64
> +
> +#define TEGRA_ARBGNT_ICTLR_BASE TEGRA_PPSB_BASE + 0x4040
> +#define TEGRA_ARBGNT_ICTLR_SIZE 192
> +
> +#define TEGRA_SECONDARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4100
> +#define TEGRA_SECONDARY_ICTLR_SIZE 64
> +
> +#define TEGRA_TERTIARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4200
> +#define TEGRA_TERTIARY_ICTLR_SIZE 64
> +
> +#define TEGRA_QUATERNARY_ICTLR_BASE TEGRA_PPSB_BASE + 0x4300
> +#define TEGRA_QUATERNARY_ICTLR_SIZE 64
> +
> +#define TEGRA_TMR1_BASE TEGRA_PPSB_BASE + 0x5000
> +#define TEGRA_TMR1_SIZE 8
> +
> +#define TEGRA_TMR2_BASE TEGRA_PPSB_BASE + 0x5008
> +#define TEGRA_TMR2_SIZE 8
> +
> +#define TEGRA_TMRUS_BASE TEGRA_PPSB_BASE + 0x5010
> +#define TEGRA_TMRUS_SIZE 64
> +
> +#define TEGRA_TMR3_BASE TEGRA_PPSB_BASE + 0x5050
> +#define TEGRA_TMR3_SIZE 8
> +
> +#define TEGRA_TMR4_BASE TEGRA_PPSB_BASE + 0x5058
> +#define TEGRA_TMR4_SIZE 8
> +
> +#define TEGRA_CLK_RESET_BASE TEGRA_PPSB_BASE + 0x6000
> +#define TEGRA_CLK_RESET_SIZE SZ_4K
> +
> +#define TEGRA_FLOW_CTRL_BASE TEGRA_PPSB_BASE + 0x7000
> +#define TEGRA_FLOW_CTRL_SIZE 20
> +
> +#define TEGRA_AHB_DMA_BASE TEGRA_PPSB_BASE + 0x8000
> +#define TEGRA_AHB_DMA_SIZE SZ_4K
> +
> +#define TEGRA_GPIO_BASE TEGRA_PPSB_BASE + 0xD000
> +#define TEGRA_GPIO_SIZE SZ_4K
> +
> +#define TEGRA_EXCEPTION_VECTORS_BASE TEGRA_PPSB_BASE + 0xF000
> +#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
> +
> +#define TEGRA_APB_BASE 0x70000000
> +#define TEGRA_APB_SIZE SZ_256M
> +
> +#define TEGRA_UARTA_BASE TEGRA_APB_BASE + 0x6000
> +#define TEGRA_UARTA_SIZE 64
> +
> +#define TEGRA_UARTB_BASE TEGRA_APB_BASE + 0x6040
> +#define TEGRA_UARTB_SIZE 64
> +
> +#define TEGRA_UARTC_BASE TEGRA_APB_BASE + 0x6200
> +#define TEGRA_UARTC_SIZE 256
> +
> +#define TEGRA_UARTD_BASE TEGRA_APB_BASE + 0x6300
> +#define TEGRA_UARTD_SIZE 256
> +
> +#define TEGRA_UARTE_BASE TEGRA_APB_BASE + 0x6400
> +#define TEGRA_UARTE_SIZE 256
> +
> +#define TEGRA_NAND_BASE TEGRA_APB_BASE + 0x8000
> +#define TEGRA_NAND_SIZE 256
> +
> +#define TEGRA_SNOR_BASE TEGRA_APB_BASE + 0x9000
> +#define TEGRA_SNOR_SIZE SZ_4K
> +
> +#define TEGRA_I2C_BASE TEGRA_APB_BASE + 0xC000
> +#define TEGRA_I2C_SIZE 256
> +
> +#define TEGRA_TWC_BASE TEGRA_APB_BASE + 0xC100
> +#define TEGRA_TWC_SIZE 256
> +
> +#define TEGRA_SPI_BASE TEGRA_APB_BASE + 0xC380
> +#define TEGRA_SPI_SIZE 48
> +
> +#define TEGRA_I2C2_BASE TEGRA_APB_BASE + 0xC400
> +#define TEGRA_I2C2_SIZE 256
> +
> +#define TEGRA_I2C3_BASE TEGRA_APB_BASE + 0xC500
> +#define TEGRA_I2C3_SIZE 256
> +
> +#define TEGRA_OWR_BASE TEGRA_APB_BASE + 0xC600
> +#define TEGRA_OWR_SIZE 80
> +
> +#define TEGRA_DVC_BASE TEGRA_APB_BASE + 0xD000
> +#define TEGRA_DVC_SIZE 512
> +
> +#define TEGRA_SPI1_BASE TEGRA_APB_BASE + 0xD400
> +#define TEGRA_SPI1_SIZE 512
> +
> +#define TEGRA_SPI2_BASE TEGRA_APB_BASE + 0xD600
> +#define TEGRA_SPI2_SIZE 512
> +
> +#define TEGRA_SPI3_BASE TEGRA_APB_BASE + 0xD800
> +#define TEGRA_SPI3_SIZE 512
> +
> +#define TEGRA_SPI4_BASE TEGRA_APB_BASE + 0xDA00
> +#define TEGRA_SPI4_SIZE 512
> +
> +#define TEGRA_RTC_BASE TEGRA_APB_BASE + 0xE000
> +#define TEGRA_RTC_SIZE 256
> +
> +#define TEGRA_KBC_BASE TEGRA_APB_BASE + 0xE200
> +#define TEGRA_KBC_SIZE 256
> +
> +#define TEGRA_PMC_BASE TEGRA_APB_BASE + 0xE400
> +#define TEGRA_PMC_SIZE 256
> +
> +#define TEGRA_MC_BASE TEGRA_APB_BASE + 0xF000
> +#define TEGRA_MC_SIZE SZ_1K
> +
> +#define TEGRA_EMC_BASE TEGRA_APB_BASE + 0xF400
> +#define TEGRA_EMC_SIZE SZ_1K
> +
> +#define TEGRA_FUSE_BASE TEGRA_APB_BASE + 0xF800
> +#define TEGRA_FUSE_SIZE SZ_1K
> +
> +#define TEGRA_KFUSE_BASE TEGRA_APB_BASE + 0xFC00
> +#define TEGRA_KFUSE_SIZE SZ_1K
> +
> +#define TEGRA_CSITE_BASE TEGRA_APB_BASE + 0x40000
> +#define TEGRA_CSITE_SIZE SZ_256K
> +
> +#define TEGRA_AHB_BASE 0xC0000000
> +#define TEGRA_AHB_SIZE SZ_256M
> +
> +#define TEGRA_USB_BASE TEGRA_AHB_BASE + 0x5000000
> +#define TEGRA_USB_SIZE SZ_16K
> +
> +#define TEGRA_USB2_BASE TEGRA_AHB_BASE + 0x5004000
> +#define TEGRA_USB2_SIZE SZ_16K
> +
> +#define TEGRA_USB3_BASE TEGRA_AHB_BASE + 0x5008000
> +#define TEGRA_USB3_SIZE SZ_16K
> +
> +#define TEGRA_SDMMC1_BASE TEGRA_AHB_BASE + 0x8000000
> +#define TEGRA_SDMMC1_SIZE 512
> +
> +#define TEGRA_SDMMC2_BASE TEGRA_AHB_BASE + 0x8000200
> +#define TEGRA_SDMMC2_SIZE 512
> +
> +#define TEGRA_SDMMC3_BASE TEGRA_AHB_BASE + 0x8000400
> +#define TEGRA_SDMMC3_SIZE 512
> +
> +#define TEGRA_SDMMC4_BASE TEGRA_AHB_BASE + 0x8000600
> +#define TEGRA_SDMMC4_SIZE 512
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
> index 91f9b3b..73d7ca2 100644
> --- a/arch/arm/mach-tegra/reset.c
> +++ b/arch/arm/mach-tegra/reset.c
> @@ -22,7 +22,7 @@
>
> #include <common.h>
> #include <asm/io.h>
> -#include <mach/iomap.h>
> +#include <mach/tegra20-silicon.h>
>
> #define PRM_RSTCTRL TEGRA_PMC_BASE
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 1/7] tegra: move address map to tegra20-silicon.h
2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-03-02 23:25 ` Lucas Stach
2013-03-04 19:26 ` Antony Pavlov
0 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-02 23:25 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
Am Freitag, den 01.03.2013, 14:17 +0100 schrieb Jean-Christophe
PLAGNIOL-VILLARD:
> On 10:22 Fri 01 Mar , Lucas Stach wrote:
> > The address map is specific to the Tegra20 SoC. Move it to a
> > file with an appropriate name. While at it clarify and fix
> > the definitions.
>
> folloow the kernel
The Tegra kernel is fully device tree enabled and doesn't need any of
those defines, as the hardware mapping is encoded in the DT. While I'm
certainly aiming for the same thing in barebox, it's just not the right
thing to do at this state of development.
> >
> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> > ---
> > [...]
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 1/7] tegra: move address map to tegra20-silicon.h
2013-03-02 23:25 ` Lucas Stach
@ 2013-03-04 19:26 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-04 19:26 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 3 March 2013 03:25, Lucas Stach <dev@lynxeye.de> wrote:
> Am Freitag, den 01.03.2013, 14:17 +0100 schrieb Jean-Christophe
> PLAGNIOL-VILLARD:
>> On 10:22 Fri 01 Mar , Lucas Stach wrote:
>> > The address map is specific to the Tegra20 SoC. Move it to a
>> > file with an appropriate name. While at it clarify and fix
>> > the definitions.
>>
>> folloow the kernel
>
> The Tegra kernel is fully device tree enabled and doesn't need any of
> those defines, as the hardware mapping is encoded in the DT. While I'm
> certainly aiming for the same thing in barebox, it's just not the right
> thing to do at this state of development.
Is there any benefit in the renaming of the iomap.h file to tegra20-silicon.h?
I think no. The name iomap.h is used in the linux kernel so it is
natural that just the same file will have the same name it barebox.
It is more comfortable for kernel developer see the kernel header
files in bootloader with the same kernel name.
Anyway the number of kernel Tegra developers is much more than number
of barebox Tegra developers :)))
>> >
>> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> > ---
>> > [...]
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 2/7] tegra: remove debug_ll
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
2013-03-01 9:22 ` [PATCH 1/7] tegra: move address map to tegra20-silicon.h Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 17:19 ` Sascha Hauer
2013-03-01 9:22 ` [PATCH 3/7] tegra: switch to ARMv7 cpu type Lucas Stach
` (5 subsequent siblings)
7 siblings, 2 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Without some kind of initialisation those LL debug functions are mostly
useless. We might want them when booting from the AVP, but for this to
work they need some serious rework, so move them out of the way for now.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/Kconfig | 1 -
arch/arm/mach-tegra/include/mach/debug_ll.h | 42 -----------------------------
2 files changed, 43 deletions(-)
delete mode 100644 arch/arm/mach-tegra/include/mach/debug_ll.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..0ae2daa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -108,7 +108,6 @@ config ARCH_VERSATILE
config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
select CPU_ARM926T
- select HAS_DEBUG_LL
endchoice
diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
deleted file mode 100644
index 4a54e44..0000000
--- a/arch/arm/mach-tegra/include/mach/debug_ll.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/** @file
- * This File contains declaration for early output support
- */
-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
-#define __INCLUDE_ARCH_DEBUG_LL_H__
-
-#include <asm/io.h>
-#include <mach/tegra20-silicon.h>
-
-#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
-#define DEBUG_LL_UART_RSHFT 2
-
-#define rbr (0 << DEBUG_LL_UART_RSHFT)
-#define lsr (5 << DEBUG_LL_UART_RSHFT)
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-
-static inline void PUTC_LL(char ch)
-{
- while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
- ;
-
- __raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
-}
-
-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 2/7] tegra: remove debug_ll
2013-03-01 9:22 ` [PATCH 2/7] tegra: remove debug_ll Lucas Stach
@ 2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 17:19 ` Sascha Hauer
1 sibling, 0 replies; 41+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-01 13:17 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 10:22 Fri 01 Mar , Lucas Stach wrote:
> Without some kind of initialisation those LL debug functions are mostly
> useless. We might want them when booting from the AVP, but for this to
> work they need some serious rework, so move them out of the way for now.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
NACK
this is usefull for second stage
> ---
> arch/arm/Kconfig | 1 -
> arch/arm/mach-tegra/include/mach/debug_ll.h | 42 -----------------------------
> 2 files changed, 43 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/include/mach/debug_ll.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 28332ec..0ae2daa 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -108,7 +108,6 @@ config ARCH_VERSATILE
> config ARCH_TEGRA
> bool "Nvidia Tegra-based boards"
> select CPU_ARM926T
> - select HAS_DEBUG_LL
>
> endchoice
>
> diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
> deleted file mode 100644
> index 4a54e44..0000000
> --- a/arch/arm/mach-tegra/include/mach/debug_ll.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/*
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -/** @file
> - * This File contains declaration for early output support
> - */
> -#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
> -#define __INCLUDE_ARCH_DEBUG_LL_H__
> -
> -#include <asm/io.h>
> -#include <mach/tegra20-silicon.h>
> -
> -#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
> -#define DEBUG_LL_UART_RSHFT 2
> -
> -#define rbr (0 << DEBUG_LL_UART_RSHFT)
> -#define lsr (5 << DEBUG_LL_UART_RSHFT)
> -#define LSR_THRE 0x20 /* Xmit holding register empty */
> -
> -static inline void PUTC_LL(char ch)
> -{
> - while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
> - ;
> -
> - __raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
> -}
> -
> -#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 2/7] tegra: remove debug_ll
2013-03-01 9:22 ` [PATCH 2/7] tegra: remove debug_ll Lucas Stach
2013-03-01 13:17 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-03-01 17:19 ` Sascha Hauer
1 sibling, 0 replies; 41+ messages in thread
From: Sascha Hauer @ 2013-03-01 17:19 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Fri, Mar 01, 2013 at 10:22:48AM +0100, Lucas Stach wrote:
> Without some kind of initialisation those LL debug functions are mostly
> useless. We might want them when booting from the AVP, but for this to
> work they need some serious rework, so move them out of the way for now.
All debug_ll functions also from other architectures assume the uarts to
be initialized already, so as Jean-Christophe mentioned, they are for
second stage or JTAG where the debugger startup script initialized the
uarts
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 3/7] tegra: switch to ARMv7 cpu type
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
2013-03-01 9:22 ` [PATCH 1/7] tegra: move address map to tegra20-silicon.h Lucas Stach
2013-03-01 9:22 ` [PATCH 2/7] tegra: remove debug_ll Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 9:22 ` [PATCH 4/7] tegra: add blank tegra20 platform init Lucas Stach
` (4 subsequent siblings)
7 siblings, 0 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Main barebox is running on the A9 cluster. Use the correct ISA.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ae2daa..1c41e44 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -107,7 +107,7 @@ config ARCH_VERSATILE
config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
- select CPU_ARM926T
+ select CPU_V7
endchoice
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* [PATCH 4/7] tegra: add blank tegra20 platform init
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
` (2 preceding siblings ...)
2013-03-01 9:22 ` [PATCH 3/7] tegra: switch to ARMv7 cpu type Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 13:16 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 9:22 ` [PATCH 5/7] tegra: add driver for the clock and reset module Lucas Stach
` (3 subsequent siblings)
7 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Devices will get initialised here, as soon as the drivers are added.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/tegra20.c | 26 ++++++++++++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/mach-tegra/tegra20.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 11915e5..7777d0a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,2 +1,3 @@
obj-y += clock.o
obj-y += reset.o
+obj-y += tegra20.o
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
new file mode 100644
index 0000000..bf99b16
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/tegra20-silicon.h>
+
+static int tegra20_init(void)
+{
+ return 0;
+}
+
+postcore_initcall(tegra20_init);
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 4/7] tegra: add blank tegra20 platform init
2013-03-01 9:22 ` [PATCH 4/7] tegra: add blank tegra20 platform init Lucas Stach
@ 2013-03-01 13:16 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 41+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-01 13:16 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 10:22 Fri 01 Mar , Lucas Stach wrote:
> Devices will get initialised here, as soon as the drivers are added.
NACK do it at the first time
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/mach-tegra/Makefile | 1 +
> arch/arm/mach-tegra/tegra20.c | 26 ++++++++++++++++++++++++++
> 2 files changed, 27 insertions(+)
> create mode 100644 arch/arm/mach-tegra/tegra20.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 11915e5..7777d0a 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,2 +1,3 @@
> obj-y += clock.o
> obj-y += reset.o
> +obj-y += tegra20.o
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> new file mode 100644
> index 0000000..bf99b16
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -0,0 +1,26 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <mach/tegra20-silicon.h>
> +
> +static int tegra20_init(void)
> +{
> + return 0;
> +}
> +
> +postcore_initcall(tegra20_init);
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 5/7] tegra: add driver for the clock and reset module
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
` (3 preceding siblings ...)
2013-03-01 9:22 ` [PATCH 4/7] tegra: add blank tegra20 platform init Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 17:26 ` Sascha Hauer
2013-03-01 9:22 ` [PATCH 6/7] tegra: add proper timer driver Lucas Stach
` (2 subsequent siblings)
7 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Only a basic set of clocks is supported as of now.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/Kconfig | 2 +
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/include/mach/clkdev.h | 7 ++
arch/arm/mach-tegra/tegra20-car.c | 117 ++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 4 +
5 files changed, 131 insertions(+)
create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
create mode 100644 arch/arm/mach-tegra/tegra20-car.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c41e44..a3828e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -108,6 +108,8 @@ config ARCH_VERSATILE
config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
select CPU_V7
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
endchoice
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 7777d0a..3391528 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,4 @@
obj-y += clock.o
obj-y += reset.o
obj-y += tegra20.o
+obj-y += tegra20-car.o
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
new file mode 100644
index 0000000..95b3051
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-car.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 clock and reset (CAR) controller
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+/* Register definitions */
+#define OSC_CTRL 0x50
+#define OSC_CTRL_OSC_FREQ_MASK (3 << 30)
+#define OSC_CTRL_PLL_REF_DIV_MASK (3 << 28)
+
+static void __iomem *car_base;
+
+enum tegra20_clks {
+ cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
+ ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
+ gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
+ kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
+ dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
+ usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
+ pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
+ iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
+ uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
+ osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
+ pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
+ pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
+ pll_x, audio, pll_ref, twd, clk_max,
+};
+
+static struct clk *clks[clk_max];
+
+static unsigned long get_osc_frequency(void)
+{
+ u32 osc_ctrl = readl(car_base + OSC_CTRL);
+
+ switch (osc_ctrl & OSC_CTRL_OSC_FREQ_MASK) {
+ case 0:
+ return 13000000;
+ case 1:
+ return 19200000;
+ case 2:
+ return 12000000;
+ case 3:
+ return 26000000;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_pll_ref_div(void)
+{
+ u32 osc_ctrl = readl(car_base + OSC_CTRL);
+
+ return 1U << (osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK);
+}
+
+static int tegra20_car_probe(struct device_d *dev)
+{
+ car_base = dev_request_mem_region(dev, 0);
+ if (!car_base)
+ return -EBUSY;
+
+ /* primary clocks */
+ clks[clk_m] = clk_fixed("clk_m", get_osc_frequency());
+ clks[clk_32k] = clk_fixed("clk_32k", 32768);
+
+ clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
+ get_pll_ref_div());
+
+ /* derived clocks */
+ /* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
+ clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_car_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-car",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_car_driver = {
+ .probe = tegra20_car_probe,
+ .name = "tegra20-car",
+ .of_compatible = DRV_OF_COMPAT(tegra20_car_dt_ids),
+};
+
+static int tegra20_car_init(void)
+{
+ return platform_driver_register(&tegra20_car_driver);
+}
+postcore_initcall(tegra20_car_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index bf99b16..08c6758 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -20,6 +20,10 @@
static int tegra20_init(void)
{
+ add_generic_device("tegra20-car", DEVICE_ID_SINGLE, NULL,
+ TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
+ IORESOURCE_MEM, NULL);
+
return 0;
}
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 5/7] tegra: add driver for the clock and reset module
2013-03-01 9:22 ` [PATCH 5/7] tegra: add driver for the clock and reset module Lucas Stach
@ 2013-03-01 17:26 ` Sascha Hauer
2013-03-02 23:16 ` Lucas Stach
0 siblings, 1 reply; 41+ messages in thread
From: Sascha Hauer @ 2013-03-01 17:26 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Fri, Mar 01, 2013 at 10:22:51AM +0100, Lucas Stach wrote:
> Only a basic set of clocks is supported as of now.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/Kconfig | 2 +
> arch/arm/mach-tegra/Makefile | 1 +
> arch/arm/mach-tegra/include/mach/clkdev.h | 7 ++
> arch/arm/mach-tegra/tegra20-car.c | 117 ++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 4 +
> 5 files changed, 131 insertions(+)
> create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-tegra/tegra20-car.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1c41e44..a3828e1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -108,6 +108,8 @@ config ARCH_VERSATILE
> config ARCH_TEGRA
> bool "Nvidia Tegra-based boards"
> select CPU_V7
> + select COMMON_CLK
> + select CLKDEV_LOOKUP
>
> endchoice
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 7777d0a..3391528 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,3 +1,4 @@
> obj-y += clock.o
> obj-y += reset.o
> obj-y += tegra20.o
> +obj-y += tegra20-car.o
> diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
> new file mode 100644
> index 0000000..04b37a8
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/clkdev.h
> @@ -0,0 +1,7 @@
> +#ifndef __ASM_MACH_CLKDEV_H
> +#define __ASM_MACH_CLKDEV_H
> +
> +#define __clk_get(clk) ({ 1; })
> +#define __clk_put(clk) do { } while (0)
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
> new file mode 100644
> index 0000000..95b3051
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-car.c
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 clock and reset (CAR) controller
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +
> +/* Register definitions */
> +#define OSC_CTRL 0x50
> +#define OSC_CTRL_OSC_FREQ_MASK (3 << 30)
> +#define OSC_CTRL_PLL_REF_DIV_MASK (3 << 28)
> +
> +static void __iomem *car_base;
> +
> +enum tegra20_clks {
> + cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
> + ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
> + gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
> + kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
> + dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
> + usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
> + pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
> + iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
> + uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
> + osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
> + pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
> + pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
> + pll_x, audio, pll_ref, twd, clk_max,
> +};
> +
> +static struct clk *clks[clk_max];
> +
> +static unsigned long get_osc_frequency(void)
> +{
> + u32 osc_ctrl = readl(car_base + OSC_CTRL);
> +
> + switch (osc_ctrl & OSC_CTRL_OSC_FREQ_MASK) {
OSC_CTRL_OSC_FREQ_MASK is defined as 3 << 30, The result will never be
one of the values below.
> + case 0:
> + return 13000000;
> + case 1:
> + return 19200000;
> + case 2:
> + return 12000000;
> + case 3:
> + return 26000000;
> + default:
> + return 0;
> + }
> +}
> +
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 5/7] tegra: add driver for the clock and reset module
2013-03-01 17:26 ` Sascha Hauer
@ 2013-03-02 23:16 ` Lucas Stach
0 siblings, 0 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-02 23:16 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Am Freitag, den 01.03.2013, 18:26 +0100 schrieb Sascha Hauer:
> > +
> > +static unsigned long get_osc_frequency(void)
> > +{
> > + u32 osc_ctrl = readl(car_base + OSC_CTRL);
> > +
> > + switch (osc_ctrl & OSC_CTRL_OSC_FREQ_MASK) {
>
> OSC_CTRL_OSC_FREQ_MASK is defined as 3 << 30, The result will never be
> one of the values below.
>
> > + case 0:
> > + return 13000000;
> > + case 1:
> > + return 19200000;
> > + case 2:
> > + return 12000000;
> > + case 3:
> > + return 26000000;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
>
Grr, correct. Thanks for spotting. Just got bitten by my system using a
13MHz crystal.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 6/7] tegra: add proper timer driver
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
` (4 preceding siblings ...)
2013-03-01 9:22 ` [PATCH 5/7] tegra: add driver for the clock and reset module Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 13:14 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 17:23 ` Sascha Hauer
2013-03-01 9:22 ` [PATCH 7/7] tegra: add power management controller driver Lucas Stach
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
7 siblings, 2 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Replace the ad-hoc clocksource implementation with a proper driver for
the Tegra 20 timer. This driver is able to do the required hardware
initialisation itself.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/clock.c | 56 -----------------
arch/arm/mach-tegra/tegra20-car.c | 6 ++
arch/arm/mach-tegra/tegra20-timer.c | 117 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 4 ++
5 files changed, 128 insertions(+), 57 deletions(-)
delete mode 100644 arch/arm/mach-tegra/clock.c
create mode 100644 arch/arm/mach-tegra/tegra20-timer.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 3391528..6aa219c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,4 +1,4 @@
-obj-y += clock.o
obj-y += reset.o
obj-y += tegra20.o
obj-y += tegra20-car.o
+obj-y += tegra20-timer.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
deleted file mode 100644
index 8a7525d..0000000
--- a/arch/arm/mach-tegra/clock.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Clocksource based on Tegra internal timer
- */
-
-#include <common.h>
-#include <clock.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <init.h>
-#include <asm/io.h>
-#include <mach/tegra20-silicon.h>
-
-static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
-
-#define timer_writel(value, reg) \
- __raw_writel(value, (u32)timer_reg_base + (reg))
-#define timer_readl(reg) \
- __raw_readl((u32)timer_reg_base + (reg))
-
-static uint64_t tegra_clocksource_read(void)
-{
- return timer_readl(0x10);
-}
-
-static struct clocksource cs = {
- .read = tegra_clocksource_read,
- .mask = 0xffffffff,
-};
-
-/* FIXME: here we have no initialization. All initialization made by U-Boot */
-static int clocksource_init(void)
-{
- cs.mult = clocksource_hz2mult(1000000, cs.shift);
- init_clock(&cs);
-
- return 0;
-}
-core_initcall(clocksource_init);
diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
index 95b3051..89fa424 100644
--- a/arch/arm/mach-tegra/tegra20-car.c
+++ b/arch/arm/mach-tegra/tegra20-car.c
@@ -24,7 +24,9 @@
#include <init.h>
#include <io.h>
#include <linux/clk.h>
+#include <linux/clkdev.h>
#include <linux/err.h>
+#include <mach/tegra20-silicon.h>
/* Register definitions */
#define OSC_CTRL 0x50
@@ -93,6 +95,10 @@ static int tegra20_car_probe(struct device_d *dev)
/* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
+
+ /* device to clock links */
+ clkdev_add_physbase(clks[timer], TEGRA_TMR1_BASE, NULL);
+
return 0;
}
diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c
new file mode 100644
index 0000000..62af5d2
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-timer.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 timer, which exposes a clocksource.
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+
+/* register definitions */
+#define TIMERUS_CNTR_1US 0x10
+#define TIMERUS_USEC_CFG 0x14
+
+static void __iomem *timer_base;
+
+static uint64_t tegra20_timer_cs_read(void)
+{
+ return readl(timer_base + TIMERUS_CNTR_1US);
+}
+
+static struct clocksource cs = {
+ .read = tegra20_timer_cs_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .mult = 1000,
+};
+
+static int tegra20_timer_probe(struct device_d *dev)
+{
+ struct clk *timer_clk;
+ unsigned long rate;
+
+ /* use only one timer */
+ if (timer_base)
+ return -EBUSY;
+
+ timer_base = dev_request_mem_region(dev, 0);
+ if (!timer_base) {
+ dev_err(dev, "could not get memory region\n");
+ return -ENODEV;
+ }
+
+ timer_clk = clk_get(dev, NULL);
+ if (!timer_clk) {
+ dev_err(dev, "could not get clock\n");
+ return -ENODEV;
+ }
+
+ clk_enable(timer_clk);
+
+ /*
+ * calibrate timer to run at 1MHz
+ * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
+ * representing the divisor and bits [8:15] representing the dividend
+ * each in n+1 form.
+ */
+ rate = clk_get_rate(timer_clk);
+ switch (rate) {
+ case 12000000:
+ writel(0x000b, timer_base + TIMERUS_USEC_CFG);
+ break;
+ case 13000000:
+ writel(0x000c, timer_base + TIMERUS_USEC_CFG);
+ break;
+ case 19200000:
+ writel(0x045f, timer_base + TIMERUS_USEC_CFG);
+ break;
+ case 26000000:
+ writel(0x0019, timer_base + TIMERUS_USEC_CFG);
+ break;
+ default:
+ dev_warn(dev, "unknown timer clock rate\n");
+ break;
+ }
+
+ init_clock(&cs);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-timer",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_timer_driver = {
+ .probe = tegra20_timer_probe,
+ .name = "tegra20-timer",
+ .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
+};
+
+static int tegra20_timer_init(void)
+{
+ return platform_driver_register(&tegra20_timer_driver);
+}
+
+coredevice_initcall(tegra20_timer_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index 08c6758..eccc7b8 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -24,6 +24,10 @@ static int tegra20_init(void)
TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
IORESOURCE_MEM, NULL);
+ add_generic_device("tegra20-timer", DEVICE_ID_SINGLE, NULL,
+ TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
+ IORESOURCE_MEM, NULL);
+
return 0;
}
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-01 9:22 ` [PATCH 6/7] tegra: add proper timer driver Lucas Stach
@ 2013-03-01 13:14 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 17:23 ` Sascha Hauer
1 sibling, 0 replies; 41+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-01 13:14 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 10:22 Fri 01 Mar , Lucas Stach wrote:
> Replace the ad-hoc clocksource implementation with a proper driver for
> the Tegra 20 timer. This driver is able to do the required hardware
> initialisation itself.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/mach-tegra/Makefile | 2 +-
> arch/arm/mach-tegra/clock.c | 56 -----------------
> arch/arm/mach-tegra/tegra20-car.c | 6 ++
> arch/arm/mach-tegra/tegra20-timer.c | 117 ++++++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 4 ++
> 5 files changed, 128 insertions(+), 57 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/clock.c
> create mode 100644 arch/arm/mach-tegra/tegra20-timer.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 3391528..6aa219c 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,4 +1,4 @@
> -obj-y += clock.o
> obj-y += reset.o
> obj-y += tegra20.o
> obj-y += tegra20-car.o
> +obj-y += tegra20-timer.o
> diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
> deleted file mode 100644
> index 8a7525d..0000000
> --- a/arch/arm/mach-tegra/clock.c
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/*
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -/**
> - * @file
> - * @brief Clocksource based on Tegra internal timer
> - */
> -
> -#include <common.h>
> -#include <clock.h>
> -#include <linux/list.h>
> -#include <linux/clk.h>
> -#include <init.h>
> -#include <asm/io.h>
> -#include <mach/tegra20-silicon.h>
> -
> -static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
> -
> -#define timer_writel(value, reg) \
> - __raw_writel(value, (u32)timer_reg_base + (reg))
> -#define timer_readl(reg) \
> - __raw_readl((u32)timer_reg_base + (reg))
> -
> -static uint64_t tegra_clocksource_read(void)
> -{
> - return timer_readl(0x10);
> -}
> -
> -static struct clocksource cs = {
> - .read = tegra_clocksource_read,
> - .mask = 0xffffffff,
> -};
> -
> -/* FIXME: here we have no initialization. All initialization made by U-Boot */
> -static int clocksource_init(void)
> -{
> - cs.mult = clocksource_hz2mult(1000000, cs.shift);
> - init_clock(&cs);
> -
> - return 0;
> -}
> -core_initcall(clocksource_init);
> diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
> index 95b3051..89fa424 100644
> --- a/arch/arm/mach-tegra/tegra20-car.c
> +++ b/arch/arm/mach-tegra/tegra20-car.c
> @@ -24,7 +24,9 @@
> #include <init.h>
> #include <io.h>
> #include <linux/clk.h>
> +#include <linux/clkdev.h>
> #include <linux/err.h>
> +#include <mach/tegra20-silicon.h>
>
> /* Register definitions */
> #define OSC_CTRL 0x50
> @@ -93,6 +95,10 @@ static int tegra20_car_probe(struct device_d *dev)
> /* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
> clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
>
> +
> + /* device to clock links */
> + clkdev_add_physbase(clks[timer], TEGRA_TMR1_BASE, NULL);
> +
> return 0;
> }
>
> diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c
> new file mode 100644
> index 0000000..62af5d2
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-timer.c
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 timer, which exposes a clocksource.
> + */
> +
> +#include <common.h>
> +#include <clock.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/clk.h>
> +
> +/* register definitions */
> +#define TIMERUS_CNTR_1US 0x10
> +#define TIMERUS_USEC_CFG 0x14
> +
> +static void __iomem *timer_base;
> +
> +static uint64_t tegra20_timer_cs_read(void)
> +{
> + return readl(timer_base + TIMERUS_CNTR_1US);
> +}
> +
> +static struct clocksource cs = {
> + .read = tegra20_timer_cs_read,
> + .mask = CLOCKSOURCE_MASK(32),
> + .mult = 1000,
no calculate it
> +};
> +
> +static int tegra20_timer_probe(struct device_d *dev)
> +{
> + struct clk *timer_clk;
> + unsigned long rate;
> +
> + /* use only one timer */
> + if (timer_base)
> + return -EBUSY;
> +
> + timer_base = dev_request_mem_region(dev, 0);
> + if (!timer_base) {
> + dev_err(dev, "could not get memory region\n");
> + return -ENODEV;
> + }
> +
> + timer_clk = clk_get(dev, NULL);
> + if (!timer_clk) {
> + dev_err(dev, "could not get clock\n");
> + return -ENODEV;
> + }
> +
> + clk_enable(timer_clk);
> +
> + /*
> + * calibrate timer to run at 1MHz
> + * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
> + * representing the divisor and bits [8:15] representing the dividend
> + * each in n+1 form.
> + */
> + rate = clk_get_rate(timer_clk);
> + switch (rate) {
> + case 12000000:
> + writel(0x000b, timer_base + TIMERUS_USEC_CFG);
> + break;
> + case 13000000:
> + writel(0x000c, timer_base + TIMERUS_USEC_CFG);
> + break;
> + case 19200000:
> + writel(0x045f, timer_base + TIMERUS_USEC_CFG);
> + break;
> + case 26000000:
> + writel(0x0019, timer_base + TIMERUS_USEC_CFG);
you put 4 write NO
just 1
> + break;
> + default:
> + dev_warn(dev, "unknown timer clock rate\n");
> + break;
> + }
here
> +
> + init_clock(&cs);
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-timer",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d tegra20_timer_driver = {
> + .probe = tegra20_timer_probe,
> + .name = "tegra20-timer",
> + .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
> +};
> +
> +static int tegra20_timer_init(void)
> +{
> + return platform_driver_register(&tegra20_timer_driver);
> +}
> +
> +coredevice_initcall(tegra20_timer_init);
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> index 08c6758..eccc7b8 100644
> --- a/arch/arm/mach-tegra/tegra20.c
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -24,6 +24,10 @@ static int tegra20_init(void)
> TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
> IORESOURCE_MEM, NULL);
>
> + add_generic_device("tegra20-timer", DEVICE_ID_SINGLE, NULL,
> + TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
> + IORESOURCE_MEM, NULL);
> +
> return 0;
> }
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-01 9:22 ` [PATCH 6/7] tegra: add proper timer driver Lucas Stach
2013-03-01 13:14 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-03-01 17:23 ` Sascha Hauer
2013-03-02 23:13 ` Lucas Stach
1 sibling, 1 reply; 41+ messages in thread
From: Sascha Hauer @ 2013-03-01 17:23 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Fri, Mar 01, 2013 at 10:22:52AM +0100, Lucas Stach wrote:
> Replace the ad-hoc clocksource implementation with a proper driver for
> the Tegra 20 timer. This driver is able to do the required hardware
> initialisation itself.
>
> +
> +static int tegra20_timer_probe(struct device_d *dev)
> +{
> + struct clk *timer_clk;
> + unsigned long rate;
> +
> + /* use only one timer */
> + if (timer_base)
> + return -EBUSY;
> +
> + timer_base = dev_request_mem_region(dev, 0);
> + if (!timer_base) {
> + dev_err(dev, "could not get memory region\n");
> + return -ENODEV;
> + }
> +
> + timer_clk = clk_get(dev, NULL);
> + if (!timer_clk) {
> + dev_err(dev, "could not get clock\n");
> + return -ENODEV;
> + }
> +
> + clk_enable(timer_clk);
> +
> + /*
> + * calibrate timer to run at 1MHz
We don't need the timer to be running at a certain frequency, you can
just use clocks_calc_mult_shift to calculate the correct values from
whatever frequency.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-01 17:23 ` Sascha Hauer
@ 2013-03-02 23:13 ` Lucas Stach
2013-03-03 7:07 ` Antony Pavlov
0 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-02 23:13 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Am Freitag, den 01.03.2013, 18:23 +0100 schrieb Sascha Hauer:
> On Fri, Mar 01, 2013 at 10:22:52AM +0100, Lucas Stach wrote:
> > Replace the ad-hoc clocksource implementation with a proper driver for
> > the Tegra 20 timer. This driver is able to do the required hardware
> > initialisation itself.
> >
> > +
> > +static int tegra20_timer_probe(struct device_d *dev)
> > +{
> > + struct clk *timer_clk;
> > + unsigned long rate;
> > +
> > + /* use only one timer */
> > + if (timer_base)
> > + return -EBUSY;
> > +
> > + timer_base = dev_request_mem_region(dev, 0);
> > + if (!timer_base) {
> > + dev_err(dev, "could not get memory region\n");
> > + return -ENODEV;
> > + }
> > +
> > + timer_clk = clk_get(dev, NULL);
> > + if (!timer_clk) {
> > + dev_err(dev, "could not get clock\n");
> > + return -ENODEV;
> > + }
> > +
> > + clk_enable(timer_clk);
> > +
> > + /*
> > + * calibrate timer to run at 1MHz
>
> We don't need the timer to be running at a certain frequency, you can
> just use clocks_calc_mult_shift to calculate the correct values from
> whatever frequency.
Other hardware blocks like the flow controller might assume the timer to
be running at 1MHz. The timer and time register is named US (like usec)
for a reason. It's the officially correct way to initialize this timer
(as documented in the Tegra TRM).
Regards,
Lucas
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-02 23:13 ` Lucas Stach
@ 2013-03-03 7:07 ` Antony Pavlov
2013-03-04 17:09 ` Lucas Stach
0 siblings, 1 reply; 41+ messages in thread
From: Antony Pavlov @ 2013-03-03 7:07 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 3 March 2013 03:13, Lucas Stach <dev@lynxeye.de> wrote:
> Am Freitag, den 01.03.2013, 18:23 +0100 schrieb Sascha Hauer:
>> On Fri, Mar 01, 2013 at 10:22:52AM +0100, Lucas Stach wrote:
>> > Replace the ad-hoc clocksource implementation with a proper driver for
>> > the Tegra 20 timer. This driver is able to do the required hardware
>> > initialisation itself.
>> >
>> > +
>> > +static int tegra20_timer_probe(struct device_d *dev)
>> > +{
>> > + struct clk *timer_clk;
>> > + unsigned long rate;
>> > +
>> > + /* use only one timer */
>> > + if (timer_base)
>> > + return -EBUSY;
>> > +
>> > + timer_base = dev_request_mem_region(dev, 0);
>> > + if (!timer_base) {
>> > + dev_err(dev, "could not get memory region\n");
>> > + return -ENODEV;
>> > + }
>> > +
>> > + timer_clk = clk_get(dev, NULL);
>> > + if (!timer_clk) {
>> > + dev_err(dev, "could not get clock\n");
>> > + return -ENODEV;
>> > + }
>> > +
>> > + clk_enable(timer_clk);
>> > +
>> > + /*
>> > + * calibrate timer to run at 1MHz
>>
>> We don't need the timer to be running at a certain frequency, you can
>> just use clocks_calc_mult_shift to calculate the correct values from
>> whatever frequency.
>
> Other hardware blocks like the flow controller might assume the timer to
> be running at 1MHz. The timer and time register is named US (like usec)
> for a reason. It's the officially correct way to initialize this timer
> (as documented in the Tegra TRM).
IMHO, then Jean-Christophe speaking about 'just use
clocks_calc_mult_shift' he mean this part of your
arch/arm/mach-tegra/tegra20-timer.c:
+static struct clocksource cs = {
+ .read = tegra20_timer_cs_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .mult = 1000,
+};
He want to say "please don't use fixed 'mult' value, use
clocks_calc_mult_shift to calculate it".
Please try to examine existing clocksources.
The command
grep -R -A 5 "static struct clocksource.*=" arch/arm/
will show you some results like this
arch/arm/mach-imx/clocksource.c:static struct clocksource cs = {
arch/arm/mach-imx/clocksource.c- .read = imx_clocksource_read,
arch/arm/mach-imx/clocksource.c- .mask = CLOCKSOURCE_MASK(32),
arch/arm/mach-imx/clocksource.c- .shift = 10,
arch/arm/mach-imx/clocksource.c-};
or even like that
arch/arm/mach-clps711x/clock.c:static struct clocksource cs = {
arch/arm/mach-clps711x/clock.c- .read = clocksource_read,
arch/arm/mach-clps711x/clock.c- .mask = CLOCKSOURCE_MASK(16),
arch/arm/mach-clps711x/clock.c-};
But I can't find any example of 'struct clocksource' definition with
fixed 'mult' value.
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-03 7:07 ` Antony Pavlov
@ 2013-03-04 17:09 ` Lucas Stach
2013-03-04 19:14 ` Antony Pavlov
0 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-04 17:09 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Am Sonntag, den 03.03.2013, 11:07 +0400 schrieb Antony Pavlov:
> On 3 March 2013 03:13, Lucas Stach <dev@lynxeye.de> wrote:
> > Am Freitag, den 01.03.2013, 18:23 +0100 schrieb Sascha Hauer:
> >> On Fri, Mar 01, 2013 at 10:22:52AM +0100, Lucas Stach wrote:
> >> > Replace the ad-hoc clocksource implementation with a proper driver for
> >> > the Tegra 20 timer. This driver is able to do the required hardware
> >> > initialisation itself.
> >> >
> >> > +
> >> > +static int tegra20_timer_probe(struct device_d *dev)
> >> > +{
> >> > + struct clk *timer_clk;
> >> > + unsigned long rate;
> >> > +
> >> > + /* use only one timer */
> >> > + if (timer_base)
> >> > + return -EBUSY;
> >> > +
> >> > + timer_base = dev_request_mem_region(dev, 0);
> >> > + if (!timer_base) {
> >> > + dev_err(dev, "could not get memory region\n");
> >> > + return -ENODEV;
> >> > + }
> >> > +
> >> > + timer_clk = clk_get(dev, NULL);
> >> > + if (!timer_clk) {
> >> > + dev_err(dev, "could not get clock\n");
> >> > + return -ENODEV;
> >> > + }
> >> > +
> >> > + clk_enable(timer_clk);
> >> > +
> >> > + /*
> >> > + * calibrate timer to run at 1MHz
> >>
> >> We don't need the timer to be running at a certain frequency, you can
> >> just use clocks_calc_mult_shift to calculate the correct values from
> >> whatever frequency.
> >
> > Other hardware blocks like the flow controller might assume the timer to
> > be running at 1MHz. The timer and time register is named US (like usec)
> > for a reason. It's the officially correct way to initialize this timer
> > (as documented in the Tegra TRM).
>
> IMHO, then Jean-Christophe speaking about 'just use
> clocks_calc_mult_shift' he mean this part of your
> arch/arm/mach-tegra/tegra20-timer.c:
>
> +static struct clocksource cs = {
> + .read = tegra20_timer_cs_read,
> + .mask = CLOCKSOURCE_MASK(32),
> + .mult = 1000,
> +};
>
> He want to say "please don't use fixed 'mult' value, use
> clocks_calc_mult_shift to calculate it".
>
> Please try to examine existing clocksources.
>
> The command
> grep -R -A 5 "static struct clocksource.*=" arch/arm/
> will show you some results like this
>
> arch/arm/mach-imx/clocksource.c:static struct clocksource cs = {
> arch/arm/mach-imx/clocksource.c- .read = imx_clocksource_read,
> arch/arm/mach-imx/clocksource.c- .mask = CLOCKSOURCE_MASK(32),
> arch/arm/mach-imx/clocksource.c- .shift = 10,
> arch/arm/mach-imx/clocksource.c-};
>
> or even like that
> arch/arm/mach-clps711x/clock.c:static struct clocksource cs = {
> arch/arm/mach-clps711x/clock.c- .read = clocksource_read,
> arch/arm/mach-clps711x/clock.c- .mask = CLOCKSOURCE_MASK(16),
> arch/arm/mach-clps711x/clock.c-};
>
> But I can't find any example of 'struct clocksource' definition with
> fixed 'mult' value.
>
I've looked at other clocksource drivers before implementing the Tegra
one and it's right that all other clocksources calculate the mult at
runtime. But as the Tegra clocksource is guaranteed to run at 1MHz at
every point in time I don't really see any benefit of calculating the
mult over just having it as static init data.
Is there anything I'm missing?
Regards,
Lucas
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 6/7] tegra: add proper timer driver
2013-03-04 17:09 ` Lucas Stach
@ 2013-03-04 19:14 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-04 19:14 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 4 March 2013 21:09, Lucas Stach <dev@lynxeye.de> wrote:
> Am Sonntag, den 03.03.2013, 11:07 +0400 schrieb Antony Pavlov:
>> On 3 March 2013 03:13, Lucas Stach <dev@lynxeye.de> wrote:
>> > Am Freitag, den 01.03.2013, 18:23 +0100 schrieb Sascha Hauer:
>> >> On Fri, Mar 01, 2013 at 10:22:52AM +0100, Lucas Stach wrote:
>> >> > Replace the ad-hoc clocksource implementation with a proper driver for
>> >> > the Tegra 20 timer. This driver is able to do the required hardware
>> >> > initialisation itself.
>> >> >
>> >> > +
>> >> > +static int tegra20_timer_probe(struct device_d *dev)
>> >> > +{
>> >> > + struct clk *timer_clk;
>> >> > + unsigned long rate;
>> >> > +
>> >> > + /* use only one timer */
>> >> > + if (timer_base)
>> >> > + return -EBUSY;
>> >> > +
>> >> > + timer_base = dev_request_mem_region(dev, 0);
>> >> > + if (!timer_base) {
>> >> > + dev_err(dev, "could not get memory region\n");
>> >> > + return -ENODEV;
>> >> > + }
>> >> > +
>> >> > + timer_clk = clk_get(dev, NULL);
>> >> > + if (!timer_clk) {
>> >> > + dev_err(dev, "could not get clock\n");
>> >> > + return -ENODEV;
>> >> > + }
>> >> > +
>> >> > + clk_enable(timer_clk);
>> >> > +
>> >> > + /*
>> >> > + * calibrate timer to run at 1MHz
>> >>
>> >> We don't need the timer to be running at a certain frequency, you can
>> >> just use clocks_calc_mult_shift to calculate the correct values from
>> >> whatever frequency.
>> >
>> > Other hardware blocks like the flow controller might assume the timer to
>> > be running at 1MHz. The timer and time register is named US (like usec)
>> > for a reason. It's the officially correct way to initialize this timer
>> > (as documented in the Tegra TRM).
>>
>> IMHO, then Jean-Christophe speaking about 'just use
>> clocks_calc_mult_shift' he mean this part of your
>> arch/arm/mach-tegra/tegra20-timer.c:
>>
>> +static struct clocksource cs = {
>> + .read = tegra20_timer_cs_read,
>> + .mask = CLOCKSOURCE_MASK(32),
>> + .mult = 1000,
>> +};
>>
>> He want to say "please don't use fixed 'mult' value, use
>> clocks_calc_mult_shift to calculate it".
>>
>> Please try to examine existing clocksources.
>>
>> The command
>> grep -R -A 5 "static struct clocksource.*=" arch/arm/
>> will show you some results like this
>>
>> arch/arm/mach-imx/clocksource.c:static struct clocksource cs = {
>> arch/arm/mach-imx/clocksource.c- .read = imx_clocksource_read,
>> arch/arm/mach-imx/clocksource.c- .mask = CLOCKSOURCE_MASK(32),
>> arch/arm/mach-imx/clocksource.c- .shift = 10,
>> arch/arm/mach-imx/clocksource.c-};
>>
>> or even like that
>> arch/arm/mach-clps711x/clock.c:static struct clocksource cs = {
>> arch/arm/mach-clps711x/clock.c- .read = clocksource_read,
>> arch/arm/mach-clps711x/clock.c- .mask = CLOCKSOURCE_MASK(16),
>> arch/arm/mach-clps711x/clock.c-};
>>
>> But I can't find any example of 'struct clocksource' definition with
>> fixed 'mult' value.
>>
>
> I've looked at other clocksource drivers before implementing the Tegra
> one and it's right that all other clocksources calculate the mult at
> runtime. But as the Tegra clocksource is guaranteed to run at 1MHz at
> every point in time I don't really see any benefit of calculating the
> mult over just having it as static init data.
>
> Is there anything I'm missing?
You use your knowlege about the clock rate twice:
* then you actually set up the clock rate;
* then you set up the clocksource device data structure (the values
of the 'shift' and the 'mult' fields).
But there is no any EXPLICIT relation between the clock rate and the
'shift' and 'mult' values; It is not clear and evident that if you
change the clock frequency you must change the 'mult' value too. There
are a techical means to change clock frequency in spite of the
recommended clock frequency is 1 MHz. Don't forget the quote from the
book 'Murphy's laws and corollaries':
Anything that can go wrong will go wrong.
In the short-term your tricky realisation looks good, but in the
long-term it is a potential source of a problems.
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 7/7] tegra: add power management controller driver
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
` (5 preceding siblings ...)
2013-03-01 9:22 ` [PATCH 6/7] tegra: add proper timer driver Lucas Stach
@ 2013-03-01 9:22 ` Lucas Stach
2013-03-01 13:15 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
7 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-01 9:22 UTC (permalink / raw)
To: barebox
Currently only implements system wide reset functionality.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/reset.c | 39 -----------------
arch/arm/mach-tegra/tegra20-pmc.c | 89 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 4 ++
4 files changed, 94 insertions(+), 40 deletions(-)
delete mode 100644 arch/arm/mach-tegra/reset.c
create mode 100644 arch/arm/mach-tegra/tegra20-pmc.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6aa219c..bcc0cd4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,4 +1,4 @@
-obj-y += reset.o
obj-y += tegra20.o
obj-y += tegra20-car.o
+obj-y += tegra20-pmc.o
obj-y += tegra20-timer.o
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
deleted file mode 100644
index 73d7ca2..0000000
--- a/arch/arm/mach-tegra/reset.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Resetting an malta board
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <mach/tegra20-silicon.h>
-
-#define PRM_RSTCTRL TEGRA_PMC_BASE
-
-void __noreturn reset_cpu(ulong addr)
-{
- int rstctrl;
-
- rstctrl = __raw_readl((char *)PRM_RSTCTRL);
- rstctrl |= 0x10;
- __raw_writel(rstctrl, (char *)PRM_RSTCTRL);
-
- unreachable();
-}
-EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
new file mode 100644
index 0000000..ed765f5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 power management controller.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+
+/* register definitions */
+#define PMC_CNTRL 0x00
+#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
+#define PMC_CNTRL_INTR_POLARITY (1 << 17)
+#define PMC_CNTRL_CPUPWRREQ_OE (1 << 16)
+#define PMC_CNTRL_CPUPWRREQ_POLARITY (1 << 15)
+#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
+#define PMC_CNTRL_AOINIT (1 << 13)
+#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
+#define PMC_CNTRL_SYSCLK_OE (1 << 11)
+#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
+#define PMC_CNTRL_PWRREQ_OE (1 << 9)
+#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
+#define PMC_CNTRL_BLINK_EN (1 << 7)
+#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
+#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
+#define PMC_CNTRL_MAIN_RST (1 << 4)
+#define PMC_CNTRL_KBC_RST (1 << 3)
+#define PMC_CNTRL_RTC_RST (1 << 2)
+#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
+#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
+
+static void __iomem *pmc_base;
+
+/* main SoC reset trigger */
+void __noreturn reset_cpu(ulong addr)
+{
+ writel(PMC_CNTRL_MAIN_RST, pmc_base + PMC_CNTRL);
+
+ unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
+
+static int tegra20_pmc_probe(struct device_d *dev)
+{
+ pmc_base = dev_request_mem_region(dev, 0);
+ if (!pmc_base) {
+ dev_err(dev, "could not get memory region\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-pmc",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_pmc_driver = {
+ .probe = tegra20_pmc_probe,
+ .name = "tegra20-pmc",
+ .of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
+};
+
+static int tegra20_pmc_init(void)
+{
+ return platform_driver_register(&tegra20_pmc_driver);
+}
+
+coredevice_initcall(tegra20_pmc_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index eccc7b8..54e8819 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -28,6 +28,10 @@ static int tegra20_init(void)
TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
IORESOURCE_MEM, NULL);
+ add_generic_device("tegra20-pmc", DEVICE_ID_SINGLE, NULL,
+ TEGRA_PMC_BASE, TEGRA_PMC_SIZE,
+ IORESOURCE_MEM, NULL);
+
return 0;
}
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 7/7] tegra: add power management controller driver
2013-03-01 9:22 ` [PATCH 7/7] tegra: add power management controller driver Lucas Stach
@ 2013-03-01 13:15 ` Jean-Christophe PLAGNIOL-VILLARD
2013-03-01 17:28 ` Sascha Hauer
0 siblings, 1 reply; 41+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-01 13:15 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 10:22 Fri 01 Mar , Lucas Stach wrote:
> Currently only implements system wide reset functionality.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
you work for pengu I expect the proper e-mail here and in the author
> ---
> arch/arm/mach-tegra/Makefile | 2 +-
> arch/arm/mach-tegra/reset.c | 39 -----------------
> arch/arm/mach-tegra/tegra20-pmc.c | 89 +++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 4 ++
> 4 files changed, 94 insertions(+), 40 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/reset.c
> create mode 100644 arch/arm/mach-tegra/tegra20-pmc.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 6aa219c..bcc0cd4 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,4 +1,4 @@
> -obj-y += reset.o
> obj-y += tegra20.o
> obj-y += tegra20-car.o
> +obj-y += tegra20-pmc.o
> obj-y += tegra20-timer.o
> diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
> deleted file mode 100644
> index 73d7ca2..0000000
> --- a/arch/arm/mach-tegra/reset.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/*
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -/**
> - * @file
> - * @brief Resetting an malta board
> - */
> -
> -#include <common.h>
> -#include <asm/io.h>
> -#include <mach/tegra20-silicon.h>
> -
> -#define PRM_RSTCTRL TEGRA_PMC_BASE
> -
> -void __noreturn reset_cpu(ulong addr)
> -{
> - int rstctrl;
> -
> - rstctrl = __raw_readl((char *)PRM_RSTCTRL);
> - rstctrl |= 0x10;
> - __raw_writel(rstctrl, (char *)PRM_RSTCTRL);
> -
> - unreachable();
> -}
> -EXPORT_SYMBOL(reset_cpu);
> diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
> new file mode 100644
> index 0000000..ed765f5
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-pmc.c
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 power management controller.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +
> +/* register definitions */
> +#define PMC_CNTRL 0x00
> +#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
> +#define PMC_CNTRL_INTR_POLARITY (1 << 17)
> +#define PMC_CNTRL_CPUPWRREQ_OE (1 << 16)
> +#define PMC_CNTRL_CPUPWRREQ_POLARITY (1 << 15)
> +#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
> +#define PMC_CNTRL_AOINIT (1 << 13)
> +#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
> +#define PMC_CNTRL_SYSCLK_OE (1 << 11)
> +#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
> +#define PMC_CNTRL_PWRREQ_OE (1 << 9)
> +#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
> +#define PMC_CNTRL_BLINK_EN (1 << 7)
> +#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
> +#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
> +#define PMC_CNTRL_MAIN_RST (1 << 4)
> +#define PMC_CNTRL_KBC_RST (1 << 3)
> +#define PMC_CNTRL_RTC_RST (1 << 2)
> +#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
> +#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
> +
> +static void __iomem *pmc_base;
> +
> +/* main SoC reset trigger */
> +void __noreturn reset_cpu(ulong addr)
> +{
> + writel(PMC_CNTRL_MAIN_RST, pmc_base + PMC_CNTRL);
> +
> + unreachable();
> +}
> +EXPORT_SYMBOL(reset_cpu);
> +
> +static int tegra20_pmc_probe(struct device_d *dev)
> +{
> + pmc_base = dev_request_mem_region(dev, 0);
> + if (!pmc_base) {
> + dev_err(dev, "could not get memory region\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-pmc",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d tegra20_pmc_driver = {
> + .probe = tegra20_pmc_probe,
> + .name = "tegra20-pmc",
> + .of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
> +};
> +
> +static int tegra20_pmc_init(void)
> +{
> + return platform_driver_register(&tegra20_pmc_driver);
> +}
> +
> +coredevice_initcall(tegra20_pmc_init);
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> index eccc7b8..54e8819 100644
> --- a/arch/arm/mach-tegra/tegra20.c
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -28,6 +28,10 @@ static int tegra20_init(void)
> TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
> IORESOURCE_MEM, NULL);
>
> + add_generic_device("tegra20-pmc", DEVICE_ID_SINGLE, NULL,
> + TEGRA_PMC_BASE, TEGRA_PMC_SIZE,
> + IORESOURCE_MEM, NULL);
> +
> return 0;
> }
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH 7/7] tegra: add power management controller driver
2013-03-01 13:15 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-03-01 17:28 ` Sascha Hauer
2013-03-01 18:00 ` Antony Pavlov
0 siblings, 1 reply; 41+ messages in thread
From: Sascha Hauer @ 2013-03-01 17:28 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Fri, Mar 01, 2013 at 02:15:34PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 10:22 Fri 01 Mar , Lucas Stach wrote:
> > Currently only implements system wide reset functionality.
> >
> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> you work for pengu I expect the proper e-mail here and in the author
If Lucas is doing this at home why shouldn't he use his private address?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 7/7] tegra: add power management controller driver
2013-03-01 17:28 ` Sascha Hauer
@ 2013-03-01 18:00 ` Antony Pavlov
2013-03-02 23:21 ` Lucas Stach
0 siblings, 1 reply; 41+ messages in thread
From: Antony Pavlov @ 2013-03-01 18:00 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 1 March 2013 21:28, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Fri, Mar 01, 2013 at 02:15:34PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 10:22 Fri 01 Mar , Lucas Stach wrote:
>> > Currently only implements system wide reset functionality.
>> >
>> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> you work for pengu I expect the proper e-mail here and in the author
>
> If Lucas is doing this at home why shouldn't he use his private address?
But he uses Pengutronix e-mail address inside c-files (e.g. see
arch/arm/mach-tegra/tegra20-car.c).
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 7/7] tegra: add power management controller driver
2013-03-01 18:00 ` Antony Pavlov
@ 2013-03-02 23:21 ` Lucas Stach
0 siblings, 0 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-02 23:21 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Am Freitag, den 01.03.2013, 22:00 +0400 schrieb Antony Pavlov:
> On 1 March 2013 21:28, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Fri, Mar 01, 2013 at 02:15:34PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 10:22 Fri 01 Mar , Lucas Stach wrote:
> >> > Currently only implements system wide reset functionality.
> >> >
> >> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> >> you work for pengu I expect the proper e-mail here and in the author
> >
> > If Lucas is doing this at home why shouldn't he use his private address?
>
> But he uses Pengutronix e-mail address inside c-files (e.g. see
> arch/arm/mach-tegra/tegra20-car.c).
>
I know this is a bit schizophrenic. While I work for Pengutronix Tegra
is my personal pet project so it get's signed off with my personal mail
address, still I would like for mails regarding any barebox stuff to be
directed at my pengutronix inbox.
But if it really bothers you I'll change the header for the next
revision.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 0/5] Rework current Tegra support
2013-03-01 9:22 [PATCH 0/7] Rework current Tegra support Lucas Stach
` (6 preceding siblings ...)
2013-03-01 9:22 ` [PATCH 7/7] tegra: add power management controller driver Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-07 10:33 ` [PATCH v2 1/5] tegra: pull in iomap.h from the Linux kernel Lucas Stach
` (4 more replies)
7 siblings, 5 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
This patchset converts the current ad-hoc implementation within the
Tegra arch into proper barebox drivers. It slightly enhances
functionality, but mostly this is a cleanup to provide a good base
for further work.
V2 incorporates the review feedback I got so far. Mostly avoiding
renaming iomap.h and leaving debug_ll as is.
Lucas Stach (5):
tegra: pull in iomap.h from the Linux kernel
tegra: switch to ARMv7 cpu type
tegra: add driver for the clock and reset module
tegra: add proper timer driver
tegra: add power management controller driver
arch/arm/Kconfig | 4 +-
arch/arm/mach-tegra/Makefile | 6 +-
arch/arm/mach-tegra/clock.c | 56 -------------
arch/arm/mach-tegra/include/mach/clkdev.h | 7 ++
arch/arm/mach-tegra/include/mach/iomap.h | 64 +++++----------
arch/arm/mach-tegra/reset.c | 39 ---------
arch/arm/mach-tegra/tegra20-car.c | 126 ++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20-pmc.c | 89 +++++++++++++++++++++
arch/arm/mach-tegra/tegra20-timer.c | 120 ++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 38 +++++++++
10 files changed, 406 insertions(+), 143 deletions(-)
delete mode 100644 arch/arm/mach-tegra/clock.c
create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
delete mode 100644 arch/arm/mach-tegra/reset.c
create mode 100644 arch/arm/mach-tegra/tegra20-car.c
create mode 100644 arch/arm/mach-tegra/tegra20-pmc.c
create mode 100644 arch/arm/mach-tegra/tegra20-timer.c
create mode 100644 arch/arm/mach-tegra/tegra20.c
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* [PATCH v2 1/5] tegra: pull in iomap.h from the Linux kernel
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-07 10:33 ` [PATCH v2 2/5] tegra: switch to ARMv7 cpu type Lucas Stach
` (3 subsequent siblings)
4 siblings, 0 replies; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
This updates iomap.h to the latest Linux code.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/include/mach/iomap.h | 64 ++++++++++----------------------
1 file changed, 19 insertions(+), 45 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index ba478e7..6ca6504 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -62,47 +62,35 @@
#define TEGRA_RES_SEMA_BASE 0x60001000
#define TEGRA_RES_SEMA_SIZE SZ_4K
-#define TEGRA_HDMI_BASE 0x54280000
-#define TEGRA_HDMI_SIZE SZ_256K
-
-#define TEGRA_GART_BASE 0x58000000
-#define TEGRA_GART_SIZE SZ_32M
-
-#define TEGRA_RES_SEMA_BASE 0x60001000
-#define TEGRA_RES_SEMA_SIZE SZ_4K
-
-#define TEGRA_ARB_SEMA_BASE 0x60002000
-#define TEGRA_ARB_SEMA_SIZE SZ_4K
-
#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE 64
-
-#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
-#define TEGRA_ARBGNT_ICTLR_SIZE 192
+#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE 64
+#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE 64
+#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZE 64
+#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
#define TEGRA_TMR1_BASE 0x60005000
-#define TEGRA_TMR1_SIZE 8
+#define TEGRA_TMR1_SIZE SZ_8
#define TEGRA_TMR2_BASE 0x60005008
-#define TEGRA_TMR2_SIZE 8
+#define TEGRA_TMR2_SIZE SZ_8
#define TEGRA_TMRUS_BASE 0x60005010
-#define TEGRA_TMRUS_SIZE 64
+#define TEGRA_TMRUS_SIZE SZ_64
#define TEGRA_TMR3_BASE 0x60005050
-#define TEGRA_TMR3_SIZE 8
+#define TEGRA_TMR3_SIZE SZ_8
#define TEGRA_TMR4_BASE 0x60005058
-#define TEGRA_TMR4_SIZE 8
+#define TEGRA_TMR4_SIZE SZ_8
#define TEGRA_CLK_RESET_BASE 0x60006000
#define TEGRA_CLK_RESET_SIZE SZ_4K
@@ -125,17 +113,17 @@
#define TEGRA_AHB_GIZMO_BASE 0x6000C004
#define TEGRA_AHB_GIZMO_SIZE 0x10C
+#define TEGRA_SB_BASE 0x6000C200
+#define TEGRA_SB_SIZE 256
+
#define TEGRA_STATMON_BASE 0x6000C400
#define TEGRA_STATMON_SIZE SZ_1K
#define TEGRA_GPIO_BASE 0x6000D000
#define TEGRA_GPIO_SIZE SZ_4K
-#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
-#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
-
-#define TEGRA_VDE_BASE 0x6001A000
-#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256)
+#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
#define TEGRA_APB_MISC_BASE 0x70000000
#define TEGRA_APB_MISC_SIZE SZ_4K
@@ -156,10 +144,10 @@
#define TEGRA_I2S2_SIZE SZ_256
#define TEGRA_UARTA_BASE 0x70006000
-#define TEGRA_UARTA_SIZE 64
+#define TEGRA_UARTA_SIZE SZ_64
#define TEGRA_UARTB_BASE 0x70006040
-#define TEGRA_UARTB_SIZE 64
+#define TEGRA_UARTB_SIZE SZ_64
#define TEGRA_UARTC_BASE 0x70006200
#define TEGRA_UARTC_SIZE SZ_256
@@ -275,18 +263,4 @@
#define TEGRA_SDMMC4_BASE 0xC8000600
#define TEGRA_SDMMC4_SIZE SZ_512
-#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
-# define TEGRA_DEBUG_UART_BASE 0
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
-#endif
-
#endif
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
2013-03-07 10:33 ` [PATCH v2 1/5] tegra: pull in iomap.h from the Linux kernel Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-08 6:03 ` Antony Pavlov
2013-03-07 10:33 ` [PATCH v2 3/5] tegra: add driver for the clock and reset module Lucas Stach
` (2 subsequent siblings)
4 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
Main barebox is running on the A9 cluster. Use the correct ISA.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7ac134e..5dbf74d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -125,7 +125,7 @@ config ARCH_VEXPRESS
config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
- select CPU_ARM926T
+ select CPU_V7
select HAS_DEBUG_LL
endchoice
--
1.8.1.2
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-07 10:33 ` [PATCH v2 2/5] tegra: switch to ARMv7 cpu type Lucas Stach
@ 2013-03-08 6:03 ` Antony Pavlov
2013-03-08 13:17 ` Lucas Stach
2013-03-08 14:32 ` Sascha Hauer
0 siblings, 2 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-08 6:03 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
Hi!
This commit breaks usb ethernet card on my board.
toshiba ac100> / usb
USB: scanning bus for devices...
Bus 001 Device 003: ID 0bdb:190a F3307
Bus 001 Device 004: ID 0bda:58f2 USB Camera
Bus 001 Device 005: ID 2001:3c05 DUB-E100
mdio_bus: miibus0: probed
eth0: got preset MAC address: 1C:7E:E5:0F:E1:14
Bus 001 Device 002: ID 0424:2513
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
5 USB Device(s) found
toshiba ac100> / dhcp
100Mbps full duplex link detected
dhcp failed: error 1
dhcp: error 1
toshiba ac100>
The next branch with Sascha's 'usb: ehci: initialize ehci_data' patch
works fine.
On 7 March 2013 14:33, Lucas Stach <dev@lynxeye.de> wrote:
> Main barebox is running on the A9 cluster. Use the correct ISA.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 7ac134e..5dbf74d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -125,7 +125,7 @@ config ARCH_VEXPRESS
>
> config ARCH_TEGRA
> bool "Nvidia Tegra-based boards"
> - select CPU_ARM926T
> + select CPU_V7
> select HAS_DEBUG_LL
>
> endchoice
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-08 6:03 ` Antony Pavlov
@ 2013-03-08 13:17 ` Lucas Stach
2013-03-08 16:56 ` Antony Pavlov
2013-03-08 14:32 ` Sascha Hauer
1 sibling, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-08 13:17 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Am Freitag, den 08.03.2013, 10:03 +0400 schrieb Antony Pavlov:
> Hi!
>
> This commit breaks usb ethernet card on my board.
>
If you are using a GCC >= 4.7 this is most likely the problem that GCC
now produces hardware unaligned access instructions on ARMv7 by default.
Unfortunately the EHCI spec has placed one of the registers at an
unaligned offset. Barebox traps the processor when hitting an unaligned
access in hardware.
Thanks for the heads up, I'll make sure we resolve this problem before
this patchset goes in.
Regards,
Lucas
_______________________________________________
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-08 13:17 ` Lucas Stach
@ 2013-03-08 16:56 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-08 16:56 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 8 March 2013 17:17, Lucas Stach <dev@lynxeye.de> wrote:
> Am Freitag, den 08.03.2013, 10:03 +0400 schrieb Antony Pavlov:
>> Hi!
>>
>> This commit breaks usb ethernet card on my board.
>>
> If you are using a GCC >= 4.7 this is most likely the problem that GCC
> now produces hardware unaligned access instructions on ARMv7 by default.
I'm using GCC 4.4.6.
> Unfortunately the EHCI spec has placed one of the registers at an
> unaligned offset. Barebox traps the processor when hitting an unaligned
> access in hardware.
>
> Thanks for the heads up, I'll make sure we resolve this problem before
> this patchset goes in.
>
> Regards,
> Lucas
>
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-08 6:03 ` Antony Pavlov
2013-03-08 13:17 ` Lucas Stach
@ 2013-03-08 14:32 ` Sascha Hauer
2013-03-08 17:15 ` Antony Pavlov
1 sibling, 1 reply; 41+ messages in thread
From: Sascha Hauer @ 2013-03-08 14:32 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Hi Antony,
On Fri, Mar 08, 2013 at 10:03:19AM +0400, Antony Pavlov wrote:
> Hi!
>
> This commit breaks usb ethernet card on my board.
>
> toshiba ac100> / usb
> USB: scanning bus for devices...
> Bus 001 Device 003: ID 0bdb:190a F3307
> Bus 001 Device 004: ID 0bda:58f2 USB Camera
> Bus 001 Device 005: ID 2001:3c05 DUB-E100
> mdio_bus: miibus0: probed
> eth0: got preset MAC address: 1C:7E:E5:0F:E1:14
> Bus 001 Device 002: ID 0424:2513
> Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
> 5 USB Device(s) found
> toshiba ac100> / dhcp
> 100Mbps full duplex link detected
> dhcp failed: error 1
> dhcp: error 1
> toshiba ac100>
Could you try the following?
Sascha
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index 9d9b854..c631815 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -22,7 +22,7 @@ static inline void arm_cpu_lowlevel_init(void)
#if __LINUX_ARM_ARCH__ >= 6
r |= CR_U;
- r &= CR_A;
+ r &= ~CR_A;
#else
r |= CR_A;
#endif
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v2 2/5] tegra: switch to ARMv7 cpu type
2013-03-08 14:32 ` Sascha Hauer
@ 2013-03-08 17:15 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-08 17:15 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 8 March 2013 18:32, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Antony,
>
> On Fri, Mar 08, 2013 at 10:03:19AM +0400, Antony Pavlov wrote:
>> Hi!
>>
>> This commit breaks usb ethernet card on my board.
>>
>> toshiba ac100> / usb
>> USB: scanning bus for devices...
>> Bus 001 Device 003: ID 0bdb:190a F3307
>> Bus 001 Device 004: ID 0bda:58f2 USB Camera
>> Bus 001 Device 005: ID 2001:3c05 DUB-E100
>> mdio_bus: miibus0: probed
>> eth0: got preset MAC address: 1C:7E:E5:0F:E1:14
>> Bus 001 Device 002: ID 0424:2513
>> Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
>> 5 USB Device(s) found
>> toshiba ac100> / dhcp
>> 100Mbps full duplex link detected
>> dhcp failed: error 1
>> dhcp: error 1
>> toshiba ac100>
>
> Could you try the following?
>
Alas! This patch did't help.
> diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
> index 9d9b854..c631815 100644
> --- a/arch/arm/include/asm/barebox-arm-head.h
> +++ b/arch/arm/include/asm/barebox-arm-head.h
> @@ -22,7 +22,7 @@ static inline void arm_cpu_lowlevel_init(void)
>
> #if __LINUX_ARM_ARCH__ >= 6
> r |= CR_U;
> - r &= CR_A;
> + r &= ~CR_A;
> #else
> r |= CR_A;
> #endif
>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 3/5] tegra: add driver for the clock and reset module
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
2013-03-07 10:33 ` [PATCH v2 1/5] tegra: pull in iomap.h from the Linux kernel Lucas Stach
2013-03-07 10:33 ` [PATCH v2 2/5] tegra: switch to ARMv7 cpu type Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-10 7:41 ` Antony Pavlov
2013-03-07 10:33 ` [PATCH v2 4/5] tegra: add proper timer driver Lucas Stach
2013-03-07 10:33 ` [PATCH v2 5/5] tegra: add power management controller driver Lucas Stach
4 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
Only a basic set of clocks is supported as of now.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/Kconfig | 2 +
arch/arm/mach-tegra/Makefile | 2 +
arch/arm/mach-tegra/include/mach/clkdev.h | 7 ++
arch/arm/mach-tegra/tegra20-car.c | 121 ++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 30 ++++++++
5 files changed, 162 insertions(+)
create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
create mode 100644 arch/arm/mach-tegra/tegra20-car.c
create mode 100644 arch/arm/mach-tegra/tegra20.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5dbf74d..9724494 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -127,6 +127,8 @@ config ARCH_TEGRA
bool "Nvidia Tegra-based boards"
select CPU_V7
select HAS_DEBUG_LL
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
endchoice
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 11915e5..3391528 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,2 +1,4 @@
obj-y += clock.o
obj-y += reset.o
+obj-y += tegra20.o
+obj-y += tegra20-car.o
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
new file mode 100644
index 0000000..eec3cc3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-car.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 clock and reset (CAR) controller
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <mach/iomap.h>
+
+/* Register definitions */
+#define OSC_CTRL 0x50
+#define OSC_CTRL_OSC_FREQ_SHIFT 30
+#define OSC_CTRL_OSC_FREQ_MASK (3 << OSC_CTRL_OSC_FREQ_SHIFT)
+#define OSC_CTRL_PLL_REF_DIV_SHIFT 28
+#define OSC_CTRL_PLL_REF_DIV_MASK (3 << OSC_CTRL_PLL_REF_DIV_SHIFT)
+
+static void __iomem *car_base;
+
+enum tegra20_clks {
+ cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
+ ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
+ gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
+ kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
+ dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
+ usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
+ pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
+ iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
+ uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
+ osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
+ pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
+ pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
+ pll_x, audio, pll_ref, twd, clk_max,
+};
+
+static struct clk *clks[clk_max];
+
+static unsigned long get_osc_frequency(void)
+{
+ u32 osc_ctrl = readl(car_base + OSC_CTRL);
+
+ switch ((osc_ctrl & OSC_CTRL_OSC_FREQ_MASK) >> OSC_CTRL_OSC_FREQ_SHIFT)
+ {
+ case 0:
+ return 13000000;
+ case 1:
+ return 19200000;
+ case 2:
+ return 12000000;
+ case 3:
+ return 26000000;
+ default:
+ return 0;
+ }
+}
+
+static unsigned int get_pll_ref_div(void)
+{
+ u32 osc_ctrl = readl(car_base + OSC_CTRL);
+
+ return 1U << ((osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK) >>
+ OSC_CTRL_PLL_REF_DIV_SHIFT);
+}
+
+static int tegra20_car_probe(struct device_d *dev)
+{
+ car_base = dev_request_mem_region(dev, 0);
+ if (!car_base)
+ return -EBUSY;
+
+ /* primary clocks */
+ clks[clk_m] = clk_fixed("clk_m", get_osc_frequency());
+ clks[clk_32k] = clk_fixed("clk_32k", 32768);
+
+ clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
+ get_pll_ref_div());
+
+ /* derived clocks */
+ /* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
+ clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_car_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-car",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_car_driver = {
+ .probe = tegra20_car_probe,
+ .name = "tegra20-car",
+ .of_compatible = DRV_OF_COMPAT(tegra20_car_dt_ids),
+};
+
+static int tegra20_car_init(void)
+{
+ return platform_driver_register(&tegra20_car_driver);
+}
+postcore_initcall(tegra20_car_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
new file mode 100644
index 0000000..3831f1b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/iomap.h>
+
+static int tegra20_init(void)
+{
+ add_generic_device("tegra20-car", DEVICE_ID_SINGLE, NULL,
+ TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
+ IORESOURCE_MEM, NULL);
+
+ return 0;
+}
+
+postcore_initcall(tegra20_init);
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v2 3/5] tegra: add driver for the clock and reset module
2013-03-07 10:33 ` [PATCH v2 3/5] tegra: add driver for the clock and reset module Lucas Stach
@ 2013-03-10 7:41 ` Antony Pavlov
2013-03-10 9:53 ` Sascha Hauer
0 siblings, 1 reply; 41+ messages in thread
From: Antony Pavlov @ 2013-03-10 7:41 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 7 March 2013 14:33, Lucas Stach <dev@lynxeye.de> wrote:
> Only a basic set of clocks is supported as of now.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/Kconfig | 2 +
> arch/arm/mach-tegra/Makefile | 2 +
> arch/arm/mach-tegra/include/mach/clkdev.h | 7 ++
> arch/arm/mach-tegra/tegra20-car.c | 121 ++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 30 ++++++++
> 5 files changed, 162 insertions(+)
> create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-tegra/tegra20-car.c
> create mode 100644 arch/arm/mach-tegra/tegra20.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5dbf74d..9724494 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -127,6 +127,8 @@ config ARCH_TEGRA
> bool "Nvidia Tegra-based boards"
> select CPU_V7
> select HAS_DEBUG_LL
> + select COMMON_CLK
> + select CLKDEV_LOOKUP
>
> endchoice
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 11915e5..3391528 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,2 +1,4 @@
> obj-y += clock.o
> obj-y += reset.o
> +obj-y += tegra20.o
> +obj-y += tegra20-car.o
> diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
> new file mode 100644
> index 0000000..04b37a8
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/clkdev.h
> @@ -0,0 +1,7 @@
> +#ifndef __ASM_MACH_CLKDEV_H
> +#define __ASM_MACH_CLKDEV_H
> +
> +#define __clk_get(clk) ({ 1; })
> +#define __clk_put(clk) do { } while (0)
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
> new file mode 100644
> index 0000000..eec3cc3
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-car.c
> @@ -0,0 +1,121 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 clock and reset (CAR) controller
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <mach/iomap.h>
> +
> +/* Register definitions */
> +#define OSC_CTRL 0x50
> +#define OSC_CTRL_OSC_FREQ_SHIFT 30
> +#define OSC_CTRL_OSC_FREQ_MASK (3 << OSC_CTRL_OSC_FREQ_SHIFT)
> +#define OSC_CTRL_PLL_REF_DIV_SHIFT 28
> +#define OSC_CTRL_PLL_REF_DIV_MASK (3 << OSC_CTRL_PLL_REF_DIV_SHIFT)
> +
> +static void __iomem *car_base;
> +
> +enum tegra20_clks {
> + cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
> + ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
> + gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
> + kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
> + dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
> + usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
> + pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
> + iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
> + uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
> + osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
> + pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
> + pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
> + pll_x, audio, pll_ref, twd, clk_max,
> +};
> +
Please remove unused constants or register appropriate clocks.
> +static struct clk *clks[clk_max];
> +
> +static unsigned long get_osc_frequency(void)
> +{
> + u32 osc_ctrl = readl(car_base + OSC_CTRL);
> +
> + switch ((osc_ctrl & OSC_CTRL_OSC_FREQ_MASK) >> OSC_CTRL_OSC_FREQ_SHIFT)
> + {
> + case 0:
> + return 13000000;
> + case 1:
> + return 19200000;
> + case 2:
> + return 12000000;
> + case 3:
> + return 26000000;
> + default:
> + return 0;
> + }
> +}
> +
> +static unsigned int get_pll_ref_div(void)
> +{
> + u32 osc_ctrl = readl(car_base + OSC_CTRL);
> +
> + return 1U << ((osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK) >>
> + OSC_CTRL_PLL_REF_DIV_SHIFT);
> +}
> +
> +static int tegra20_car_probe(struct device_d *dev)
> +{
Please check car_base befor use, e.g. see your tegra20_timer_probe() function.
> + car_base = dev_request_mem_region(dev, 0);
> + if (!car_base)
> + return -EBUSY;
> +
> + /* primary clocks */
> + clks[clk_m] = clk_fixed("clk_m", get_osc_frequency());
> + clks[clk_32k] = clk_fixed("clk_32k", 32768);
> +
> + clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
> + get_pll_ref_div());
> +
> + /* derived clocks */
> + /* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
> + clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id tegra20_car_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-car",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d tegra20_car_driver = {
> + .probe = tegra20_car_probe,
> + .name = "tegra20-car",
> + .of_compatible = DRV_OF_COMPAT(tegra20_car_dt_ids),
> +};
> +
> +static int tegra20_car_init(void)
> +{
> + return platform_driver_register(&tegra20_car_driver);
> +}
> +postcore_initcall(tegra20_car_init);
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> new file mode 100644
> index 0000000..3831f1b
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <mach/iomap.h>
> +
> +static int tegra20_init(void)
> +{
> + add_generic_device("tegra20-car", DEVICE_ID_SINGLE, NULL,
> + TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
> + IORESOURCE_MEM, NULL);
> +
> + return 0;
> +}
> +
> +postcore_initcall(tegra20_init);
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v2 3/5] tegra: add driver for the clock and reset module
2013-03-10 7:41 ` Antony Pavlov
@ 2013-03-10 9:53 ` Sascha Hauer
0 siblings, 0 replies; 41+ messages in thread
From: Sascha Hauer @ 2013-03-10 9:53 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
On Sun, Mar 10, 2013 at 11:41:44AM +0400, Antony Pavlov wrote:
> > +static void __iomem *car_base;
> > +
> > +enum tegra20_clks {
> > + cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
> > + ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
> > + gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
> > + kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
> > + dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
> > + usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
> > + pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
> > + iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
> > + uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
> > + osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
> > + pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
> > + pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
> > + pll_x, audio, pll_ref, twd, clk_max,
> > +};
> > +
> Please remove unused constants or register appropriate clocks.
Maybe it makes sense to keep them. When they are in sync with the
devicetree it means we could derive clocks from the devicetree should
we ever want to. However, we could also do this later when we really
need it, so I have no objection in either direction.
Sascha
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 4/5] tegra: add proper timer driver
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
` (2 preceding siblings ...)
2013-03-07 10:33 ` [PATCH v2 3/5] tegra: add driver for the clock and reset module Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-10 7:12 ` Antony Pavlov
2013-03-07 10:33 ` [PATCH v2 5/5] tegra: add power management controller driver Lucas Stach
4 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
Replace the ad-hoc clocksource implementation with a proper driver for
the Tegra 20 timer. This driver is able to do the required hardware
initialisation itself.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/clock.c | 56 -----------------
arch/arm/mach-tegra/tegra20-car.c | 5 ++
arch/arm/mach-tegra/tegra20-timer.c | 120 ++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 4 ++
5 files changed, 130 insertions(+), 57 deletions(-)
delete mode 100644 arch/arm/mach-tegra/clock.c
create mode 100644 arch/arm/mach-tegra/tegra20-timer.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 3391528..6aa219c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,4 +1,4 @@
-obj-y += clock.o
obj-y += reset.o
obj-y += tegra20.o
obj-y += tegra20-car.o
+obj-y += tegra20-timer.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
deleted file mode 100644
index 82065ee..0000000
--- a/arch/arm/mach-tegra/clock.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Clocksource based on Tegra internal timer
- */
-
-#include <common.h>
-#include <clock.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <init.h>
-#include <asm/io.h>
-#include <mach/iomap.h>
-
-static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
-
-#define timer_writel(value, reg) \
- __raw_writel(value, (u32)timer_reg_base + (reg))
-#define timer_readl(reg) \
- __raw_readl((u32)timer_reg_base + (reg))
-
-static uint64_t tegra_clocksource_read(void)
-{
- return timer_readl(0x10);
-}
-
-static struct clocksource cs = {
- .read = tegra_clocksource_read,
- .mask = 0xffffffff,
-};
-
-/* FIXME: here we have no initialization. All initialization made by U-Boot */
-static int clocksource_init(void)
-{
- cs.mult = clocksource_hz2mult(1000000, cs.shift);
- init_clock(&cs);
-
- return 0;
-}
-core_initcall(clocksource_init);
diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
index eec3cc3..3ac389f 100644
--- a/arch/arm/mach-tegra/tegra20-car.c
+++ b/arch/arm/mach-tegra/tegra20-car.c
@@ -23,6 +23,7 @@
#include <init.h>
#include <io.h>
#include <linux/clk.h>
+#include <linux/clkdev.h>
#include <linux/err.h>
#include <mach/iomap.h>
@@ -97,6 +98,10 @@ static int tegra20_car_probe(struct device_d *dev)
/* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
+
+ /* device to clock links */
+ clkdev_add_physbase(clks[timer], TEGRA_TMR1_BASE, NULL);
+
return 0;
}
diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c
new file mode 100644
index 0000000..6c1d302
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-timer.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 timer, which exposes a clocksource.
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+
+/* register definitions */
+#define TIMERUS_CNTR_1US 0x10
+#define TIMERUS_USEC_CFG 0x14
+
+static void __iomem *timer_base;
+
+static uint64_t tegra20_timer_cs_read(void)
+{
+ return readl(timer_base + TIMERUS_CNTR_1US);
+}
+
+static struct clocksource cs = {
+ .read = tegra20_timer_cs_read,
+ .mask = CLOCKSOURCE_MASK(32),
+};
+
+static int tegra20_timer_probe(struct device_d *dev)
+{
+ struct clk *timer_clk;
+ unsigned long rate;
+ u32 reg;
+
+ /* use only one timer */
+ if (timer_base)
+ return -EBUSY;
+
+ timer_base = dev_request_mem_region(dev, 0);
+ if (!timer_base) {
+ dev_err(dev, "could not get memory region\n");
+ return -ENODEV;
+ }
+
+ timer_clk = clk_get(dev, NULL);
+ if (!timer_clk) {
+ dev_err(dev, "could not get clock\n");
+ return -ENODEV;
+ }
+
+ clk_enable(timer_clk);
+
+ /*
+ * calibrate timer to run at 1MHz
+ * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
+ * representing the divisor and bits [8:15] representing the dividend
+ * each in n+1 form.
+ */
+ rate = clk_get_rate(timer_clk);
+ switch (rate) {
+ case 12000000:
+ reg = 0x000b;
+ break;
+ case 13000000:
+ reg = 0x000c;
+ break;
+ case 19200000:
+ reg = 0x045f;
+ break;
+ case 26000000:
+ reg = 0x0019;
+ break;
+ default:
+ reg = 0;
+ dev_warn(dev, "unknown timer clock rate\n");
+ break;
+ }
+ writel(reg, timer_base + TIMERUS_USEC_CFG);
+
+ cs.mult = clocksource_hz2mult(1000000, cs.shift);
+ init_clock(&cs);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-timer",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_timer_driver = {
+ .probe = tegra20_timer_probe,
+ .name = "tegra20-timer",
+ .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
+};
+
+static int tegra20_timer_init(void)
+{
+ return platform_driver_register(&tegra20_timer_driver);
+}
+
+coredevice_initcall(tegra20_timer_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index 3831f1b..c1b3f78 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -24,6 +24,10 @@ static int tegra20_init(void)
TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
IORESOURCE_MEM, NULL);
+ add_generic_device("tegra20-timer", DEVICE_ID_SINGLE, NULL,
+ TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
+ IORESOURCE_MEM, NULL);
+
return 0;
}
--
1.8.1.2
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v2 4/5] tegra: add proper timer driver
2013-03-07 10:33 ` [PATCH v2 4/5] tegra: add proper timer driver Lucas Stach
@ 2013-03-10 7:12 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-10 7:12 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 7 March 2013 14:33, Lucas Stach <dev@lynxeye.de> wrote:
> Replace the ad-hoc clocksource implementation with a proper driver for
> the Tegra 20 timer. This driver is able to do the required hardware
> initialisation itself.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/mach-tegra/Makefile | 2 +-
> arch/arm/mach-tegra/clock.c | 56 -----------------
> arch/arm/mach-tegra/tegra20-car.c | 5 ++
> arch/arm/mach-tegra/tegra20-timer.c | 120 ++++++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 4 ++
> 5 files changed, 130 insertions(+), 57 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/clock.c
> create mode 100644 arch/arm/mach-tegra/tegra20-timer.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 3391528..6aa219c 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,4 +1,4 @@
> -obj-y += clock.o
> obj-y += reset.o
> obj-y += tegra20.o
> obj-y += tegra20-car.o
> +obj-y += tegra20-timer.o
> diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
> deleted file mode 100644
> index 82065ee..0000000
> --- a/arch/arm/mach-tegra/clock.c
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -/*
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -/**
> - * @file
> - * @brief Clocksource based on Tegra internal timer
> - */
> -
> -#include <common.h>
> -#include <clock.h>
> -#include <linux/list.h>
> -#include <linux/clk.h>
> -#include <init.h>
> -#include <asm/io.h>
> -#include <mach/iomap.h>
> -
> -static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
> -
> -#define timer_writel(value, reg) \
> - __raw_writel(value, (u32)timer_reg_base + (reg))
> -#define timer_readl(reg) \
> - __raw_readl((u32)timer_reg_base + (reg))
> -
> -static uint64_t tegra_clocksource_read(void)
> -{
> - return timer_readl(0x10);
> -}
> -
> -static struct clocksource cs = {
> - .read = tegra_clocksource_read,
> - .mask = 0xffffffff,
> -};
> -
> -/* FIXME: here we have no initialization. All initialization made by U-Boot */
> -static int clocksource_init(void)
> -{
> - cs.mult = clocksource_hz2mult(1000000, cs.shift);
> - init_clock(&cs);
> -
> - return 0;
> -}
> -core_initcall(clocksource_init);
> diff --git a/arch/arm/mach-tegra/tegra20-car.c b/arch/arm/mach-tegra/tegra20-car.c
> index eec3cc3..3ac389f 100644
> --- a/arch/arm/mach-tegra/tegra20-car.c
> +++ b/arch/arm/mach-tegra/tegra20-car.c
> @@ -23,6 +23,7 @@
> #include <init.h>
> #include <io.h>
> #include <linux/clk.h>
> +#include <linux/clkdev.h>
> #include <linux/err.h>
> #include <mach/iomap.h>
>
> @@ -97,6 +98,10 @@ static int tegra20_car_probe(struct device_d *dev)
> /* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
> clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
>
> +
Please no extra empty line here.
> + /* device to clock links */
> + clkdev_add_physbase(clks[timer], TEGRA_TMR1_BASE, NULL);
> +
> return 0;
> }
>
> diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c
> new file mode 100644
> index 0000000..6c1d302
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-timer.c
> @@ -0,0 +1,120 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 timer, which exposes a clocksource.
> + */
> +
> +#include <common.h>
> +#include <clock.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/clk.h>
> +
> +/* register definitions */
> +#define TIMERUS_CNTR_1US 0x10
> +#define TIMERUS_USEC_CFG 0x14
> +
> +static void __iomem *timer_base;
> +
> +static uint64_t tegra20_timer_cs_read(void)
> +{
> + return readl(timer_base + TIMERUS_CNTR_1US);
> +}
> +
> +static struct clocksource cs = {
> + .read = tegra20_timer_cs_read,
> + .mask = CLOCKSOURCE_MASK(32),
> +};
> +
> +static int tegra20_timer_probe(struct device_d *dev)
> +{
> + struct clk *timer_clk;
> + unsigned long rate;
> + u32 reg;
> +
> + /* use only one timer */
> + if (timer_base)
> + return -EBUSY;
> +
> + timer_base = dev_request_mem_region(dev, 0);
> + if (!timer_base) {
> + dev_err(dev, "could not get memory region\n");
> + return -ENODEV;
> + }
> +
> + timer_clk = clk_get(dev, NULL);
> + if (!timer_clk) {
> + dev_err(dev, "could not get clock\n");
> + return -ENODEV;
> + }
> +
> + clk_enable(timer_clk);
> +
> + /*
> + * calibrate timer to run at 1MHz
> + * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
> + * representing the divisor and bits [8:15] representing the dividend
> + * each in n+1 form.
> + */
> + rate = clk_get_rate(timer_clk);
> + switch (rate) {
> + case 12000000:
> + reg = 0x000b;
> + break;
> + case 13000000:
> + reg = 0x000c;
> + break;
> + case 19200000:
> + reg = 0x045f;
> + break;
> + case 26000000:
> + reg = 0x0019;
> + break;
> + default:
> + reg = 0;
> + dev_warn(dev, "unknown timer clock rate\n");
> + break;
> + }
> + writel(reg, timer_base + TIMERUS_USEC_CFG);
> +
> + cs.mult = clocksource_hz2mult(1000000, cs.shift);
> + init_clock(&cs);
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-timer",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d tegra20_timer_driver = {
> + .probe = tegra20_timer_probe,
> + .name = "tegra20-timer",
> + .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids),
> +};
> +
> +static int tegra20_timer_init(void)
> +{
> + return platform_driver_register(&tegra20_timer_driver);
> +}
> +
In barebox there is a tradition to skip emty line before *_initcall.
Try
grep -B1 -RHn "coredevice_initcall" arch/
> +coredevice_initcall(tegra20_timer_init);
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> index 3831f1b..c1b3f78 100644
> --- a/arch/arm/mach-tegra/tegra20.c
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -24,6 +24,10 @@ static int tegra20_init(void)
> TEGRA_CLK_RESET_BASE, TEGRA_CLK_RESET_SIZE,
> IORESOURCE_MEM, NULL);
>
> + add_generic_device("tegra20-timer", DEVICE_ID_SINGLE, NULL,
> + TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
> + IORESOURCE_MEM, NULL);
> +
> return 0;
> }
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v2 5/5] tegra: add power management controller driver
2013-03-07 10:33 ` [PATCH v2 0/5] Rework current Tegra support Lucas Stach
` (3 preceding siblings ...)
2013-03-07 10:33 ` [PATCH v2 4/5] tegra: add proper timer driver Lucas Stach
@ 2013-03-07 10:33 ` Lucas Stach
2013-03-10 8:19 ` Antony Pavlov
4 siblings, 1 reply; 41+ messages in thread
From: Lucas Stach @ 2013-03-07 10:33 UTC (permalink / raw)
To: barebox
Currently only implements system wide reset functionality.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/reset.c | 39 -----------------
arch/arm/mach-tegra/tegra20-pmc.c | 89 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20.c | 4 ++
4 files changed, 94 insertions(+), 40 deletions(-)
delete mode 100644 arch/arm/mach-tegra/reset.c
create mode 100644 arch/arm/mach-tegra/tegra20-pmc.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6aa219c..bcc0cd4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,4 +1,4 @@
-obj-y += reset.o
obj-y += tegra20.o
obj-y += tegra20-car.o
+obj-y += tegra20-pmc.o
obj-y += tegra20-timer.o
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
deleted file mode 100644
index 91f9b3b..0000000
--- a/arch/arm/mach-tegra/reset.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/**
- * @file
- * @brief Resetting an malta board
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <mach/iomap.h>
-
-#define PRM_RSTCTRL TEGRA_PMC_BASE
-
-void __noreturn reset_cpu(ulong addr)
-{
- int rstctrl;
-
- rstctrl = __raw_readl((char *)PRM_RSTCTRL);
- rstctrl |= 0x10;
- __raw_writel(rstctrl, (char *)PRM_RSTCTRL);
-
- unreachable();
-}
-EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
new file mode 100644
index 0000000..ed765f5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20-pmc.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file
+ * @brief Device driver for the Tegra 20 power management controller.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+
+/* register definitions */
+#define PMC_CNTRL 0x00
+#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
+#define PMC_CNTRL_INTR_POLARITY (1 << 17)
+#define PMC_CNTRL_CPUPWRREQ_OE (1 << 16)
+#define PMC_CNTRL_CPUPWRREQ_POLARITY (1 << 15)
+#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
+#define PMC_CNTRL_AOINIT (1 << 13)
+#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
+#define PMC_CNTRL_SYSCLK_OE (1 << 11)
+#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
+#define PMC_CNTRL_PWRREQ_OE (1 << 9)
+#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
+#define PMC_CNTRL_BLINK_EN (1 << 7)
+#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
+#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
+#define PMC_CNTRL_MAIN_RST (1 << 4)
+#define PMC_CNTRL_KBC_RST (1 << 3)
+#define PMC_CNTRL_RTC_RST (1 << 2)
+#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
+#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
+
+static void __iomem *pmc_base;
+
+/* main SoC reset trigger */
+void __noreturn reset_cpu(ulong addr)
+{
+ writel(PMC_CNTRL_MAIN_RST, pmc_base + PMC_CNTRL);
+
+ unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
+
+static int tegra20_pmc_probe(struct device_d *dev)
+{
+ pmc_base = dev_request_mem_region(dev, 0);
+ if (!pmc_base) {
+ dev_err(dev, "could not get memory region\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-pmc",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d tegra20_pmc_driver = {
+ .probe = tegra20_pmc_probe,
+ .name = "tegra20-pmc",
+ .of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
+};
+
+static int tegra20_pmc_init(void)
+{
+ return platform_driver_register(&tegra20_pmc_driver);
+}
+
+coredevice_initcall(tegra20_pmc_init);
diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
index c1b3f78..884671a 100644
--- a/arch/arm/mach-tegra/tegra20.c
+++ b/arch/arm/mach-tegra/tegra20.c
@@ -28,6 +28,10 @@ static int tegra20_init(void)
TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
IORESOURCE_MEM, NULL);
+ add_generic_device("tegra20-pmc", DEVICE_ID_SINGLE, NULL,
+ TEGRA_PMC_BASE, TEGRA_PMC_SIZE,
+ IORESOURCE_MEM, NULL);
+
return 0;
}
--
1.8.1.2
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v2 5/5] tegra: add power management controller driver
2013-03-07 10:33 ` [PATCH v2 5/5] tegra: add power management controller driver Lucas Stach
@ 2013-03-10 8:19 ` Antony Pavlov
0 siblings, 0 replies; 41+ messages in thread
From: Antony Pavlov @ 2013-03-10 8:19 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On 7 March 2013 14:33, Lucas Stach <dev@lynxeye.de> wrote:
> Currently only implements system wide reset functionality.
Please split this patch into two patches, one for reset_cpu()-related
stuff and one for the rest.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> arch/arm/mach-tegra/Makefile | 2 +-
> arch/arm/mach-tegra/reset.c | 39 -----------------
> arch/arm/mach-tegra/tegra20-pmc.c | 89 +++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/tegra20.c | 4 ++
> 4 files changed, 94 insertions(+), 40 deletions(-)
> delete mode 100644 arch/arm/mach-tegra/reset.c
> create mode 100644 arch/arm/mach-tegra/tegra20-pmc.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 6aa219c..bcc0cd4 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -1,4 +1,4 @@
> -obj-y += reset.o
> obj-y += tegra20.o
> obj-y += tegra20-car.o
> +obj-y += tegra20-pmc.o
> obj-y += tegra20-timer.o
> diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
> deleted file mode 100644
> index 91f9b3b..0000000
> --- a/arch/arm/mach-tegra/reset.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -/*
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -/**
> - * @file
> - * @brief Resetting an malta board
> - */
> -
> -#include <common.h>
> -#include <asm/io.h>
> -#include <mach/iomap.h>
> -
> -#define PRM_RSTCTRL TEGRA_PMC_BASE
> -
> -void __noreturn reset_cpu(ulong addr)
> -{
> - int rstctrl;
> -
> - rstctrl = __raw_readl((char *)PRM_RSTCTRL);
> - rstctrl |= 0x10;
> - __raw_writel(rstctrl, (char *)PRM_RSTCTRL);
> -
> - unreachable();
> -}
> -EXPORT_SYMBOL(reset_cpu);
> diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c
> new file mode 100644
> index 0000000..ed765f5
> --- /dev/null
> +++ b/arch/arm/mach-tegra/tegra20-pmc.c
> @@ -0,0 +1,89 @@
> +/*
> + * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/**
> + * @file
> + * @brief Device driver for the Tegra 20 power management controller.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +
> +/* register definitions */
> +#define PMC_CNTRL 0x00
> +#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
> +#define PMC_CNTRL_INTR_POLARITY (1 << 17)
> +#define PMC_CNTRL_CPUPWRREQ_OE (1 << 16)
> +#define PMC_CNTRL_CPUPWRREQ_POLARITY (1 << 15)
> +#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
> +#define PMC_CNTRL_AOINIT (1 << 13)
> +#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
> +#define PMC_CNTRL_SYSCLK_OE (1 << 11)
> +#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
> +#define PMC_CNTRL_PWRREQ_OE (1 << 9)
> +#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
> +#define PMC_CNTRL_BLINK_EN (1 << 7)
> +#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
> +#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
> +#define PMC_CNTRL_MAIN_RST (1 << 4)
> +#define PMC_CNTRL_KBC_RST (1 << 3)
> +#define PMC_CNTRL_RTC_RST (1 << 2)
> +#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
> +#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
> +
> +static void __iomem *pmc_base;
> +
> +/* main SoC reset trigger */
> +void __noreturn reset_cpu(ulong addr)
> +{
> + writel(PMC_CNTRL_MAIN_RST, pmc_base + PMC_CNTRL);
> +
> + unreachable();
> +}
> +EXPORT_SYMBOL(reset_cpu);
> +
> +static int tegra20_pmc_probe(struct device_d *dev)
> +{
> + pmc_base = dev_request_mem_region(dev, 0);
> + if (!pmc_base) {
> + dev_err(dev, "could not get memory region\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-pmc",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d tegra20_pmc_driver = {
> + .probe = tegra20_pmc_probe,
> + .name = "tegra20-pmc",
> + .of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids),
> +};
> +
> +static int tegra20_pmc_init(void)
> +{
> + return platform_driver_register(&tegra20_pmc_driver);
> +}
> +
> +coredevice_initcall(tegra20_pmc_init);
> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c
> index c1b3f78..884671a 100644
> --- a/arch/arm/mach-tegra/tegra20.c
> +++ b/arch/arm/mach-tegra/tegra20.c
> @@ -28,6 +28,10 @@ static int tegra20_init(void)
> TEGRA_TMR1_BASE, TEGRA_TMR1_SIZE,
> IORESOURCE_MEM, NULL);
>
> + add_generic_device("tegra20-pmc", DEVICE_ID_SINGLE, NULL,
> + TEGRA_PMC_BASE, TEGRA_PMC_SIZE,
> + IORESOURCE_MEM, NULL);
> +
> return 0;
> }
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
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