* [PATCH 1/2] ARM: i.MX: Update MX2x iomux definitions @ 2013-04-07 8:48 Alexander Shiyan 2013-04-07 8:48 ` [PATCH 2/2] ARM: i.MX: Update MX51 " Alexander Shiyan 0 siblings, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-07 8:48 UTC (permalink / raw) To: barebox The patch updates MX2x iomux definitions from kernel. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/mach-imx/include/mach/iomux-mx27.h | 6 ------ arch/arm/mach-imx/include/mach/iomux-mx2x.h | 12 ++++++------ 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h index 7d24967..b6e3345 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx27.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h @@ -25,12 +25,6 @@ #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) diff --git a/arch/arm/mach-imx/include/mach/iomux-mx2x.h b/arch/arm/mach-imx/include/mach/iomux-mx2x.h index 2f9560f..15c2e2b 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx2x.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx2x.h @@ -86,12 +86,12 @@ #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -- 1.8.1.5 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-07 8:48 [PATCH 1/2] ARM: i.MX: Update MX2x iomux definitions Alexander Shiyan @ 2013-04-07 8:48 ` Alexander Shiyan 2013-04-09 6:49 ` Sascha Hauer 0 siblings, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-07 8:48 UTC (permalink / raw) To: barebox The patch updates MX51 iomux definitions from kernel. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/mach-imx/include/mach/iomux-mx51.h | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h index 0252d41..2623e7a 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx51.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h @@ -107,11 +107,13 @@ #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) @@ -228,6 +230,7 @@ #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) @@ -256,12 +259,14 @@ #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) @@ -637,7 +642,9 @@ #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) @@ -649,20 +656,20 @@ #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) #define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) #define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) @@ -692,17 +699,17 @@ #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, MX51_PAD_CTRL_5) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) @@ -780,6 +787,8 @@ #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) @@ -788,13 +797,16 @@ #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) @@ -803,11 +815,13 @@ #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ -- 1.8.1.5 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-07 8:48 ` [PATCH 2/2] ARM: i.MX: Update MX51 " Alexander Shiyan @ 2013-04-09 6:49 ` Sascha Hauer 2013-04-09 6:52 ` Re[2]: " Alexander Shiyan 0 siblings, 1 reply; 11+ messages in thread From: Sascha Hauer @ 2013-04-09 6:49 UTC (permalink / raw) To: Alexander Shiyan; +Cc: barebox On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > The patch updates MX51 iomux definitions from kernel. > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> This patch effectively reverts: commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 Author: Eric Bénard <eric@eukrea.com> Date: Thu Sep 6 21:39:30 2012 +0200 i.MX51: unbreak FEC iomux in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced with the kernel but this leads to some changes in the PAD_CTRL of some FEC pins leading to a non working FEC on our cpuimx51 board. This patch set back the PAD_CTRL of the missing pins to the initial value. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> You shouldn't do this. -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re[2]: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 6:49 ` Sascha Hauer @ 2013-04-09 6:52 ` Alexander Shiyan 2013-04-09 7:31 ` Sascha Hauer 0 siblings, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-09 6:52 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > The patch updates MX51 iomux definitions from kernel. > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > This patch effectively reverts: > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > Author: Eric Bénard <eric@eukrea.com> > Date: Thu Sep 6 21:39:30 2012 +0200 > > i.MX51: unbreak FEC iomux > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > with the kernel but this leads to some changes in the PAD_CTRL of some > FEC pins leading to a non working FEC on our cpuimx51 board. > > This patch set back the PAD_CTRL of the missing pins to the initial > value. > > Signed-off-by: Eric Bénard <eric@eukrea.com> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > You shouldn't do this. What about write a patch for the kernel for this? --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 6:52 ` Re[2]: " Alexander Shiyan @ 2013-04-09 7:31 ` Sascha Hauer 2013-04-09 8:01 ` Re[2]: " Alexander Shiyan 0 siblings, 1 reply; 11+ messages in thread From: Sascha Hauer @ 2013-04-09 7:31 UTC (permalink / raw) To: Alexander Shiyan; +Cc: barebox On Tue, Apr 09, 2013 at 10:52:16AM +0400, Alexander Shiyan wrote: > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > The patch updates MX51 iomux definitions from kernel. > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > This patch effectively reverts: > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > Author: Eric Bénard <eric@eukrea.com> > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > i.MX51: unbreak FEC iomux > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > with the kernel but this leads to some changes in the PAD_CTRL of some > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > value. > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > You shouldn't do this. > > What about write a patch for the kernel for this? By the time I applied Erics patch I considered the days of the traditional iomux support in the kernel counted. From that day on we have to maintain our own versions anyway. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re[2]: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 7:31 ` Sascha Hauer @ 2013-04-09 8:01 ` Alexander Shiyan 2013-04-09 8:03 ` Eric Bénard 0 siblings, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-09 8:01 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > This patch effectively reverts: > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > Author: Eric Bénard <eric@eukrea.com> > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > i.MX51: unbreak FEC iomux > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > value. > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > You shouldn't do this. > > > > What about write a patch for the kernel for this? > > By the time I applied Erics patch I considered the days of the > traditional iomux support in the kernel counted. From that day on > we have to maintain our own versions anyway. OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. This will keep iomux-mx51.h file synced. --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 8:01 ` Re[2]: " Alexander Shiyan @ 2013-04-09 8:03 ` Eric Bénard 2013-04-09 8:15 ` Re[2]: " Alexander Shiyan 2013-04-09 15:05 ` Alexander Shiyan 0 siblings, 2 replies; 11+ messages in thread From: Eric Bénard @ 2013-04-09 8:03 UTC (permalink / raw) To: Alexander Shiyan; +Cc: barebox Hi Alexander, Le Tue, 09 Apr 2013 12:01:51 +0400, Alexander Shiyan <shc_work@mail.ru> a écrit : > > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > > > This patch effectively reverts: > > > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > > Author: Eric Bénard <eric@eukrea.com> > > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > > > i.MX51: unbreak FEC iomux > > > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > > value. > > > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > > > You shouldn't do this. > > > > > > What about write a patch for the kernel for this? > > > > By the time I applied Erics patch I considered the days of the > > traditional iomux support in the kernel counted. From that day on > > we have to maintain our own versions anyway. > > OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC > pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. > This will keep iomux-mx51.h file synced. > Fine for me. Do you have a problem with these pads setting so that you need to revert the change ? Eric _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re[2]: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 8:03 ` Eric Bénard @ 2013-04-09 8:15 ` Alexander Shiyan 2013-04-09 15:05 ` Alexander Shiyan 1 sibling, 0 replies; 11+ messages in thread From: Alexander Shiyan @ 2013-04-09 8:15 UTC (permalink / raw) To: Eric B�nard; +Cc: barebox > Le Tue, 09 Apr 2013 12:01:51 +0400, > Alexander Shiyan <shc_work@mail.ru> a écrit : > > > > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > > > > > This patch effectively reverts: > > > > > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > > > Author: Eric Bénard <eric@eukrea.com> > > > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > > > > > i.MX51: unbreak FEC iomux > > > > > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > > > value. > > > > > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > > > > > You shouldn't do this. > > > > > > > > What about write a patch for the kernel for this? > > > > > > By the time I applied Erics patch I considered the days of the > > > traditional iomux support in the kernel counted. From that day on > > > we have to maintain our own versions anyway. > > > > OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC > > pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. > > This will keep iomux-mx51.h file synced. > > > Fine for me. Do you have a problem with these pads setting so that you > need to revert the change ? No problems. Just want to sync this header since it have a few pin definitions that currently is missing in barebox. --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re[2]: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 8:03 ` Eric Bénard 2013-04-09 8:15 ` Re[2]: " Alexander Shiyan @ 2013-04-09 15:05 ` Alexander Shiyan 2013-04-12 10:36 ` Re[3]: " Alexander Shiyan 1 sibling, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-09 15:05 UTC (permalink / raw) To: Eric B�nard; +Cc: barebox > Le Tue, 09 Apr 2013 12:01:51 +0400, > Alexander Shiyan <shc_work@mail.ru> a écrit : > > > > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > > > > > This patch effectively reverts: > > > > > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > > > Author: Eric Bénard <eric@eukrea.com> > > > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > > > > > i.MX51: unbreak FEC iomux > > > > > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > > > value. > > > > > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > > > > > You shouldn't do this. > > > > > > > > What about write a patch for the kernel for this? > > > > > > By the time I applied Erics patch I considered the days of the > > > traditional iomux support in the kernel counted. From that day on > > > we have to maintain our own versions anyway. > > > > OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC > > pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. > > This will keep iomux-mx51.h file synced. > > > Fine for me. Do you have a problem with these pads setting so that you > need to revert the change ? So, below is a temporary fixup. From 47d0d7b9c0355ba31e4c563891b2e9159dc07533 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan <shc_work@mail.ru> Date: Tue, 9 Apr 2013 19:01:40 +0400 Subject: [PATCH] ARM: cpuimx51: Fix PAD_CTRLs for FEC Signed-off-by: Alexander Shiyan <shc_work@mail.ru> --- arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index 5e77f90..523a805 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -55,23 +55,23 @@ static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { MX51_PAD_UART1_RTS__UART1_RTS, MX51_PAD_UART1_CTS__UART1_CTS, /* FEC */ - MX51_PAD_DISP2_DAT1__FEC_RX_ER, + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_CTRL_5), MX51_PAD_DISP2_DAT15__FEC_TDATA0, MX51_PAD_DISP2_DAT6__FEC_TDATA1, MX51_PAD_DISP2_DAT7__FEC_TDATA2, MX51_PAD_DISP2_DAT8__FEC_TDATA3, MX51_PAD_DISP2_DAT9__FEC_TX_EN, - MX51_PAD_DISP2_DAT10__FEC_COL, - MX51_PAD_DISP2_DAT11__FEC_RX_CLK, - MX51_PAD_DISP2_DAT12__FEC_RX_DV, + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT10__FEC_COL, MX51_PAD_CTRL_5), + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT11__FEC_RX_CLK, MX51_PAD_CTRL_5), + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT12__FEC_RX_DV, MX51_PAD_CTRL_5), MX51_PAD_DISP2_DAT13__FEC_TX_CLK, MX51_PAD_DI2_PIN4__FEC_CRS, MX51_PAD_DI2_PIN2__FEC_MDC, - MX51_PAD_DI2_PIN3__FEC_MDIO, + NEW_PAD_CTRL(MX51_PAD_DI2_PIN3__FEC_MDIO, MX51_PAD_CTRL_5), MX51_PAD_DISP2_DAT14__FEC_RDATA0, MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, - MX51_PAD_DI_GP4__FEC_RDATA2, - MX51_PAD_DISP2_DAT0__FEC_RDATA3, + NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2, MX51_PAD_CTRL_5), + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT0__FEC_RDATA3, MX51_PAD_CTRL_5), MX51_PAD_DI_GP3__FEC_TX_ER, MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */ /* NAND */ -- 1.8.1.5 --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re[3]: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-09 15:05 ` Alexander Shiyan @ 2013-04-12 10:36 ` Alexander Shiyan 2013-04-12 17:26 ` Sascha Hauer 0 siblings, 1 reply; 11+ messages in thread From: Alexander Shiyan @ 2013-04-12 10:36 UTC (permalink / raw) To: Eric B�nard, Sascha Hauer, barebox > > Le Tue, 09 Apr 2013 12:01:51 +0400, > > Alexander Shiyan <shc_work@mail.ru> a écrit : > > > > > > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > > > > > > > This patch effectively reverts: > > > > > > > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > > > > Author: Eric Bénard <eric@eukrea.com> > > > > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > > > > > > > i.MX51: unbreak FEC iomux > > > > > > > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > > > > value. > > > > > > > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > > > > > > > You shouldn't do this. > > > > > > > > > > What about write a patch for the kernel for this? > > > > > > > > By the time I applied Erics patch I considered the days of the > > > > traditional iomux support in the kernel counted. From that day on > > > > we have to maintain our own versions anyway. > > > > > > OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC > > > pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. > > > This will keep iomux-mx51.h file synced. > > > > > Fine for me. Do you have a problem with these pads setting so that you > > need to revert the change ? > So, below is a temporary fixup. > > From 47d0d7b9c0355ba31e4c563891b2e9159dc07533 Mon Sep 17 00:00:00 2001 > From: Alexander Shiyan <shc_work@mail.ru> > Date: Tue, 9 Apr 2013 19:01:40 +0400 > Subject: [PATCH] ARM: cpuimx51: Fix PAD_CTRLs for FEC > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > --- > arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > index 5e77f90..523a805 100644 > --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > @@ -55,23 +55,23 @@ static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { > MX51_PAD_UART1_RTS__UART1_RTS, > MX51_PAD_UART1_CTS__UART1_CTS, > /* FEC */ > - MX51_PAD_DISP2_DAT1__FEC_RX_ER, > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_CTRL_5), > MX51_PAD_DISP2_DAT15__FEC_TDATA0, > MX51_PAD_DISP2_DAT6__FEC_TDATA1, > MX51_PAD_DISP2_DAT7__FEC_TDATA2, > MX51_PAD_DISP2_DAT8__FEC_TDATA3, > MX51_PAD_DISP2_DAT9__FEC_TX_EN, > - MX51_PAD_DISP2_DAT10__FEC_COL, > - MX51_PAD_DISP2_DAT11__FEC_RX_CLK, > - MX51_PAD_DISP2_DAT12__FEC_RX_DV, > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT10__FEC_COL, MX51_PAD_CTRL_5), > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT11__FEC_RX_CLK, MX51_PAD_CTRL_5), > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT12__FEC_RX_DV, MX51_PAD_CTRL_5), > MX51_PAD_DISP2_DAT13__FEC_TX_CLK, > MX51_PAD_DI2_PIN4__FEC_CRS, > MX51_PAD_DI2_PIN2__FEC_MDC, > - MX51_PAD_DI2_PIN3__FEC_MDIO, > + NEW_PAD_CTRL(MX51_PAD_DI2_PIN3__FEC_MDIO, MX51_PAD_CTRL_5), > MX51_PAD_DISP2_DAT14__FEC_RDATA0, > MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, > - MX51_PAD_DI_GP4__FEC_RDATA2, > - MX51_PAD_DISP2_DAT0__FEC_RDATA3, > + NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2, MX51_PAD_CTRL_5), > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT0__FEC_RDATA3, MX51_PAD_CTRL_5), > MX51_PAD_DI_GP3__FEC_TX_ER, > MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */ > /* NAND */ > -- > 1.8.1.5 > > --- ping --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: Update MX51 iomux definitions 2013-04-12 10:36 ` Re[3]: " Alexander Shiyan @ 2013-04-12 17:26 ` Sascha Hauer 0 siblings, 0 replies; 11+ messages in thread From: Sascha Hauer @ 2013-04-12 17:26 UTC (permalink / raw) To: Alexander Shiyan; +Cc: barebox On Fri, Apr 12, 2013 at 02:36:09PM +0400, Alexander Shiyan wrote: > > > Le Tue, 09 Apr 2013 12:01:51 +0400, > > > Alexander Shiyan <shc_work@mail.ru> a écrit : > > > > > > > > > > On Sun, Apr 07, 2013 at 12:48:57PM +0400, Alexander Shiyan wrote: > > > > > > > > The patch updates MX51 iomux definitions from kernel. > > > > > > > > > > > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > > > > > > > > > > > > > This patch effectively reverts: > > > > > > > > > > > > > > commit 298d15571da8d1cb71e7fd87cc53cad3b2bf1d12 > > > > > > > Author: Eric Bénard <eric@eukrea.com> > > > > > > > Date: Thu Sep 6 21:39:30 2012 +0200 > > > > > > > > > > > > > > i.MX51: unbreak FEC iomux > > > > > > > > > > > > > > in commit 2bdc9f57a86dff41cfc1f87b644a2e53fdcce2b6 the iomux was synced > > > > > > > with the kernel but this leads to some changes in the PAD_CTRL of some > > > > > > > FEC pins leading to a non working FEC on our cpuimx51 board. > > > > > > > > > > > > > > This patch set back the PAD_CTRL of the missing pins to the initial > > > > > > > value. > > > > > > > > > > > > > > Signed-off-by: Eric Bénard <eric@eukrea.com> > > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > > > > > > > > > > > > You shouldn't do this. > > > > > > > > > > > > What about write a patch for the kernel for this? > > > > > > > > > > By the time I applied Erics patch I considered the days of the > > > > > traditional iomux support in the kernel counted. From that day on > > > > > we have to maintain our own versions anyway. > > > > > > > > OK. Maybe as temporary solution we can define eukrea_cpuimx51 FEC > > > > pins with NEW_PAD_CTRL macro? If so, I'll create a patch for this. > > > > This will keep iomux-mx51.h file synced. > > > > > > > Fine for me. Do you have a problem with these pads setting so that you > > > need to revert the change ? > > So, below is a temporary fixup. > > > > From 47d0d7b9c0355ba31e4c563891b2e9159dc07533 Mon Sep 17 00:00:00 2001 > > From: Alexander Shiyan <shc_work@mail.ru> > > Date: Tue, 9 Apr 2013 19:01:40 +0400 > > Subject: [PATCH] ARM: cpuimx51: Fix PAD_CTRLs for FEC > > > > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru> > > --- > > arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > > index 5e77f90..523a805 100644 > > --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > > +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c > > @@ -55,23 +55,23 @@ static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { > > MX51_PAD_UART1_RTS__UART1_RTS, > > MX51_PAD_UART1_CTS__UART1_CTS, > > /* FEC */ > > - MX51_PAD_DISP2_DAT1__FEC_RX_ER, > > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_CTRL_5), > > MX51_PAD_DISP2_DAT15__FEC_TDATA0, > > MX51_PAD_DISP2_DAT6__FEC_TDATA1, > > MX51_PAD_DISP2_DAT7__FEC_TDATA2, > > MX51_PAD_DISP2_DAT8__FEC_TDATA3, > > MX51_PAD_DISP2_DAT9__FEC_TX_EN, > > - MX51_PAD_DISP2_DAT10__FEC_COL, > > - MX51_PAD_DISP2_DAT11__FEC_RX_CLK, > > - MX51_PAD_DISP2_DAT12__FEC_RX_DV, > > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT10__FEC_COL, MX51_PAD_CTRL_5), > > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT11__FEC_RX_CLK, MX51_PAD_CTRL_5), > > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT12__FEC_RX_DV, MX51_PAD_CTRL_5), > > MX51_PAD_DISP2_DAT13__FEC_TX_CLK, > > MX51_PAD_DI2_PIN4__FEC_CRS, > > MX51_PAD_DI2_PIN2__FEC_MDC, > > - MX51_PAD_DI2_PIN3__FEC_MDIO, > > + NEW_PAD_CTRL(MX51_PAD_DI2_PIN3__FEC_MDIO, MX51_PAD_CTRL_5), > > MX51_PAD_DISP2_DAT14__FEC_RDATA0, > > MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, > > - MX51_PAD_DI_GP4__FEC_RDATA2, > > - MX51_PAD_DISP2_DAT0__FEC_RDATA3, > > + NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2, MX51_PAD_CTRL_5), > > + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT0__FEC_RDATA3, MX51_PAD_CTRL_5), > > MX51_PAD_DI_GP3__FEC_TX_ER, > > MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */ > > /* NAND */ > > -- > > 1.8.1.5 > > > > --- > > ping Applied this one and then the original series. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2013-04-12 17:26 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-04-07 8:48 [PATCH 1/2] ARM: i.MX: Update MX2x iomux definitions Alexander Shiyan 2013-04-07 8:48 ` [PATCH 2/2] ARM: i.MX: Update MX51 " Alexander Shiyan 2013-04-09 6:49 ` Sascha Hauer 2013-04-09 6:52 ` Re[2]: " Alexander Shiyan 2013-04-09 7:31 ` Sascha Hauer 2013-04-09 8:01 ` Re[2]: " Alexander Shiyan 2013-04-09 8:03 ` Eric Bénard 2013-04-09 8:15 ` Re[2]: " Alexander Shiyan 2013-04-09 15:05 ` Alexander Shiyan 2013-04-12 10:36 ` Re[3]: " Alexander Shiyan 2013-04-12 17:26 ` Sascha Hauer
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