Re[2]: Boot from SD fail after 2013.02

["Alexander Shiyan" <shc_work@mail.ru>]

> > > > > On Wed, Apr 17, 2013 at 12:40:21PM +0400, Alexander Shiyan wrote:
> > > > > >  Hello.
> > > > > > 
> > > > > > I found strange problem with boot from SD after 2013.02 release.
> > > > > > Using a git-bisect I found problem start point, so:
> > > > > > 
> > > > > > 8e19ee94ab7aea50635845de31daef1b593e1205 is the first bad commit
> > > > > > commit 8e19ee94ab7aea50635845de31daef1b593e1205
> > > > > > Author: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > Date:   Fri Jan 25 23:39:20 2013 +0100
> > > > > > 
> > > > > >     ARM: Setup stack at end of SDRAM
> > > > > >     
> > > > > >     Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > > 
> > > > > > 
> > > > > > Exploring this commit does not helps me to have any idea how it
> > > > > > depends on SD-boot.
> > > > > > My target is ARM imx51 ConnectCore board.
> > > > > > Also I test it with freescale_mx51_babbage_defconfig since some
> > > > > > stuff is compatible with ConnectCore board.
> > > > > > Can anyone confirm this issue or have a solution?
> > > > > 
> > > > > Without this patch applied, can you post the output of the 'iomem'
> > > > > command and confirm that the SDRAM size is detected correctly?
> > > > 
> > > > Memory size is correct, 256M. At this time I cannot run "iomem" since
> > > > I am restore the faulty part as a result of my games.
> > > 
> > > Does barebox still work 2nd stage or is this a 1st stage only problem?
> > 
> > PBL is not used in my config now and I think this is a lowlevel stuff
> > because serial is not inited and I cannot see any message.
> 
> I was not asking about pbl, but only if you can start barebox from a
> running barebox.
> 
> > I any case I cannot test more now due broken hardware. I return to
> > test this after repair. Thanks!

So. OK, I temporary patch my board and it working now.
Please forget about correct memory size, it is not true.
Size is incorrect. Both banks are enabled and size detected as 512M.
I think this size is programmed by flash_header:
  { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
  { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },

After program NAND and start from NAND, size is still wrong...
So, what we can do it this case for proper operation? Disable second bank?
Define minimal size? Can you suggest a solution?

barebox@ConnectCore i.MX51:/ iomem
0x00000000 - 0xffffffff (size 0x00000000) iomem
  0x70004000 - 0x70004fff (size 0x00001000) imx-esdhc0
  0x7000c000 - 0x7000cfff (size 0x00001000) imx21-uart2
  0x70010000 - 0x70010fff (size 0x00001000) imx_spi0
  0x70020000 - 0x70020fff (size 0x00001000) imx-esdhc2
  0x73f84000 - 0x73f84fff (size 0x00001000) imx31-gpio0
  0x73f88000 - 0x73f88fff (size 0x00001000) imx31-gpio1
  0x73f8c000 - 0x73f8cfff (size 0x00001000) imx31-gpio2
  0x73f90000 - 0x73f90fff (size 0x00001000) imx31-gpio3
  0x73f98000 - 0x73f98fff (size 0x00001000) imx21-wdt0
  0x73fa0000 - 0x73fa0fff (size 0x00001000) imx31-gpt0
  0x73fa8000 - 0x73fa8fff (size 0x00001000) imx-iomuxv30
  0x73fbc000 - 0x73fbcfff (size 0x00001000) imx21-uart0
  0x73fc0000 - 0x73fc0fff (size 0x00001000) imx21-uart1
  0x73fd4000 - 0x73fd4fff (size 0x00001000) imx51-ccm0
  0x83f98000 - 0x83f98fff (size 0x00001000) imx_iim0
  0x83fc4000 - 0x83fc4fff (size 0x00001000) i2c-fsl1
  0x83fd9000 - 0x83fd9fff (size 0x00001000) imx51-esdctl0
  0x83fdb000 - 0x83fdbfff (size 0x00001000) imx_nand0
  0x90000000 - 0xafffffff (size 0x20000000) ram0
    0x95ef8000 - 0x95efffff (size 0x00008000) stack
    0x95f00000 - 0x97efffff (size 0x02000000) malloc space
    0x97f02000 - 0x97f33c07 (size 0x00031c08) barebox
    0x97f37df0 - 0x97f3e9df (size 0x00006bf0) bss
  0xcfff0000 - 0xcfff0fff (size 0x00001000) imx_nand0


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