From: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
To: barebox@lists.infradead.org
Cc: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Subject: [PATCH 2/3] ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)
Date: Tue, 14 May 2013 15:14:55 +0200 [thread overview]
Message-ID: <1368537296-19610-2-git-send-email-enrico.scholz@sigma-chemnitz.de> (raw)
In-Reply-To: <1368537296-19610-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
---
arch/arm/cpu/cache-armv7.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 5bdf7e4..5595cf6 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -65,7 +65,7 @@ ENTRY(v7_mmu_cache_flush)
mcr p15, 0, r12, c7, c14, 0 @ clean+invalidate D
b iflush
hierarchical:
- stmfd sp!, {r0-r7, r9-r11}
+ stmfd sp!, {r4-r7, r9-r11}
mcr p15, 0, r12, c7, c10, 5 @ DMB
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
@@ -107,7 +107,7 @@ skip:
cmp r3, r12
bgt loop1
finished:
- ldmfd sp!, {r0-r7, r9-r11}
+ ldmfd sp!, {r4-r7, r9-r11}
mov r12, #0 @ switch back to cache level 0
mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr
iflush:
--
1.8.1.4
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next prev parent reply other threads:[~2013-05-14 13:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-14 13:14 [PATCH 1/3] ARM v7: fix mmu-off operation Enrico Scholz
2013-05-14 13:14 ` Enrico Scholz [this message]
2013-05-14 13:14 ` [PATCH 3/3] ARM v7: added v7_mmu_cache_invalidate() Enrico Scholz
2013-05-17 8:28 ` Sascha Hauer
2013-05-15 6:28 ` [PATCH 1/3] ARM v7: fix mmu-off operation Sascha Hauer
2013-05-17 8:24 ` Sascha Hauer
2013-05-17 9:22 ` Enrico Scholz
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