[PATCH 0/6] ARM: mvebu: DT support, SPI driver, and Dove DT

[PATCH 0/6] ARM: mvebu: DT support, SPI driver, and Dove DT

[Sebastian Hesselbarth]

This patch set is a first attempt to bring full DT support to Marvell
MVEBU SoCs. It also introduces a driver for the SPI controller found
on these SoCs with special treatment of additional functions for Dove
and Armada 370/XP SoCs.

First, current soc_init is moved from postcore initcall to core initcall,
to allow clocks to be accessed early. Then DT support is added for both
clocksource drivers found on Orion and Armada 370/XP SoCs, respectively.
Third, a DT-only SPI driver is added to allow access to SPI devices found
on boards comprising Marvell SoCs.

The last two patches extend SolidRun CuBox defconfig with a bunch of
options for future drivers and debug commands and import DTS files from
Linux with an additional node for the timer.

The patch set depends on the MVEBU/Orion clocksource callback patch sent
earlier.

Sebastian Hesselbarth (6):
  ARM: mvebu: move soc_init to core_initcall
  clocksource: orion: add DT support
  clocksource: mvebu: add DT support
  spi: add Marvell MVEBU SoC SPI driver
  ARM: mvebu: add more options to SolidRun CuBox defconfig
  ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

 arch/arm/configs/solidrun_cubox_defconfig |   71 ++++++
 arch/arm/dts/dove-cubox.dts               |  154 ++++++++++++
 arch/arm/dts/dove.dtsi                    |  285 ++++++++++++++++++++++
 arch/arm/mach-mvebu/armada-370-xp.c       |    2 +-
 arch/arm/mach-mvebu/dove.c                |    2 +-
 arch/arm/mach-mvebu/kirkwood.c            |    2 +-
 drivers/clocksource/mvebu.c               |    9 +-
 drivers/clocksource/orion.c               |    8 +-
 drivers/spi/Kconfig                       |    4 +
 drivers/spi/Makefile                      |    1 +
 drivers/spi/mvebu_spi.c                   |  378 +++++++++++++++++++++++++++++
 11 files changed, 910 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/dts/dove-cubox.dts
 create mode 100644 arch/arm/dts/dove.dtsi
 create mode 100644 drivers/spi/mvebu_spi.c

---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
-- 
1.7.2.5


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[PATCH 1/6] ARM: mvebu: move soc_init to core_initcall

[Sebastian Hesselbarth]

Clocks need to be accessed early for DT support, so move soc_init to
core_initcall instead of postcore_initcall.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/armada-370-xp.c |    2 +-
 arch/arm/mach-mvebu/dove.c          |    2 +-
 arch/arm/mach-mvebu/kirkwood.c      |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 2cdc3b0..1d64861 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -109,7 +109,7 @@ static int armada_370_xp_init_soc(void)
 	armada_370_xp_add_uart();
 	return 0;
 }
-postcore_initcall(armada_370_xp_init_soc);
+core_initcall(armada_370_xp_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 6e8e113..ee63917 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -132,7 +132,7 @@ static int dove_init_soc(void)
 
 	return 0;
 }
-postcore_initcall(dove_init_soc);
+core_initcall(dove_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 3e16f41..9e43dae 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -95,7 +95,7 @@ static int kirkwood_init_soc(void)
 
 	return 0;
 }
-postcore_initcall(kirkwood_init_soc);
+core_initcall(kirkwood_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
-- 
1.7.2.5


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[PATCH 2/6] clocksource: orion: add DT support

[Sebastian Hesselbarth]

This adds device tree support to orion timer and also converts clk_get
to clk_lookup to find TCLK without device name reference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/clocksource/orion.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c
index e3db845..ed71fa4 100644
--- a/drivers/clocksource/orion.c
+++ b/drivers/clocksource/orion.c
@@ -49,7 +49,7 @@ static int orion_timer_probe(struct device_d *dev)
 	uint32_t val;
 
 	timer_base = dev_request_mem_region(dev, 0);
-	tclk = clk_get(dev, "tclk");
+	tclk = clk_lookup("tclk");
 
 	/* setup TIMER0 as free-running clock source */
 	__raw_writel(~0, timer_base + TIMER0_VAL);
@@ -64,9 +64,15 @@ static int orion_timer_probe(struct device_d *dev)
 	return 0;
 }
 
+static struct of_device_id orion_timer_dt_ids[] = {
+	{ .compatible = "marvell,orion-timer", },
+	{ }
+};
+
 static struct driver_d orion_timer_driver = {
 	.name = "orion-timer",
 	.probe = orion_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(orion_timer_dt_ids),
 };
 
 static int orion_timer_init(void)
-- 
1.7.2.5


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Re: [PATCH 2/6] clocksource: orion: add DT support

[Sascha Hauer]

On Fri, Jun 28, 2013 at 08:25:43PM +0200, Sebastian Hesselbarth wrote:
> This adds device tree support to orion timer and also converts clk_get
> to clk_lookup to find TCLK without device name reference.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: barebox@lists.infradead.org
> ---
>  drivers/clocksource/orion.c |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c
> index e3db845..ed71fa4 100644
> --- a/drivers/clocksource/orion.c
> +++ b/drivers/clocksource/orion.c
> @@ -49,7 +49,7 @@ static int orion_timer_probe(struct device_d *dev)
>  	uint32_t val;
>  
>  	timer_base = dev_request_mem_region(dev, 0);
> -	tclk = clk_get(dev, "tclk");
> +	tclk = clk_lookup("tclk");

Please don't do this. I don't know how it is done in the kernel
for orion atm, but you could for example help yourself with
clkdev_add_physbase until the clocks can be properly looked up from
the devicetree.

Sascha


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Re: [PATCH 2/6] clocksource: orion: add DT support

[Sebastian Hesselbarth]

On 06/29/2013 10:49 AM, Sascha Hauer wrote:
> On Fri, Jun 28, 2013 at 08:25:43PM +0200, Sebastian Hesselbarth wrote:
>> This adds device tree support to orion timer and also converts clk_get
>> to clk_lookup to find TCLK without device name reference.
>>
>> Signed-off-by: Sebastian Hesselbarth<sebastian.hesselbarth@gmail.com>
>> ---
>> Cc: Thomas Petazzoni<thomas.petazzoni@free-electrons.com>
>> Cc: barebox@lists.infradead.org
>> ---
>>   drivers/clocksource/orion.c |    8 +++++++-
>>   1 files changed, 7 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c
>> index e3db845..ed71fa4 100644
>> --- a/drivers/clocksource/orion.c
>> +++ b/drivers/clocksource/orion.c
>> @@ -49,7 +49,7 @@ static int orion_timer_probe(struct device_d *dev)
>>   	uint32_t val;
>>
>>   	timer_base = dev_request_mem_region(dev, 0);
>> -	tclk = clk_get(dev, "tclk");
>> +	tclk = clk_lookup("tclk");
>
> Please don't do this. I don't know how it is done in the kernel
> for orion atm, but you could for example help yourself with
> clkdev_add_physbase until the clocks can be properly looked up from
> the devicetree.

Ok, clock provider for MVEBU barebox is still missing. But in the
meantime, I will use clkdev_add_physbase or any equivalent workaround
until full clock provider will be available.

Sebastian


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[PATCH 3/6] clocksource: mvebu: add DT support

[Sebastian Hesselbarth]

This adds device tree support to mvebu timer and also converts clk_get
to clk_lookup to find TCLK without device name reference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/clocksource/mvebu.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c
index 8bedd99..93b0b61 100644
--- a/drivers/clocksource/mvebu.c
+++ b/drivers/clocksource/mvebu.c
@@ -57,8 +57,7 @@ static int mvebu_timer_probe(struct device_d *dev)
 	u32 val;
 
 	timer_base = dev_request_mem_region(dev, 0);
-
-	tclk = clk_get(dev, "tclk");
+	tclk = clk_lookup("tclk");
 
 	val = __raw_readl(timer_base + TIMER_CTRL_OFF);
 	val &= ~TIMER0_25MHZ;
@@ -78,9 +77,15 @@ static int mvebu_timer_probe(struct device_d *dev)
 	return 0;
 }
 
+static struct of_device_id mvebu_timer_dt_ids[] = {
+	{ .compatible = "marvell,armada-370-xp-timer", },
+	{ }
+};
+
 static struct driver_d mvebu_timer_driver = {
 	.name = "mvebu-timer",
 	.probe = mvebu_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_timer_dt_ids),
 };
 
 static int mvebu_timer_init(void)
-- 
1.7.2.5


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[PATCH 4/6] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

This adds support for the SPI controller found on Marvell MVEBU SoCs
(Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
is DT only. Compatible strings are provided for Orion (common denominator),
Armada 370/XP and Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/spi/Kconfig     |    4 +
 drivers/spi/Makefile    |    1 +
 drivers/spi/mvebu_spi.c |  378 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 383 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/mvebu_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c279c21..422693c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -38,6 +38,10 @@ config DRIVER_SPI_MXS
 	depends on ARCH_IMX23 || ARCH_IMX28
 	depends on SPI
 
+config DRIVER_SPI_MVEBU
+	bool "Marvell MVEBU SoC SPI master driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_DOVE || ARCH_KIRKWOOD
+
 config DRIVER_SPI_OMAP3
 	bool "OMAP3 McSPI Master driver"
 	depends on ARCH_OMAP3 || ARCH_AM33XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 642b7ec..1036f8f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_SPI) += spi.o
 obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
+obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
 obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
 obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
 obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o
diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c
new file mode 100644
index 0000000..200523d
--- /dev/null
+++ b/drivers/spi/mvebu_spi.c
@@ -0,0 +1,378 @@
+/*
+ * Marvell MVEBU SoC SPI controller
+ *  compatible with Dove, Kirkwood, MV78x00, Armada 370/XP
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <spi/spi.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#define SPI_IF_CTRL		0x00
+#define  IF_CS_NUM(x)		((x) << 2)
+#define  IF_CS_NUM_MASK		IF_CS_NUM(7)
+#define  IF_READ_READY		BIT(1)
+#define  IF_CS_ENABLE		BIT(0)
+#define SPI_IF_CONFIG		0x04
+#define  IF_CLK_DIV(x)		((x) << 11)
+#define  IF_CLK_DIV_MASK	(0x7 << 11)
+#define  IF_FAST_READ		BIT(10)
+#define  IF_ADDRESS_LEN_4BYTE	(3 << 8)
+#define  IF_ADDRESS_LEN_3BYTE	(2 << 8)
+#define  IF_ADDRESS_LEN_2BYTE	(1 << 8)
+#define  IF_ADDRESS_LEN_1BYTE	(0 << 8)
+#define  IF_CLK_PRESCALE_POW8	BIT(7)
+#define  IF_CLK_PRESCALE_POW4	BIT(6)
+#define  IF_TRANSFER_2BYTE	BIT(5)
+#define  IF_CLK_PRESCALE_POW2	BIT(4)
+#define  IF_CLK_PRESCALE(x)	((x) & 0x0f)
+#define  IF_CLK_PRE_PRESCALE(x)	(((((x) & 0xc) << 1) | ((x) & 0x1)) << 4)
+#define  IF_CLK_PRESCALE_MASK	(IF_CLK_PRESCALE(7) | IF_CLK_PRE_PRESCALE(7))
+#define SPI_DATA_OUT		0x08
+#define SPI_DATA_IN		0x0c
+#define SPI_INT_CAUSE		0x10
+#define SPI_INT_MASK		0x14
+#define  INT_READ_READY		BIT(0)
+
+#define SPI_SPI_MAX_CS	8
+
+struct mvebu_spi {
+	struct spi_master master;
+	void __iomem *base;
+	struct clk *clk;
+	bool data16;
+	int (*set_baudrate)(struct mvebu_spi *p, u32 speed);
+};
+
+#define priv_from_spi_device(s)	\
+	container_of(s->master, struct mvebu_spi, master);
+
+static inline int mvebu_spi_set_cs(struct mvebu_spi *p, u8 cs, u8 mode, bool en)
+{
+	u32 val;
+
+	/*
+	 * Only Armada 370/XP support up to 8 CS signals, for the
+	 * others this register bits are read-only
+	 */
+	if (cs > SPI_SPI_MAX_CS)
+		return -EINVAL;
+
+	if (mode & SPI_CS_HIGH)
+		en = !en;
+
+	val = IF_CS_NUM(cs);
+	if (en)
+		val |= IF_CS_ENABLE;
+
+	writel(val, p->base + SPI_IF_CTRL);
+
+	return 0;
+}
+
+static int mvebu_spi_set_transfer_size(struct mvebu_spi *p, int size)
+{
+	u32 val;
+
+	if (size != 8 && size != 16)
+		return -EINVAL;
+
+	p->data16 = (size == 16);
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~IF_TRANSFER_2BYTE;
+	if (p->data16)
+		val |= IF_TRANSFER_2BYTE;
+	writel(val, p->base + SPI_IF_CONFIG);
+	
+	return 0;
+}
+
+static int mvebu_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, val;
+
+	/* standard prescaler values: 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	pscl = roundup(pscl, 2);
+
+	debug("%s: clk = %lu, speed = %u, pscl = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl);
+
+	if (pscl > 30)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP) 
+static int armada_370_xp_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, pdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+
+	/* additional prescaler divider: 1, 2, 4, 8, 16, 32, 64, 128 */
+	pdiv = 0; rate = pscl;
+	while (rate > 15 && pdiv <= 7) {
+		rate /= 2;
+		pdiv++;
+	}
+
+	debug("%s: clk = %lu, speed = %u, pscl = %d, pdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, pdiv);
+
+	if (rate > 15 || pdiv > 7)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRE_PRESCALE(pdiv) | IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+#if defined(ARCH_DOVE)
+static int dove_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, sdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 and 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	if (pscl > 15)
+		pscl = roundup(pscl, 2);
+
+	/* additional sclk divider: 1, 2, 4, 8, 16 */
+	sdiv = 0; rate = pscl;
+	while (rate > 30 && sdiv <= 4) {
+		rate /= 2;
+		sdiv++;
+	}
+
+	debug("%s: clk = %lu, speed = %u, pscl = %d, sdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, sdiv);
+
+	if (rate > 30 || sdiv > 4)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) &
+		~(IF_CLK_DIV_MASK | IF_CLK_PRESCALE_MASK);
+
+	val |= IF_CLK_DIV(sdiv);
+	if (pscl > 15)
+		val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	else
+		val |= IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
+{
+	/*
+	 * From public datasheets of Orion SoCs, it is unclear
+	 * if the SPI controller supports setting CPOL/CPHA.
+	 * Dove has an SCK_INV but as with the other SoCs, it
+	 * is tagged with "Must be 1".
+	 *
+	 * For now, we just bail out if device requests any
+	 * other mode than SPI_MODE0.
+	 */
+
+	if ((mode & (SPI_CPOL|SPI_CPHA)) == SPI_MODE_0)
+		return 0;
+
+	pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
+
+	return -EINVAL;
+}
+
+static int mvebu_spi_setup(struct spi_device *spi)
+{
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	debug("%s: mode %02x, bits_per_word = %d, speed = %d\n",
+		__func__, spi->mode, spi->bits_per_word, spi->max_speed_hz);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_mode(priv, spi->mode);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	return priv->set_baudrate(priv, spi->max_speed_hz);
+}
+
+static inline int mvebu_spi_wait_for_read_ready(struct mvebu_spi *p)
+{
+	int timeout = 100;
+	while ((readl(p->base + SPI_IF_CTRL) & IF_READ_READY) == 0 &&
+		timeout--)
+		udelay(1);
+	if (timeout < 0)
+		return -EIO;
+	return 0;
+}
+
+static int mvebu_spi_do_transfer(struct spi_device *spi,
+				 struct spi_transfer *t)
+{
+	const u8 *txdata = t->tx_buf;
+	u8 *rxdata = t->rx_buf;
+	int ret = 0, n, inc;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	if (t->bits_per_word)
+		ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	if (t->speed_hz)
+		ret = priv->set_baudrate(priv, t->speed_hz);
+	if (ret)
+		return ret;
+
+	inc = (priv->data16) ? 2 : 1;
+	for (n = 0; n < t->len; n += inc) {
+		u32 data = 0;
+
+		if (txdata)
+			data = *txdata++;
+		if (txdata && priv->data16)
+			data |= (*txdata++ << 8);
+
+		writel(data, priv->base + SPI_DATA_OUT);
+
+		ret = mvebu_spi_wait_for_read_ready(priv);
+		if (ret) {
+			dev_err(&spi->dev, "timeout reading from device %s\n",
+				dev_name(&spi->dev));
+			return ret;
+		}
+
+		data = readl(priv->base + SPI_DATA_IN);
+
+		if (rxdata)
+			*rxdata++ = (data & 0xff);
+		if (rxdata && priv->data16)
+			*rxdata++ = (data >> 8) & 0xff;
+	}
+
+	return 0;
+}
+
+static int mvebu_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct spi_transfer *t;
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, true);
+	if (ret)
+		return ret;
+
+	msg->actual_length = 0;
+
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		ret = mvebu_spi_do_transfer(spi, t);
+		if (ret)
+			break;
+		msg->actual_length += t->len;
+	}
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static struct of_device_id mvebu_spi_dt_ids[] = {
+	{ .compatible = "marvell,orion-spi",
+	  .data = (unsigned long)&mvebu_spi_set_baudrate },
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP) 
+	{ .compatible = "marvell,armada-370-xp-spi",
+	  .data = (unsigned long)&armada_370_xp_spi_set_baudrate },
+#endif
+#if defined(ARCH_DOVE)
+	{ .compatible = "marvell,dove-spi",
+	  .data = (unsigned long)&dove_spi_set_baudrate },
+#endif
+	{ }
+};
+
+static int mvebu_spi_probe(struct device_d *dev)
+{
+	struct spi_master *master;
+	struct mvebu_spi *priv;
+	const struct of_device_id *match;
+	int ret = 0;
+
+	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
+	if (!match)
+		return -EINVAL;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->base = dev_request_mem_region(dev, 0);
+	priv->set_baudrate = (void *)match->data;
+	priv->clk = clk_lookup("tclk");
+	if (IS_ERR(priv->clk)) {
+		ret = PTR_ERR(priv->clk);
+		goto err_free;
+	}
+
+	master = &priv->master;
+	master->dev = dev;
+	master->bus_num = dev->id;
+	master->setup = mvebu_spi_setup;
+	master->transfer = mvebu_spi_transfer;
+	master->num_chipselect = 1;
+
+	if (dev->device_node)
+		spi_of_register_slaves(master, dev->device_node);
+
+	ret = spi_register_master(master);
+	if (!ret)
+		return 0;
+
+err_free:
+	free(priv);
+
+	return ret;
+}
+
+static struct driver_d mvebu_spi_driver = {
+	.name  = "mvebu-spi",
+	.probe = mvebu_spi_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_spi_dt_ids),
+};
+device_platform_driver(mvebu_spi_driver);
-- 
1.7.2.5


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Re: [PATCH 4/6] spi: add Marvell MVEBU SoC SPI driver

[Sascha Hauer]

On Fri, Jun 28, 2013 at 08:25:45PM +0200, Sebastian Hesselbarth wrote:
> This adds support for the SPI controller found on Marvell MVEBU SoCs
> (Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
> is DT only. Compatible strings are provided for Orion (common denominator),
> Armada 370/XP and Dove SoCs.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Mostly good, some minor stuff inline.

> +static int mvebu_spi_set_transfer_size(struct mvebu_spi *p, int size)
> +{
> +	u32 val;
> +
> +	if (size != 8 && size != 16)
> +		return -EINVAL;
> +
> +	p->data16 = (size == 16);
> +
> +	val = readl(p->base + SPI_IF_CONFIG) & ~IF_TRANSFER_2BYTE;
> +	if (p->data16)
> +		val |= IF_TRANSFER_2BYTE;
> +	writel(val, p->base + SPI_IF_CONFIG);
> +	

Trailing whitespaces here and elsewhere.

> +	return 0;
> +}
> +
> +static int mvebu_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
> +{
> +	u32 pscl, val;
> +
> +	/* standard prescaler values: 1,2,4,6,...,30 */
> +	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
> +	pscl = roundup(pscl, 2);
> +
> +	debug("%s: clk = %lu, speed = %u, pscl = %d\n",
> +		__func__, clk_get_rate(p->clk), speed, pscl);

Please use dev_dbg and friends in drivers.

> +	int ret = 0;
> +
> +	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
> +	if (!match)
> +		return -EINVAL;
> +
> +	priv = xzalloc(sizeof(*priv));
> +	priv->base = dev_request_mem_region(dev, 0);

Please check priv->base for validity. I know, most other drivers also
don't do it, but at least new drivers should.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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[PATCH 5/6] ARM: mvebu: add more options to SolidRun CuBox defconfig

[Sebastian Hesselbarth]

This patch updates SolidRun CuBox defconfig to more commands also valueable
for debug. Also, all future driver subsystems are enabled to ease driver
development.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/configs/solidrun_cubox_defconfig |   71 +++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/solidrun_cubox_defconfig b/arch/arm/configs/solidrun_cubox_defconfig
index 1a27d81..c900243 100644
--- a/arch/arm/configs/solidrun_cubox_defconfig
+++ b/arch/arm/configs/solidrun_cubox_defconfig
@@ -1,9 +1,80 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="dove-cubox"
 CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_DOVE=y
 CONFIG_AEABI=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
 CONFIG_DEBUG_LL=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_BASENAME=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_LOADY=y
 CONFIG_CMD_LOADS=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_WD=y
+CONFIG_OFDEVICE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SPI_MVEBU=y
+CONFIG_I2C=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_DISK_AHCI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_LED=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_WATCHDOG=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
-- 
1.7.2.5


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[PATCH 6/6] ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

[Sebastian Hesselbarth]

This imports dove.dtsi and dove-cubox.dts from Linux kernel with timer
node added.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/dts/dove-cubox.dts |  154 +++++++++++++++++++++++
 arch/arm/dts/dove.dtsi      |  285 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 439 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/dove-cubox.dts
 create mode 100644 arch/arm/dts/dove.dtsi

diff --git a/arch/arm/dts/dove-cubox.dts b/arch/arm/dts/dove-cubox.dts
new file mode 100644
index 0000000..b7dc243
--- /dev/null
+++ b/arch/arm/dts/dove-cubox.dts
@@ -0,0 +1,154 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	compatible = "solidrun,cubox", "marvell,dove";
+	model = "SolidRun CuBox";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x3f000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_gpio_18>;
+		pinctrl-names = "default";
+
+		power {
+			label = "Power";
+			gpios = <&gpio0 18 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 1 0>;
+		};
+	};
+
+	clocks {
+		/* 25MHz reference crystal */
+		ref25: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+
+	video-card {
+		compatible = "marvell,dove-video-card";
+		reg = <0x3f000000 0x1000000>;
+		marvell,external-encoder = <&tda19988>;
+	};
+};
+
+&uart0 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&lcd0 {
+	status = "okay";
+	clocks = <&si5351 0>;
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	si5351: clock-generator {
+		compatible = "silabs,si5351a-msop";
+		reg = <0x60>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#clock-cells = <1>;
+
+		/* connect xtal input to 25MHz reference */
+		clocks = <&ref25>;
+
+		/* connect xtal input as source of pll0 and pll1 */
+		silabs,pll-source = <0 0>, <1 0>;
+
+		clkout0 {
+			reg = <0>;
+			silabs,drive-strength = <8>;
+			silabs,multisynth-source = <0>;
+			silabs,clock-source = <0>;
+			silabs,pll-master;
+		};
+
+		clkout1 {
+			reg = <1>;
+			silabs,drive-strength = <8>;
+			silabs,multisynth-source = <1>;
+			silabs,clock-source = <0>;
+			silabs,pll-master;
+		};
+
+		clkout2 {
+			reg = <2>;
+			silabs,multisynth-source = <1>;
+			silabs,clock-source = <0>;
+		};
+	};
+
+	tda19988: hdmi-encoder@70 {
+		compatible = "nxp,tda1998x";
+		reg = <0x70>;
+	};
+};
+
+&sdio0 {
+	status = "okay";
+        bus-width = <4>;
+	/* sdio0 card detect is connected to wrong pin on CuBox */
+	cd-gpios = <&gpio0 12 1>;
+};
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash@0 {
+		compatible = "winbond,w25q32", "m25p80";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>;
+	pinctrl-names = "default";
+
+	pmx_gpio_1: pmx-gpio-1 {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_gpio_12: pmx-gpio-12 {
+		marvell,pins = "mpp12";
+		marvell,function = "gpio";
+	};
+
+	pmx_gpio_18: pmx-gpio-18 {
+		marvell,pins = "mpp18";
+		marvell,function = "gpio";
+	};
+};
diff --git a/arch/arm/dts/dove.dtsi b/arch/arm/dts/dove.dtsi
new file mode 100644
index 0000000..98b7e29
--- /dev/null
+++ b/arch/arm/dts/dove.dtsi
@@ -0,0 +1,285 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "marvell,dove";
+	model = "Marvell Armada 88AP510 SoC";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
+	soc@f1000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&intc>;
+
+		ranges = <0xc8000000 0xc8000000 0x0100000   /* CESA SRAM   1M */
+		          0xe0000000 0xe0000000 0x8000000   /* PCIe0 Mem 128M */
+		          0xe8000000 0xe8000000 0x8000000   /* PCIe1 Mem 128M */
+		          0xf0000000 0xf0000000 0x0100000   /* ScratchPad  1M */
+		          0x00000000 0xf1000000 0x1000000   /* SB/NB regs 16M */
+		          0xf2000000 0xf2000000 0x0100000   /* PCIe0 I/O   1M */
+		          0xf2100000 0xf2100000 0x0100000   /* PCIe0 I/O   1M */
+		          0xf8000000 0xf8000000 0x8000000>; /* BootROM   128M */
+
+		l2: l2-cache {
+			compatible = "marvell,tauros2-cache";
+			marvell,tauros2-cache-features = <0>;
+		};
+
+		timer: timer@20300 {
+			compatible = "marvell,orion-timer";
+                        reg = <0x20300 0x30>;
+		};
+
+		intc: interrupt-controller@20204 {
+			compatible = "marvell,orion-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x20204 0x04>, <0x20214 0x04>;
+		};
+
+		core_clk: core-clocks@d0214 {
+			compatible = "marvell,dove-core-clock";
+			reg = <0xd0214 0x4>;
+			#clock-cells = <1>;
+		};
+
+		gate_clk: clock-gating-control@d0038 {
+			compatible = "marvell,dove-gating-clock";
+			reg = <0xd0038 0x4>;
+			clocks = <&core_clk 0>;
+			#clock-cells = <1>;
+		};
+
+		thermal: thermal@d001c {
+			compatible = "marvell,dove-thermal";
+			reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+		};
+
+		uart0: serial@12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <7>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart1: serial@12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <8>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart2: serial@12200 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <9>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart3: serial@12300 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <10>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		gpio0: gpio@d0400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0400 0x20>;
+			ngpios = <32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <12>, <13>, <14>, <60>;
+		};
+
+		gpio1: gpio@d0420 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0420 0x20>;
+			ngpios = <32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <61>;
+		};
+
+		gpio2: gpio@e8400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xe8400 0x0c>;
+			ngpios = <8>;
+		};
+
+		pinctrl: pinctrl@d0200 {
+			compatible = "marvell,dove-pinctrl";
+			reg = <0xd0200 0x10>;
+			clocks = <&gate_clk 22>;
+		};
+
+		spi0: spi@10600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			interrupts = <6>;
+			reg = <0x10600 0x28>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		spi1: spi@14600 {
+			compatible = "marvell,dove-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			interrupts = <5>;
+			reg = <0x14600 0x28>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11>;
+			clock-frequency = <400000>;
+			timeout-ms = <1000>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		ehci0: usb-host@50000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x50000 0x1000>;
+			interrupts = <24>;
+			clocks = <&gate_clk 0>;
+			status = "okay";
+		};
+
+		ehci1: usb-host@51000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x51000 0x1000>;
+			interrupts = <25>;
+			clocks = <&gate_clk 1>;
+			status = "okay";
+		};
+
+		sdio0: sdio@92000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x92000 0x100>;
+			interrupts = <35>, <37>;
+			clocks = <&gate_clk 8>;
+			status = "disabled";
+		};
+
+		sdio1: sdio@90000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x90000 0x100>;
+			interrupts = <36>, <38>;
+			clocks = <&gate_clk 9>;
+			status = "disabled";
+		};
+
+		sata0: sata@a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x2400>;
+			interrupts = <62>;
+			clocks = <&gate_clk 3>;
+			nr-ports = <1>;
+			status = "disabled";
+		};
+
+		rtc@d8500 {
+			compatible = "marvell,orion-rtc";
+			reg = <0xd8500 0x20>;
+		};
+
+		crypto: crypto@30000 {
+			compatible = "marvell,orion-crypto";
+			reg = <0x30000 0x10000>,
+			      <0xc8000000 0x800>;
+			reg-names = "regs", "sram";
+			interrupts = <31>;
+			clocks = <&gate_clk 15>;
+			status = "okay";
+		};
+
+		xor0: dma-engine@60800 {
+			compatible = "marvell,orion-xor";
+			reg = <0x60800 0x100
+			       0x60a00 0x100>;
+			clocks = <&gate_clk 23>;
+			status = "okay";
+
+			channel0 {
+				interrupts = <39>;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+
+			channel1 {
+				interrupts = <40>;
+				dmacap,memset;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+		};
+
+		xor1: dma-engine@60900 {
+			compatible = "marvell,orion-xor";
+			reg = <0x60900 0x100
+			       0x60b00 0x100>;
+			clocks = <&gate_clk 24>;
+			status = "okay";
+
+			channel0 {
+				interrupts = <42>;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+
+			channel1 {
+				interrupts = <43>;
+				dmacap,memset;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+		};
+		
+		lcd0: lcd-controller@820000 {
+			compatible = "marvell,dove-lcd";
+			reg = <0x820000 0x200>;
+			interrupts = <47>;
+			clocks = <0>;
+			status = "disabled";
+		};
+		
+		lcd1: lcd-controller@810000 {
+			compatible = "marvell,dove-lcd";
+			reg = <0x810000 0x200>;
+			interrupts = <46>;
+			clocks = <0>;
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.2.5


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Re: [PATCH 6/6] ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

[Sascha Hauer]

On Fri, Jun 28, 2013 at 08:25:47PM +0200, Sebastian Hesselbarth wrote:
> This imports dove.dtsi and dove-cubox.dts from Linux kernel with timer
> node added.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: barebox@lists.infradead.org
> ---
>  arch/arm/dts/dove-cubox.dts |  154 +++++++++++++++++++++++
>  arch/arm/dts/dove.dtsi      |  285 +++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 439 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/dts/dove-cubox.dts
>  create mode 100644 arch/arm/dts/dove.dtsi
> 
> diff --git a/arch/arm/dts/dove-cubox.dts b/arch/arm/dts/dove-cubox.dts
> new file mode 100644
> index 0000000..b7dc243
> --- /dev/null
> +++ b/arch/arm/dts/dove-cubox.dts
> @@ -0,0 +1,154 @@
> +/dts-v1/;
> +
> +/include/ "dove.dtsi"
> +
> +/ {
> +	compatible = "solidrun,cubox", "marvell,dove";
> +	model = "SolidRun CuBox";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x3f000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};

I would add a linux,stdoutpath property here. Then you can switch to
CONFIG_CONSOLE_ACTIVATE_NONE in the defconfig and enable multiple uarts
in the dts without risking that the first one to be activated is not the
console port.

> +
> +&sdio0 {
> +	status = "okay";
> +        bus-width = <4>;

Use tab here.

> +		};
> +		
> +		lcd0: lcd-controller@820000 {
> +			compatible = "marvell,dove-lcd";
> +			reg = <0x820000 0x200>;
> +			interrupts = <47>;
> +			clocks = <0>;
> +			status = "disabled";
> +		};
> +		

Trailing whitespaces.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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[PATCH v2 00/10] ARM: mvebu: DT support, SPI, GPIO driver, and Dove DT

[Sebastian Hesselbarth]

This patch set is a first attempt to bring full DT support to Marvell
MVEBU SoCs. It also introduces a driver for the SPI controller found
on these SoCs with special treatment of additional functions for Dove
and Armada 370/XP SoCs. Also a GPIO driver is added that I have written
during OF patches.

First, current soc_init is moved from postcore initcall to core initcall,
to allow clocks to be accessed early. Clock lookup for timers is converted
to physbase instead of name-based lookup. Then DT support is added for both
clocksource drivers found on Orion and Armada 370/XP SoCs, respectively.

Also, a DT-only SPI driver is added to allow access to SPI devices found
on boards comprising Marvell SoCs. Then a DT-only GPIO driver compatible
with MVEBU SoCs and device tree parsing for gpio-leds is added.

The last two patches extend SolidRun CuBox defconfig with a bunch of
options for future drivers and debug commands and import DTS files from
Linux with an additional node for the timer.

Sebastian Hesselbarth (10):
  ARM: mvebu: move soc_init to core_initcall
  clocksource: orion: lookup clock by physbase
  clocksource: orion: add DT support
  clocksource: mvebu: lookup clock by physbase
  clocksource: mvebu: add DT support
  spi: add Marvell MVEBU SoC SPI driver
  GPIO: add Marvell Orion/MVEBU SoC GPIO driver
  LED: add support for device tree parsing of gpio-leds
  ARM: mvebu: add more options to SolidRun CuBox defconfig
  ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

 arch/arm/Kconfig                          |    1 +
 arch/arm/configs/solidrun_cubox_defconfig |   72 ++++++
 arch/arm/dts/dove-cubox.dts               |  155 ++++++++++++
 arch/arm/dts/dove.dtsi                    |  285 +++++++++++++++++++++
 arch/arm/mach-mvebu/armada-370-xp.c       |    5 +-
 arch/arm/mach-mvebu/dove.c                |    5 +-
 arch/arm/mach-mvebu/include/mach/gpio.h   |    6 +
 arch/arm/mach-mvebu/kirkwood.c            |    5 +-
 drivers/clocksource/mvebu.c               |    9 +-
 drivers/clocksource/orion.c               |    8 +-
 drivers/gpio/Kconfig                      |    8 +
 drivers/gpio/Makefile                     |    1 +
 drivers/gpio/gpio-orion.c                 |  132 ++++++++++
 drivers/led/Kconfig                       |    4 +
 drivers/led/led-gpio.c                    |   45 ++++
 drivers/spi/Kconfig                       |    4 +
 drivers/spi/Makefile                      |    1 +
 drivers/spi/mvebu_spi.c                   |  382 +++++++++++++++++++++++++++++
 18 files changed, 1119 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/dts/dove-cubox.dts
 create mode 100644 arch/arm/dts/dove.dtsi
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h
 create mode 100644 drivers/gpio/gpio-orion.c
 create mode 100644 drivers/spi/mvebu_spi.c

---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
-- 
1.7.2.5


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Re: [PATCH v2 00/10] ARM: mvebu: DT support, SPI, GPIO driver, and Dove DT

[Sascha Hauer]

On Tue, Jul 02, 2013 at 08:30:39PM +0200, Sebastian Hesselbarth wrote:
> This patch set is a first attempt to bring full DT support to Marvell
> MVEBU SoCs. It also introduces a driver for the SPI controller found
> on these SoCs with special treatment of additional functions for Dove
> and Armada 370/XP SoCs. Also a GPIO driver is added that I have written
> during OF patches.
> 
> First, current soc_init is moved from postcore initcall to core initcall,
> to allow clocks to be accessed early. Clock lookup for timers is converted
> to physbase instead of name-based lookup. Then DT support is added for both
> clocksource drivers found on Orion and Armada 370/XP SoCs, respectively.
> 
> Also, a DT-only SPI driver is added to allow access to SPI devices found
> on boards comprising Marvell SoCs. Then a DT-only GPIO driver compatible
> with MVEBU SoCs and device tree parsing for gpio-leds is added.
> 
> The last two patches extend SolidRun CuBox defconfig with a bunch of
> options for future drivers and debug commands and import DTS files from
> Linux with an additional node for the timer.
> 
> Sebastian Hesselbarth (10):
>   ARM: mvebu: move soc_init to core_initcall
>   clocksource: orion: lookup clock by physbase
>   clocksource: orion: add DT support
>   clocksource: mvebu: lookup clock by physbase
>   clocksource: mvebu: add DT support
>   spi: add Marvell MVEBU SoC SPI driver
>   GPIO: add Marvell Orion/MVEBU SoC GPIO driver
>   LED: add support for device tree parsing of gpio-leds
>   ARM: mvebu: add more options to SolidRun CuBox defconfig
>   ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

Applied this series except for the SPI driver.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v2 00/10] ARM: mvebu: DT support, SPI, GPIO driver, and Dove DT

[Sebastian Hesselbarth]

On 07/04/13 09:37, Sascha Hauer wrote:
> On Tue, Jul 02, 2013 at 08:30:39PM +0200, Sebastian Hesselbarth wrote:
>> This patch set is a first attempt to bring full DT support to Marvell
>> MVEBU SoCs. It also introduces a driver for the SPI controller found
>> on these SoCs with special treatment of additional functions for Dove
>> and Armada 370/XP SoCs. Also a GPIO driver is added that I have written
>> during OF patches.
>>
>> First, current soc_init is moved from postcore initcall to core initcall,
>> to allow clocks to be accessed early. Clock lookup for timers is converted
>> to physbase instead of name-based lookup. Then DT support is added for both
>> clocksource drivers found on Orion and Armada 370/XP SoCs, respectively.
>>
>> Also, a DT-only SPI driver is added to allow access to SPI devices found
>> on boards comprising Marvell SoCs. Then a DT-only GPIO driver compatible
>> with MVEBU SoCs and device tree parsing for gpio-leds is added.
>>
>> The last two patches extend SolidRun CuBox defconfig with a bunch of
>> options for future drivers and debug commands and import DTS files from
>> Linux with an additional node for the timer.
>>
>> Sebastian Hesselbarth (10):
>>    ARM: mvebu: move soc_init to core_initcall
>>    clocksource: orion: lookup clock by physbase
>>    clocksource: orion: add DT support
>>    clocksource: mvebu: lookup clock by physbase
>>    clocksource: mvebu: add DT support
>>    spi: add Marvell MVEBU SoC SPI driver
>>    GPIO: add Marvell Orion/MVEBU SoC GPIO driver
>>    LED: add support for device tree parsing of gpio-leds
>>    ARM: mvebu: add more options to SolidRun CuBox defconfig
>>    ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox
>
> Applied this series except for the SPI driver.

Sascha,

currently mvebu on next is broken because of missing
"OF: address and device related sync and cleanup" patch set.

I should have stated clearly that this patch set depends on
the former set.

Can you re-test the OF address/device patches and check if
they still break SPI chip select gpio on efikasb?

Sebastian

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Re: [PATCH v2 00/10] ARM: mvebu: DT support, SPI, GPIO driver, and Dove DT

[Sascha Hauer]

On Thu, Jul 04, 2013 at 01:40:24PM +0200, Sebastian Hesselbarth wrote:
> On 07/04/13 09:37, Sascha Hauer wrote:
> >On Tue, Jul 02, 2013 at 08:30:39PM +0200, Sebastian Hesselbarth wrote:
> >>This patch set is a first attempt to bring full DT support to Marvell
> >>MVEBU SoCs. It also introduces a driver for the SPI controller found
> >>on these SoCs with special treatment of additional functions for Dove
> >>and Armada 370/XP SoCs. Also a GPIO driver is added that I have written
> >>during OF patches.
> >>
> >>First, current soc_init is moved from postcore initcall to core initcall,
> >>to allow clocks to be accessed early. Clock lookup for timers is converted
> >>to physbase instead of name-based lookup. Then DT support is added for both
> >>clocksource drivers found on Orion and Armada 370/XP SoCs, respectively.
> >>
> >>Also, a DT-only SPI driver is added to allow access to SPI devices found
> >>on boards comprising Marvell SoCs. Then a DT-only GPIO driver compatible
> >>with MVEBU SoCs and device tree parsing for gpio-leds is added.
> >>
> >>The last two patches extend SolidRun CuBox defconfig with a bunch of
> >>options for future drivers and debug commands and import DTS files from
> >>Linux with an additional node for the timer.
> >>
> >>Sebastian Hesselbarth (10):
> >>   ARM: mvebu: move soc_init to core_initcall
> >>   clocksource: orion: lookup clock by physbase
> >>   clocksource: orion: add DT support
> >>   clocksource: mvebu: lookup clock by physbase
> >>   clocksource: mvebu: add DT support
> >>   spi: add Marvell MVEBU SoC SPI driver
> >>   GPIO: add Marvell Orion/MVEBU SoC GPIO driver
> >>   LED: add support for device tree parsing of gpio-leds
> >>   ARM: mvebu: add more options to SolidRun CuBox defconfig
> >>   ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox
> >
> >Applied this series except for the SPI driver.
> 
> Sascha,
> 
> currently mvebu on next is broken because of missing
> "OF: address and device related sync and cleanup" patch set.
> 
> I should have stated clearly that this patch set depends on
> the former set.
> 
> Can you re-test the OF address/device patches and check if
> they still break SPI chip select gpio on efikasb?

I applied the series and based the Marvell patches ontop of it. I
haven't tested on EfiksSB but on another board with a SPI controller, so
I assume this issue is fixed now.

Please note that your of address cleanup series adds about 1.8k to the
binary size. This doesn't sound too much, but such stuff really sums up
over time. I agree that we can't do without proper address translation
in the future, so I applied it. Just be aware in the future that we
still need a good compromise between binary size and sophisticated code.

Sascha


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Re: [PATCH v2 00/10] ARM: mvebu: DT support, SPI, GPIO driver, and Dove DT

[Sebastian Hesselbarth]

On 07/05/13 08:57, Sascha Hauer wrote:
> On Thu, Jul 04, 2013 at 01:40:24PM +0200, Sebastian Hesselbarth wrote:
>> currently mvebu on next is broken because of missing
>> "OF: address and device related sync and cleanup" patch set.
>>
>> I should have stated clearly that this patch set depends on
>> the former set.
>>
>> Can you re-test the OF address/device patches and check if
>> they still break SPI chip select gpio on efikasb?
>
> I applied the series and based the Marvell patches ontop of it. I
> haven't tested on EfiksSB but on another board with a SPI controller, so
> I assume this issue is fixed now.

Ok, I explicitly tested of_get_named_gpio with lcd-gpio driver on Dove.
If there are more issues on the now applied set, please do not hesitate
to mention it and request fixes.

> Please note that your of address cleanup series adds about 1.8k to the
> binary size. This doesn't sound too much, but such stuff really sums up
> over time. I agree that we can't do without proper address translation
> in the future, so I applied it. Just be aware in the future that we
> still need a good compromise between binary size and sophisticated code.

True. Now that I can start improving DT only mach-mvebu, I will have an
extra eye on what of the existing and imported functions can be
converted or simplified. If it leads to a significant binary size
reduction, I will send patches.

I will also prepare the last remaining node looping fix for
of_find_node_with_property later.

Thanks for the reviews!

Sebastian


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[PATCH v2 01/10] ARM: mvebu: move soc_init to core_initcall

[Sebastian Hesselbarth]

Clocks need to be accessed early for DT support, so move soc_init to
core_initcall instead of postcore_initcall.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/armada-370-xp.c |    2 +-
 arch/arm/mach-mvebu/dove.c          |    2 +-
 arch/arm/mach-mvebu/kirkwood.c      |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 2cdc3b0..1d64861 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -109,7 +109,7 @@ static int armada_370_xp_init_soc(void)
 	armada_370_xp_add_uart();
 	return 0;
 }
-postcore_initcall(armada_370_xp_init_soc);
+core_initcall(armada_370_xp_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 6e8e113..ee63917 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -132,7 +132,7 @@ static int dove_init_soc(void)
 
 	return 0;
 }
-postcore_initcall(dove_init_soc);
+core_initcall(dove_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 3e16f41..9e43dae 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -95,7 +95,7 @@ static int kirkwood_init_soc(void)
 
 	return 0;
 }
-postcore_initcall(kirkwood_init_soc);
+core_initcall(kirkwood_init_soc);
 
 void __noreturn reset_cpu(unsigned long addr)
 {
-- 
1.7.2.5


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[PATCH v2 02/10] clocksource: orion: lookup clock by physbase

[Sebastian Hesselbarth]

This converts Kirkwood and Dove SoC init to register tclk alias
for timer by physbase instead of name.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v2:
- register timer clkdev by physbase (Suggested by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/dove.c     |    3 ++-
 arch/arm/mach-mvebu/kirkwood.c |    3 ++-
 drivers/clocksource/orion.c    |    2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index ee63917..3909bf4 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -114,7 +114,7 @@ static int dove_init_clocks(void)
 	}
 
 	tclk = clk_fixed("tclk", rate);
-	return clk_register_clkdev(tclk, NULL, "orion-timer");
+	return 0;
 }
 
 static int dove_init_soc(void)
@@ -123,6 +123,7 @@ static int dove_init_soc(void)
 
 	dove_remap_mc_regs();
 	dove_init_clocks();
+	clkdev_add_physbase(tclk, (unsigned int)DOVE_TIMER_BASE, NULL);
 	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
 			   (unsigned int)DOVE_TIMER_BASE, 0x30,
 			   IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 9e43dae..2ec175a 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -78,7 +78,7 @@ static int kirkwood_init_clocks(void)
 		rate = 200000000;
 
 	tclk = clk_fixed("tclk", rate);
-	return clk_register_clkdev(tclk, NULL, "orion-timer");
+	return 0;
 }
 
 static int kirkwood_init_soc(void)
@@ -86,6 +86,7 @@ static int kirkwood_init_soc(void)
 	unsigned long phys_base, phys_size;
 
 	kirkwood_init_clocks();
+	clkdev_add_physbase(tclk, (unsigned int)KIRKWOOD_TIMER_BASE, NULL);
 	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
 			   (unsigned int)KIRKWOOD_TIMER_BASE, 0x30,
 			   IORESOURCE_MEM, NULL);
diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c
index e3db845..8817dfe 100644
--- a/drivers/clocksource/orion.c
+++ b/drivers/clocksource/orion.c
@@ -49,7 +49,7 @@ static int orion_timer_probe(struct device_d *dev)
 	uint32_t val;
 
 	timer_base = dev_request_mem_region(dev, 0);
-	tclk = clk_get(dev, "tclk");
+	tclk = clk_get(dev, NULL);
 
 	/* setup TIMER0 as free-running clock source */
 	__raw_writel(~0, timer_base + TIMER0_VAL);
-- 
1.7.2.5


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[PATCH v2 03/10] clocksource: orion: add DT support

[Sebastian Hesselbarth]

This adds device tree support to orion timer and also converts clk_get
to clk_lookup to find TCLK without device name reference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- do not use clk_lookup (Suggested by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/clocksource/orion.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c
index 8817dfe..46932f1 100644
--- a/drivers/clocksource/orion.c
+++ b/drivers/clocksource/orion.c
@@ -64,9 +64,15 @@ static int orion_timer_probe(struct device_d *dev)
 	return 0;
 }
 
+static struct of_device_id orion_timer_dt_ids[] = {
+	{ .compatible = "marvell,orion-timer", },
+	{ }
+};
+
 static struct driver_d orion_timer_driver = {
 	.name = "orion-timer",
 	.probe = orion_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(orion_timer_dt_ids),
 };
 
 static int orion_timer_init(void)
-- 
1.7.2.5


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[PATCH v2 04/10] clocksource: mvebu: lookup clock by physbase

[Sebastian Hesselbarth]

This converts Armada 370/XP SoC init to register tclk alias
for timer by physbase instead of name.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v2:
- register timer clkdev by physbase (Suggested by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/armada-370-xp.c |    3 ++-
 drivers/clocksource/mvebu.c         |    3 +--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 1d64861..24720d5 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -91,7 +91,7 @@ static int armada_xp_init_clocks(void)
 {
 	/* On Armada XP, the TCLK frequency is always 250 Mhz */
 	tclk = clk_fixed("tclk", 250000000);
-	return clk_register_clkdev(tclk, NULL, "mvebu-timer");
+	return 0;
 }
 #define armada_370_xp_init_clocks()	armada_xp_init_clocks()
 #endif
@@ -101,6 +101,7 @@ static int armada_370_xp_init_soc(void)
 	unsigned long phys_base, phys_size;
 
 	armada_370_xp_init_clocks();
+	clkdev_add_physbase(tclk, (unsigned int)ARMADA_370_XP_TIMER_BASE, NULL);
 	add_generic_device("mvebu-timer", DEVICE_ID_SINGLE, NULL,
 			   (unsigned int)ARMADA_370_XP_TIMER_BASE, 0x30,
 			   IORESOURCE_MEM, NULL);
diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c
index 8bedd99..6bd83f7 100644
--- a/drivers/clocksource/mvebu.c
+++ b/drivers/clocksource/mvebu.c
@@ -57,8 +57,7 @@ static int mvebu_timer_probe(struct device_d *dev)
 	u32 val;
 
 	timer_base = dev_request_mem_region(dev, 0);
-
-	tclk = clk_get(dev, "tclk");
+	tclk = clk_get(dev, NULL);
 
 	val = __raw_readl(timer_base + TIMER_CTRL_OFF);
 	val &= ~TIMER0_25MHZ;
-- 
1.7.2.5


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[PATCH v2 05/10] clocksource: mvebu: add DT support

[Sebastian Hesselbarth]

This adds device tree support to mvebu timer and also converts clk_get
to clk_lookup to find TCLK without device name reference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- do not use clk_lookup (Suggested by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/clocksource/mvebu.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c
index 6bd83f7..e0c85ed 100644
--- a/drivers/clocksource/mvebu.c
+++ b/drivers/clocksource/mvebu.c
@@ -77,9 +77,15 @@ static int mvebu_timer_probe(struct device_d *dev)
 	return 0;
 }
 
+static struct of_device_id mvebu_timer_dt_ids[] = {
+	{ .compatible = "marvell,armada-370-xp-timer", },
+	{ }
+};
+
 static struct driver_d mvebu_timer_driver = {
 	.name = "mvebu-timer",
 	.probe = mvebu_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_timer_dt_ids),
 };
 
 static int mvebu_timer_init(void)
-- 
1.7.2.5


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[PATCH v2 06/10] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

This adds support for the SPI controller found on Marvell MVEBU SoCs
(Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
is DT only. Compatible strings are provided for Orion (common denominator),
Armada 370/XP and Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- use dev_dbg instead of debug (Suggested by Sascha Hauer)
- check for valid reg base (Suggested by Sascha Hauer)
- whitespace fixes (Reported by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/spi/Kconfig     |    4 +
 drivers/spi/Makefile    |    1 +
 drivers/spi/mvebu_spi.c |  382 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 387 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/mvebu_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c279c21..422693c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -38,6 +38,10 @@ config DRIVER_SPI_MXS
 	depends on ARCH_IMX23 || ARCH_IMX28
 	depends on SPI
 
+config DRIVER_SPI_MVEBU
+	bool "Marvell MVEBU SoC SPI master driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_DOVE || ARCH_KIRKWOOD
+
 config DRIVER_SPI_OMAP3
 	bool "OMAP3 McSPI Master driver"
 	depends on ARCH_OMAP3 || ARCH_AM33XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 642b7ec..1036f8f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_SPI) += spi.o
 obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
+obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
 obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
 obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
 obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o
diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c
new file mode 100644
index 0000000..22110c7
--- /dev/null
+++ b/drivers/spi/mvebu_spi.c
@@ -0,0 +1,382 @@
+/*
+ * Marvell MVEBU SoC SPI controller
+ *  compatible with Dove, Kirkwood, MV78x00, Armada 370/XP
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <spi/spi.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#define SPI_IF_CTRL		0x00
+#define  IF_CS_NUM(x)		((x) << 2)
+#define  IF_CS_NUM_MASK		IF_CS_NUM(7)
+#define  IF_READ_READY		BIT(1)
+#define  IF_CS_ENABLE		BIT(0)
+#define SPI_IF_CONFIG		0x04
+#define  IF_CLK_DIV(x)		((x) << 11)
+#define  IF_CLK_DIV_MASK	(0x7 << 11)
+#define  IF_FAST_READ		BIT(10)
+#define  IF_ADDRESS_LEN_4BYTE	(3 << 8)
+#define  IF_ADDRESS_LEN_3BYTE	(2 << 8)
+#define  IF_ADDRESS_LEN_2BYTE	(1 << 8)
+#define  IF_ADDRESS_LEN_1BYTE	(0 << 8)
+#define  IF_CLK_PRESCALE_POW8	BIT(7)
+#define  IF_CLK_PRESCALE_POW4	BIT(6)
+#define  IF_TRANSFER_2BYTE	BIT(5)
+#define  IF_CLK_PRESCALE_POW2	BIT(4)
+#define  IF_CLK_PRESCALE(x)	((x) & 0x0f)
+#define  IF_CLK_PRE_PRESCALE(x)	(((((x) & 0xc) << 1) | ((x) & 0x1)) << 4)
+#define  IF_CLK_PRESCALE_MASK	(IF_CLK_PRESCALE(7) | IF_CLK_PRE_PRESCALE(7))
+#define SPI_DATA_OUT		0x08
+#define SPI_DATA_IN		0x0c
+#define SPI_INT_CAUSE		0x10
+#define SPI_INT_MASK		0x14
+#define  INT_READ_READY		BIT(0)
+
+#define SPI_SPI_MAX_CS	8
+
+struct mvebu_spi {
+	struct spi_master master;
+	void __iomem *base;
+	struct clk *clk;
+	bool data16;
+	int (*set_baudrate)(struct mvebu_spi *p, u32 speed);
+};
+
+#define priv_from_spi_device(s)	\
+	container_of(s->master, struct mvebu_spi, master);
+
+static inline int mvebu_spi_set_cs(struct mvebu_spi *p, u8 cs, u8 mode, bool en)
+{
+	u32 val;
+
+	/*
+	 * Only Armada 370/XP support up to 8 CS signals, for the
+	 * others this register bits are read-only
+	 */
+	if (cs > SPI_SPI_MAX_CS)
+		return -EINVAL;
+
+	if (mode & SPI_CS_HIGH)
+		en = !en;
+
+	val = IF_CS_NUM(cs);
+	if (en)
+		val |= IF_CS_ENABLE;
+
+	writel(val, p->base + SPI_IF_CTRL);
+
+	return 0;
+}
+
+static int mvebu_spi_set_transfer_size(struct mvebu_spi *p, int size)
+{
+	u32 val;
+
+	if (size != 8 && size != 16)
+		return -EINVAL;
+
+	p->data16 = (size == 16);
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~IF_TRANSFER_2BYTE;
+	if (p->data16)
+		val |= IF_TRANSFER_2BYTE;
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+static int mvebu_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, val;
+
+	/* standard prescaler values: 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	pscl = roundup(pscl, 2);
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl);
+
+	if (pscl > 30)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)
+static int armada_370_xp_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, pdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+
+	/* additional prescaler divider: 1, 2, 4, 8, 16, 32, 64, 128 */
+	pdiv = 0; rate = pscl;
+	while (rate > 15 && pdiv <= 7) {
+		rate /= 2;
+		pdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, pdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, pdiv);
+
+	if (rate > 15 || pdiv > 7)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRE_PRESCALE(pdiv) | IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+#if defined(ARCH_DOVE)
+static int dove_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, sdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 and 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	if (pscl > 15)
+		pscl = roundup(pscl, 2);
+
+	/* additional sclk divider: 1, 2, 4, 8, 16 */
+	sdiv = 0; rate = pscl;
+	while (rate > 30 && sdiv <= 4) {
+		rate /= 2;
+		sdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, sdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, sdiv);
+
+	if (rate > 30 || sdiv > 4)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) &
+		~(IF_CLK_DIV_MASK | IF_CLK_PRESCALE_MASK);
+
+	val |= IF_CLK_DIV(sdiv);
+	if (pscl > 15)
+		val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	else
+		val |= IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
+{
+	/*
+	 * From public datasheets of Orion SoCs, it is unclear
+	 * if the SPI controller supports setting CPOL/CPHA.
+	 * Dove has an SCK_INV but as with the other SoCs, it
+	 * is tagged with "Must be 1".
+	 *
+	 * For now, we just bail out if device requests any
+	 * other mode than SPI_MODE0.
+	 */
+
+	if ((mode & (SPI_CPOL|SPI_CPHA)) == SPI_MODE_0)
+		return 0;
+
+	pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
+
+	return -EINVAL;
+}
+
+static int mvebu_spi_setup(struct spi_device *spi)
+{
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	dev_dbg(&spi->dev, "%s: mode %02x, bits_per_word = %d, speed = %d\n",
+		__func__, spi->mode, spi->bits_per_word, spi->max_speed_hz);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_mode(priv, spi->mode);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	return priv->set_baudrate(priv, spi->max_speed_hz);
+}
+
+static inline int mvebu_spi_wait_for_read_ready(struct mvebu_spi *p)
+{
+	int timeout = 100;
+	while ((readl(p->base + SPI_IF_CTRL) & IF_READ_READY) == 0 &&
+		timeout--)
+		udelay(1);
+	if (timeout < 0)
+		return -EIO;
+	return 0;
+}
+
+static int mvebu_spi_do_transfer(struct spi_device *spi,
+				 struct spi_transfer *t)
+{
+	const u8 *txdata = t->tx_buf;
+	u8 *rxdata = t->rx_buf;
+	int ret = 0, n, inc;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	if (t->bits_per_word)
+		ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	if (t->speed_hz)
+		ret = priv->set_baudrate(priv, t->speed_hz);
+	if (ret)
+		return ret;
+
+	inc = (priv->data16) ? 2 : 1;
+	for (n = 0; n < t->len; n += inc) {
+		u32 data = 0;
+
+		if (txdata)
+			data = *txdata++;
+		if (txdata && priv->data16)
+			data |= (*txdata++ << 8);
+
+		writel(data, priv->base + SPI_DATA_OUT);
+
+		ret = mvebu_spi_wait_for_read_ready(priv);
+		if (ret) {
+			dev_err(&spi->dev, "timeout reading from device %s\n",
+				dev_name(&spi->dev));
+			return ret;
+		}
+
+		data = readl(priv->base + SPI_DATA_IN);
+
+		if (rxdata)
+			*rxdata++ = (data & 0xff);
+		if (rxdata && priv->data16)
+			*rxdata++ = (data >> 8) & 0xff;
+	}
+
+	return 0;
+}
+
+static int mvebu_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct spi_transfer *t;
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, true);
+	if (ret)
+		return ret;
+
+	msg->actual_length = 0;
+
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		ret = mvebu_spi_do_transfer(spi, t);
+		if (ret)
+			break;
+		msg->actual_length += t->len;
+	}
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static struct of_device_id mvebu_spi_dt_ids[] = {
+	{ .compatible = "marvell,orion-spi",
+	  .data = (unsigned long)&mvebu_spi_set_baudrate },
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)
+	{ .compatible = "marvell,armada-370-xp-spi",
+	  .data = (unsigned long)&armada_370_xp_spi_set_baudrate },
+#endif
+#if defined(ARCH_DOVE)
+	{ .compatible = "marvell,dove-spi",
+	  .data = (unsigned long)&dove_spi_set_baudrate },
+#endif
+	{ }
+};
+
+static int mvebu_spi_probe(struct device_d *dev)
+{
+	struct spi_master *master;
+	struct mvebu_spi *priv;
+	const struct of_device_id *match;
+	int ret = 0;
+
+	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
+	if (!match)
+		return -EINVAL;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->base = dev_request_mem_region(dev, 0);
+	if (!priv->base) {
+		ret = -EINVAL;
+		goto err_free;
+	}
+	priv->set_baudrate = (void *)match->data;
+	priv->clk = clk_lookup("tclk");
+	if (IS_ERR(priv->clk)) {
+		ret = PTR_ERR(priv->clk);
+		goto err_free;
+	}
+
+	master = &priv->master;
+	master->dev = dev;
+	master->bus_num = dev->id;
+	master->setup = mvebu_spi_setup;
+	master->transfer = mvebu_spi_transfer;
+	master->num_chipselect = 1;
+
+	if (dev->device_node)
+		spi_of_register_slaves(master, dev->device_node);
+
+	ret = spi_register_master(master);
+	if (!ret)
+		return 0;
+
+err_free:
+	free(priv);
+
+	return ret;
+}
+
+static struct driver_d mvebu_spi_driver = {
+	.name  = "mvebu-spi",
+	.probe = mvebu_spi_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_spi_dt_ids),
+};
+device_platform_driver(mvebu_spi_driver);
-- 
1.7.2.5


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Re: [PATCH v2 06/10] spi: add Marvell MVEBU SoC SPI driver

[Sascha Hauer]

On Tue, Jul 02, 2013 at 08:30:45PM +0200, Sebastian Hesselbarth wrote:
> This adds support for the SPI controller found on Marvell MVEBU SoCs
> (Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
> is DT only. Compatible strings are provided for Orion (common denominator),
> Armada 370/XP and Dove SoCs.
> 
> +#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)

These have to be CONFIG_*. Also elsewhere in this patch.

> +static int mvebu_spi_probe(struct device_d *dev)
> +{
> +	struct spi_master *master;
> +	struct mvebu_spi *priv;
> +	const struct of_device_id *match;
> +	int ret = 0;
> +
> +	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
> +	if (!match)
> +		return -EINVAL;
> +
> +	priv = xzalloc(sizeof(*priv));
> +	priv->base = dev_request_mem_region(dev, 0);
> +	if (!priv->base) {
> +		ret = -EINVAL;
> +		goto err_free;
> +	}
> +	priv->set_baudrate = (void *)match->data;
> +	priv->clk = clk_lookup("tclk");

still clk_lookup?

Sascha

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Re: [PATCH v2 06/10] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

On 07/04/13 09:36, Sascha Hauer wrote:
> On Tue, Jul 02, 2013 at 08:30:45PM +0200, Sebastian Hesselbarth wrote:
>> This adds support for the SPI controller found on Marvell MVEBU SoCs
>> (Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
>> is DT only. Compatible strings are provided for Orion (common denominator),
>> Armada 370/XP and Dove SoCs.
>>
>> +#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)
>
> These have to be CONFIG_*. Also elsewhere in this patch.

Ok will update and resend.

>> +static int mvebu_spi_probe(struct device_d *dev)
>> +{
>> +	struct spi_master *master;
>> +	struct mvebu_spi *priv;
>> +	const struct of_device_id *match;
>> +	int ret = 0;
>> +
>> +	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
>> +	if (!match)
>> +		return -EINVAL;
>> +
>> +	priv = xzalloc(sizeof(*priv));
>> +	priv->base = dev_request_mem_region(dev, 0);
>> +	if (!priv->base) {
>> +		ret = -EINVAL;
>> +		goto err_free;
>> +	}
>> +	priv->set_baudrate = (void *)match->data;
>> +	priv->clk = clk_lookup("tclk");
>
> still clk_lookup?

That was in drivers/clocksource/{orion,mvebu}.c. This slipped through.
Will be fixed in v3.

Sebastian


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[PATCH v3 1/2] ARM: mvebu: add clock aliases for spi0/spi1 on Dove

[Sebastian Hesselbarth]

This adds clock aliases for spi controllers found on Dove to allow
spi driver to get tclk frequency.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v3:
- add clock alias for Dove's spi0/spi1 devices to allow mvebu-spi
  to remove clk_lookup (Reported by Sascha Hauer)

Note: This should be the last clock aliases added here. I prefer having
a DT clk provider for those clocks instead. Either somebody is quicker
than me, or I will provide one during this or next month.

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/dove.c                   |    2 ++
 arch/arm/mach-mvebu/include/mach/dove-regs.h |    3 +++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 3909bf4..16ee116 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -124,6 +124,8 @@ static int dove_init_soc(void)
 	dove_remap_mc_regs();
 	dove_init_clocks();
 	clkdev_add_physbase(tclk, (unsigned int)DOVE_TIMER_BASE, NULL);
+	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI0_BASE, NULL);
+	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI1_BASE, NULL);
 	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
 			   (unsigned int)DOVE_TIMER_BASE, 0x30,
 			   IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-mvebu/include/mach/dove-regs.h b/arch/arm/mach-mvebu/include/mach/dove-regs.h
index 519457e..8b4319b 100644
--- a/arch/arm/mach-mvebu/include/mach/dove-regs.h
+++ b/arch/arm/mach-mvebu/include/mach/dove-regs.h
@@ -33,6 +33,9 @@
 #define DOVE_UART_BASE		(DOVE_INT_REGS_BASE + 0x12000)
 #define DOVE_UARTn_BASE(n)	(DOVE_UART_BASE + ((n) * 0x100))
 
+#define DOVE_SPI0_BASE		(DOVE_INT_REGS_BASE + 0x10600)
+#define DOVE_SPI1_BASE		(DOVE_INT_REGS_BASE + 0x14600)
+
 #define DOVE_BRIDGE_BASE	(DOVE_INT_REGS_BASE + 0x20000)
 #define  INT_REGS_BASE_MAP	0x080
 #define  BRIDGE_RSTOUT_MASK	0x108
-- 
1.7.2.5


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[PATCH v3 2/2] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

This adds support for the SPI controller found on Marvell MVEBU SoCs
(Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
is DT only. Compatible strings are provided for Orion (common denominator),
Armada 370/XP and Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- use dev_dbg instead of debug (Suggested by Sascha Hauer)
- check for valid reg base (Suggested by Sascha Hauer)
- whitespace fixes (Reported by Sascha Hauer)

v2->v3:
- use clk_get instead of clk_lookup (Reported by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/spi/Kconfig     |    4 +
 drivers/spi/Makefile    |    1 +
 drivers/spi/mvebu_spi.c |  382 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 387 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/mvebu_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c279c21..422693c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -38,6 +38,10 @@ config DRIVER_SPI_MXS
 	depends on ARCH_IMX23 || ARCH_IMX28
 	depends on SPI
 
+config DRIVER_SPI_MVEBU
+	bool "Marvell MVEBU SoC SPI master driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_DOVE || ARCH_KIRKWOOD
+
 config DRIVER_SPI_OMAP3
 	bool "OMAP3 McSPI Master driver"
 	depends on ARCH_OMAP3 || ARCH_AM33XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 642b7ec..1036f8f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_SPI) += spi.o
 obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
+obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
 obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
 obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
 obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o
diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c
new file mode 100644
index 0000000..08b8eac
--- /dev/null
+++ b/drivers/spi/mvebu_spi.c
@@ -0,0 +1,382 @@
+/*
+ * Marvell MVEBU SoC SPI controller
+ *  compatible with Dove, Kirkwood, MV78x00, Armada 370/XP
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <spi/spi.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#define SPI_IF_CTRL		0x00
+#define  IF_CS_NUM(x)		((x) << 2)
+#define  IF_CS_NUM_MASK		IF_CS_NUM(7)
+#define  IF_READ_READY		BIT(1)
+#define  IF_CS_ENABLE		BIT(0)
+#define SPI_IF_CONFIG		0x04
+#define  IF_CLK_DIV(x)		((x) << 11)
+#define  IF_CLK_DIV_MASK	(0x7 << 11)
+#define  IF_FAST_READ		BIT(10)
+#define  IF_ADDRESS_LEN_4BYTE	(3 << 8)
+#define  IF_ADDRESS_LEN_3BYTE	(2 << 8)
+#define  IF_ADDRESS_LEN_2BYTE	(1 << 8)
+#define  IF_ADDRESS_LEN_1BYTE	(0 << 8)
+#define  IF_CLK_PRESCALE_POW8	BIT(7)
+#define  IF_CLK_PRESCALE_POW4	BIT(6)
+#define  IF_TRANSFER_2BYTE	BIT(5)
+#define  IF_CLK_PRESCALE_POW2	BIT(4)
+#define  IF_CLK_PRESCALE(x)	((x) & 0x0f)
+#define  IF_CLK_PRE_PRESCALE(x)	(((((x) & 0xc) << 1) | ((x) & 0x1)) << 4)
+#define  IF_CLK_PRESCALE_MASK	(IF_CLK_PRESCALE(7) | IF_CLK_PRE_PRESCALE(7))
+#define SPI_DATA_OUT		0x08
+#define SPI_DATA_IN		0x0c
+#define SPI_INT_CAUSE		0x10
+#define SPI_INT_MASK		0x14
+#define  INT_READ_READY		BIT(0)
+
+#define SPI_SPI_MAX_CS	8
+
+struct mvebu_spi {
+	struct spi_master master;
+	void __iomem *base;
+	struct clk *clk;
+	bool data16;
+	int (*set_baudrate)(struct mvebu_spi *p, u32 speed);
+};
+
+#define priv_from_spi_device(s)	\
+	container_of(s->master, struct mvebu_spi, master);
+
+static inline int mvebu_spi_set_cs(struct mvebu_spi *p, u8 cs, u8 mode, bool en)
+{
+	u32 val;
+
+	/*
+	 * Only Armada 370/XP support up to 8 CS signals, for the
+	 * others this register bits are read-only
+	 */
+	if (cs > SPI_SPI_MAX_CS)
+		return -EINVAL;
+
+	if (mode & SPI_CS_HIGH)
+		en = !en;
+
+	val = IF_CS_NUM(cs);
+	if (en)
+		val |= IF_CS_ENABLE;
+
+	writel(val, p->base + SPI_IF_CTRL);
+
+	return 0;
+}
+
+static int mvebu_spi_set_transfer_size(struct mvebu_spi *p, int size)
+{
+	u32 val;
+
+	if (size != 8 && size != 16)
+		return -EINVAL;
+
+	p->data16 = (size == 16);
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~IF_TRANSFER_2BYTE;
+	if (p->data16)
+		val |= IF_TRANSFER_2BYTE;
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+static int mvebu_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, val;
+
+	/* standard prescaler values: 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	pscl = roundup(pscl, 2);
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl);
+
+	if (pscl > 30)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)
+static int armada_370_xp_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, pdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+
+	/* additional prescaler divider: 1, 2, 4, 8, 16, 32, 64, 128 */
+	pdiv = 0; rate = pscl;
+	while (rate > 15 && pdiv <= 7) {
+		rate /= 2;
+		pdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, pdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, pdiv);
+
+	if (rate > 15 || pdiv > 7)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRE_PRESCALE(pdiv) | IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+#if defined(ARCH_DOVE)
+static int dove_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, sdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 and 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	if (pscl > 15)
+		pscl = roundup(pscl, 2);
+
+	/* additional sclk divider: 1, 2, 4, 8, 16 */
+	sdiv = 0; rate = pscl;
+	while (rate > 30 && sdiv <= 4) {
+		rate /= 2;
+		sdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, sdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, sdiv);
+
+	if (rate > 30 || sdiv > 4)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) &
+		~(IF_CLK_DIV_MASK | IF_CLK_PRESCALE_MASK);
+
+	val |= IF_CLK_DIV(sdiv);
+	if (pscl > 15)
+		val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	else
+		val |= IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
+{
+	/*
+	 * From public datasheets of Orion SoCs, it is unclear
+	 * if the SPI controller supports setting CPOL/CPHA.
+	 * Dove has an SCK_INV but as with the other SoCs, it
+	 * is tagged with "Must be 1".
+	 *
+	 * For now, we just bail out if device requests any
+	 * other mode than SPI_MODE0.
+	 */
+
+	if ((mode & (SPI_CPOL|SPI_CPHA)) == SPI_MODE_0)
+		return 0;
+
+	pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
+
+	return -EINVAL;
+}
+
+static int mvebu_spi_setup(struct spi_device *spi)
+{
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	dev_dbg(&spi->dev, "%s: mode %02x, bits_per_word = %d, speed = %d\n",
+		__func__, spi->mode, spi->bits_per_word, spi->max_speed_hz);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_mode(priv, spi->mode);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	return priv->set_baudrate(priv, spi->max_speed_hz);
+}
+
+static inline int mvebu_spi_wait_for_read_ready(struct mvebu_spi *p)
+{
+	int timeout = 100;
+	while ((readl(p->base + SPI_IF_CTRL) & IF_READ_READY) == 0 &&
+		timeout--)
+		udelay(1);
+	if (timeout < 0)
+		return -EIO;
+	return 0;
+}
+
+static int mvebu_spi_do_transfer(struct spi_device *spi,
+				 struct spi_transfer *t)
+{
+	const u8 *txdata = t->tx_buf;
+	u8 *rxdata = t->rx_buf;
+	int ret = 0, n, inc;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	if (t->bits_per_word)
+		ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	if (t->speed_hz)
+		ret = priv->set_baudrate(priv, t->speed_hz);
+	if (ret)
+		return ret;
+
+	inc = (priv->data16) ? 2 : 1;
+	for (n = 0; n < t->len; n += inc) {
+		u32 data = 0;
+
+		if (txdata)
+			data = *txdata++;
+		if (txdata && priv->data16)
+			data |= (*txdata++ << 8);
+
+		writel(data, priv->base + SPI_DATA_OUT);
+
+		ret = mvebu_spi_wait_for_read_ready(priv);
+		if (ret) {
+			dev_err(&spi->dev, "timeout reading from device %s\n",
+				dev_name(&spi->dev));
+			return ret;
+		}
+
+		data = readl(priv->base + SPI_DATA_IN);
+
+		if (rxdata)
+			*rxdata++ = (data & 0xff);
+		if (rxdata && priv->data16)
+			*rxdata++ = (data >> 8) & 0xff;
+	}
+
+	return 0;
+}
+
+static int mvebu_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct spi_transfer *t;
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, true);
+	if (ret)
+		return ret;
+
+	msg->actual_length = 0;
+
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		ret = mvebu_spi_do_transfer(spi, t);
+		if (ret)
+			break;
+		msg->actual_length += t->len;
+	}
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static struct of_device_id mvebu_spi_dt_ids[] = {
+	{ .compatible = "marvell,orion-spi",
+	  .data = (unsigned long)&mvebu_spi_set_baudrate },
+#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)
+	{ .compatible = "marvell,armada-370-xp-spi",
+	  .data = (unsigned long)&armada_370_xp_spi_set_baudrate },
+#endif
+#if defined(ARCH_DOVE)
+	{ .compatible = "marvell,dove-spi",
+	  .data = (unsigned long)&dove_spi_set_baudrate },
+#endif
+	{ }
+};
+
+static int mvebu_spi_probe(struct device_d *dev)
+{
+	struct spi_master *master;
+	struct mvebu_spi *priv;
+	const struct of_device_id *match;
+	int ret = 0;
+
+	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
+	if (!match)
+		return -EINVAL;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->base = dev_request_mem_region(dev, 0);
+	if (!priv->base) {
+		ret = -EINVAL;
+		goto err_free;
+	}
+	priv->set_baudrate = (void *)match->data;
+	priv->clk = clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		ret = PTR_ERR(priv->clk);
+		goto err_free;
+	}
+
+	master = &priv->master;
+	master->dev = dev;
+	master->bus_num = dev->id;
+	master->setup = mvebu_spi_setup;
+	master->transfer = mvebu_spi_transfer;
+	master->num_chipselect = 1;
+
+	if (dev->device_node)
+		spi_of_register_slaves(master, dev->device_node);
+
+	ret = spi_register_master(master);
+	if (!ret)
+		return 0;
+
+err_free:
+	free(priv);
+
+	return ret;
+}
+
+static struct driver_d mvebu_spi_driver = {
+	.name  = "mvebu-spi",
+	.probe = mvebu_spi_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_spi_dt_ids),
+};
+device_platform_driver(mvebu_spi_driver);
-- 
1.7.2.5


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Re: [PATCH v3 2/2] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

On 07/04/13 13:20, Sebastian Hesselbarth wrote:
> This adds support for the SPI controller found on Marvell MVEBU SoCs
> (Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
> is DT only. Compatible strings are provided for Orion (common denominator),
> Armada 370/XP and Dove SoCs.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> v1->v2:
> - use dev_dbg instead of debug (Suggested by Sascha Hauer)
> - check for valid reg base (Suggested by Sascha Hauer)
> - whitespace fixes (Reported by Sascha Hauer)
>
> v2->v3:
> - use clk_get instead of clk_lookup (Reported by Sascha Hauer)
[...]
> +#if defined(ARCH_ARMADA_370) || defined(ARCH_ARMADA_XP)

Forgot to respect the comment given earlier on those.. will resend v4.
Sorry for that.

Sebastian


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[PATCH v4] spi: add Marvell MVEBU SoC SPI driver

[Sebastian Hesselbarth]

This adds support for the SPI controller found on Marvell MVEBU SoCs
(Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
is DT only. Compatible strings are provided for Orion (common denominator),
Armada 370/XP and Dove SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- use dev_dbg instead of debug (Suggested by Sascha Hauer)
- check for valid reg base (Suggested by Sascha Hauer)
- whitespace fixes (Reported by Sascha Hauer)

v2->v3:
- use clk_get instead of clk_lookup (Reported by Sascha Hauer)

v3->v4:
- fix missing CONFIG_ prefixes (Reported by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/spi/Kconfig     |    4 +
 drivers/spi/Makefile    |    1 +
 drivers/spi/mvebu_spi.c |  382 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 387 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/mvebu_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c279c21..422693c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -38,6 +38,10 @@ config DRIVER_SPI_MXS
 	depends on ARCH_IMX23 || ARCH_IMX28
 	depends on SPI
 
+config DRIVER_SPI_MVEBU
+	bool "Marvell MVEBU SoC SPI master driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_DOVE || ARCH_KIRKWOOD
+
 config DRIVER_SPI_OMAP3
 	bool "OMAP3 McSPI Master driver"
 	depends on ARCH_OMAP3 || ARCH_AM33XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 642b7ec..1036f8f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_SPI) += spi.o
 obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
+obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
 obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
 obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o
 obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o
diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c
new file mode 100644
index 0000000..7aaa9fe
--- /dev/null
+++ b/drivers/spi/mvebu_spi.c
@@ -0,0 +1,382 @@
+/*
+ * Marvell MVEBU SoC SPI controller
+ *  compatible with Dove, Kirkwood, MV78x00, Armada 370/XP
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <errno.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+#include <spi/spi.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#define SPI_IF_CTRL		0x00
+#define  IF_CS_NUM(x)		((x) << 2)
+#define  IF_CS_NUM_MASK		IF_CS_NUM(7)
+#define  IF_READ_READY		BIT(1)
+#define  IF_CS_ENABLE		BIT(0)
+#define SPI_IF_CONFIG		0x04
+#define  IF_CLK_DIV(x)		((x) << 11)
+#define  IF_CLK_DIV_MASK	(0x7 << 11)
+#define  IF_FAST_READ		BIT(10)
+#define  IF_ADDRESS_LEN_4BYTE	(3 << 8)
+#define  IF_ADDRESS_LEN_3BYTE	(2 << 8)
+#define  IF_ADDRESS_LEN_2BYTE	(1 << 8)
+#define  IF_ADDRESS_LEN_1BYTE	(0 << 8)
+#define  IF_CLK_PRESCALE_POW8	BIT(7)
+#define  IF_CLK_PRESCALE_POW4	BIT(6)
+#define  IF_TRANSFER_2BYTE	BIT(5)
+#define  IF_CLK_PRESCALE_POW2	BIT(4)
+#define  IF_CLK_PRESCALE(x)	((x) & 0x0f)
+#define  IF_CLK_PRE_PRESCALE(x)	(((((x) & 0xc) << 1) | ((x) & 0x1)) << 4)
+#define  IF_CLK_PRESCALE_MASK	(IF_CLK_PRESCALE(7) | IF_CLK_PRE_PRESCALE(7))
+#define SPI_DATA_OUT		0x08
+#define SPI_DATA_IN		0x0c
+#define SPI_INT_CAUSE		0x10
+#define SPI_INT_MASK		0x14
+#define  INT_READ_READY		BIT(0)
+
+#define SPI_SPI_MAX_CS	8
+
+struct mvebu_spi {
+	struct spi_master master;
+	void __iomem *base;
+	struct clk *clk;
+	bool data16;
+	int (*set_baudrate)(struct mvebu_spi *p, u32 speed);
+};
+
+#define priv_from_spi_device(s)	\
+	container_of(s->master, struct mvebu_spi, master);
+
+static inline int mvebu_spi_set_cs(struct mvebu_spi *p, u8 cs, u8 mode, bool en)
+{
+	u32 val;
+
+	/*
+	 * Only Armada 370/XP support up to 8 CS signals, for the
+	 * others this register bits are read-only
+	 */
+	if (cs > SPI_SPI_MAX_CS)
+		return -EINVAL;
+
+	if (mode & SPI_CS_HIGH)
+		en = !en;
+
+	val = IF_CS_NUM(cs);
+	if (en)
+		val |= IF_CS_ENABLE;
+
+	writel(val, p->base + SPI_IF_CTRL);
+
+	return 0;
+}
+
+static int mvebu_spi_set_transfer_size(struct mvebu_spi *p, int size)
+{
+	u32 val;
+
+	if (size != 8 && size != 16)
+		return -EINVAL;
+
+	p->data16 = (size == 16);
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~IF_TRANSFER_2BYTE;
+	if (p->data16)
+		val |= IF_TRANSFER_2BYTE;
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+static int mvebu_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, val;
+
+	/* standard prescaler values: 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	pscl = roundup(pscl, 2);
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl);
+
+	if (pscl > 30)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_ARMADA_370) || defined(CONFIG_ARCH_ARMADA_XP)
+static int armada_370_xp_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, pdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+
+	/* additional prescaler divider: 1, 2, 4, 8, 16, 32, 64, 128 */
+	pdiv = 0; rate = pscl;
+	while (rate > 15 && pdiv <= 7) {
+		rate /= 2;
+		pdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, pdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, pdiv);
+
+	if (rate > 15 || pdiv > 7)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) & ~(IF_CLK_PRESCALE_MASK);
+	val |= IF_CLK_PRE_PRESCALE(pdiv) | IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_ARCH_DOVE)
+static int dove_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
+{
+	u32 pscl, sdiv, rate, val;
+
+	/* prescaler values: 1,2,3,...,15 and 1,2,4,6,...,30 */
+	pscl = DIV_ROUND_UP(clk_get_rate(p->clk), speed);
+	if (pscl > 15)
+		pscl = roundup(pscl, 2);
+
+	/* additional sclk divider: 1, 2, 4, 8, 16 */
+	sdiv = 0; rate = pscl;
+	while (rate > 30 && sdiv <= 4) {
+		rate /= 2;
+		sdiv++;
+	}
+
+	dev_dbg(p->master.dev, "%s: clk = %lu, speed = %u, pscl = %d, sdiv = %d\n",
+		__func__, clk_get_rate(p->clk), speed, pscl, sdiv);
+
+	if (rate > 30 || sdiv > 4)
+		return -EINVAL;
+
+	val = readl(p->base + SPI_IF_CONFIG) &
+		~(IF_CLK_DIV_MASK | IF_CLK_PRESCALE_MASK);
+
+	val |= IF_CLK_DIV(sdiv);
+	if (pscl > 15)
+		val |= IF_CLK_PRESCALE_POW2 | IF_CLK_PRESCALE(pscl/2);
+	else
+		val |= IF_CLK_PRESCALE(pscl);
+	writel(val, p->base + SPI_IF_CONFIG);
+
+	return 0;
+}
+#endif
+
+static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
+{
+	/*
+	 * From public datasheets of Orion SoCs, it is unclear
+	 * if the SPI controller supports setting CPOL/CPHA.
+	 * Dove has an SCK_INV but as with the other SoCs, it
+	 * is tagged with "Must be 1".
+	 *
+	 * For now, we just bail out if device requests any
+	 * other mode than SPI_MODE0.
+	 */
+
+	if ((mode & (SPI_CPOL|SPI_CPHA)) == SPI_MODE_0)
+		return 0;
+
+	pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
+
+	return -EINVAL;
+}
+
+static int mvebu_spi_setup(struct spi_device *spi)
+{
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	dev_dbg(&spi->dev, "%s: mode %02x, bits_per_word = %d, speed = %d\n",
+		__func__, spi->mode, spi->bits_per_word, spi->max_speed_hz);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_mode(priv, spi->mode);
+	if (ret)
+		return ret;
+	ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	return priv->set_baudrate(priv, spi->max_speed_hz);
+}
+
+static inline int mvebu_spi_wait_for_read_ready(struct mvebu_spi *p)
+{
+	int timeout = 100;
+	while ((readl(p->base + SPI_IF_CTRL) & IF_READ_READY) == 0 &&
+		timeout--)
+		udelay(1);
+	if (timeout < 0)
+		return -EIO;
+	return 0;
+}
+
+static int mvebu_spi_do_transfer(struct spi_device *spi,
+				 struct spi_transfer *t)
+{
+	const u8 *txdata = t->tx_buf;
+	u8 *rxdata = t->rx_buf;
+	int ret = 0, n, inc;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	if (t->bits_per_word)
+		ret = mvebu_spi_set_transfer_size(priv, spi->bits_per_word);
+	if (ret)
+		return ret;
+
+	if (t->speed_hz)
+		ret = priv->set_baudrate(priv, t->speed_hz);
+	if (ret)
+		return ret;
+
+	inc = (priv->data16) ? 2 : 1;
+	for (n = 0; n < t->len; n += inc) {
+		u32 data = 0;
+
+		if (txdata)
+			data = *txdata++;
+		if (txdata && priv->data16)
+			data |= (*txdata++ << 8);
+
+		writel(data, priv->base + SPI_DATA_OUT);
+
+		ret = mvebu_spi_wait_for_read_ready(priv);
+		if (ret) {
+			dev_err(&spi->dev, "timeout reading from device %s\n",
+				dev_name(&spi->dev));
+			return ret;
+		}
+
+		data = readl(priv->base + SPI_DATA_IN);
+
+		if (rxdata)
+			*rxdata++ = (data & 0xff);
+		if (rxdata && priv->data16)
+			*rxdata++ = (data >> 8) & 0xff;
+	}
+
+	return 0;
+}
+
+static int mvebu_spi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct spi_transfer *t;
+	int ret;
+	struct mvebu_spi *priv = priv_from_spi_device(spi);
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, true);
+	if (ret)
+		return ret;
+
+	msg->actual_length = 0;
+
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		ret = mvebu_spi_do_transfer(spi, t);
+		if (ret)
+			break;
+		msg->actual_length += t->len;
+	}
+
+	ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, false);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static struct of_device_id mvebu_spi_dt_ids[] = {
+	{ .compatible = "marvell,orion-spi",
+	  .data = (unsigned long)&mvebu_spi_set_baudrate },
+#if defined(CONFIG_ARCH_ARMADA_370) || defined(CONFIG_ARCH_ARMADA_XP)
+	{ .compatible = "marvell,armada-370-xp-spi",
+	  .data = (unsigned long)&armada_370_xp_spi_set_baudrate },
+#endif
+#if defined(CONFIG_ARCH_DOVE)
+	{ .compatible = "marvell,dove-spi",
+	  .data = (unsigned long)&dove_spi_set_baudrate },
+#endif
+	{ }
+};
+
+static int mvebu_spi_probe(struct device_d *dev)
+{
+	struct spi_master *master;
+	struct mvebu_spi *priv;
+	const struct of_device_id *match;
+	int ret = 0;
+
+	match = of_match_node(mvebu_spi_dt_ids, dev->device_node);
+	if (!match)
+		return -EINVAL;
+
+	priv = xzalloc(sizeof(*priv));
+	priv->base = dev_request_mem_region(dev, 0);
+	if (!priv->base) {
+		ret = -EINVAL;
+		goto err_free;
+	}
+	priv->set_baudrate = (void *)match->data;
+	priv->clk = clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		ret = PTR_ERR(priv->clk);
+		goto err_free;
+	}
+
+	master = &priv->master;
+	master->dev = dev;
+	master->bus_num = dev->id;
+	master->setup = mvebu_spi_setup;
+	master->transfer = mvebu_spi_transfer;
+	master->num_chipselect = 1;
+
+	if (dev->device_node)
+		spi_of_register_slaves(master, dev->device_node);
+
+	ret = spi_register_master(master);
+	if (!ret)
+		return 0;
+
+err_free:
+	free(priv);
+
+	return ret;
+}
+
+static struct driver_d mvebu_spi_driver = {
+	.name  = "mvebu-spi",
+	.probe = mvebu_spi_probe,
+	.of_compatible = DRV_OF_COMPAT(mvebu_spi_dt_ids),
+};
+device_platform_driver(mvebu_spi_driver);
-- 
1.7.2.5


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Re: [PATCH v4] spi: add Marvell MVEBU SoC SPI driver

[Sascha Hauer]

On Thu, Jul 04, 2013 at 01:33:35PM +0200, Sebastian Hesselbarth wrote:
> This adds support for the SPI controller found on Marvell MVEBU SoCs
> (Dove, Kirkwood, Discovery Innovation, and Armada 370/XP). Current driver
> is DT only. Compatible strings are provided for Orion (common denominator),
> Armada 370/XP and Dove SoCs.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Applied, thanks

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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[PATCH RESEND] ARM: mvebu: add clock aliases for spi0/spi1 on Dove

[Sebastian Hesselbarth]

This adds clock aliases for spi controllers found on Dove to allow
spi driver to get tclk frequency.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
@Sascha: I forgot to update MVEBU SPI v4 patch numbering to indicate
that this patch is also required for the SPI driver to find its clock
with clk_get instead of clk_fixup.

As stated in the original patch for SPI clock aliases, I am not planing
to add any more clk aliases like this but prefer to work on DT clk
provider first.

Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/mach-mvebu/dove.c                   |    2 ++
 arch/arm/mach-mvebu/include/mach/dove-regs.h |    3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 3909bf4..16ee116 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -124,6 +124,8 @@ static int dove_init_soc(void)
 	dove_remap_mc_regs();
 	dove_init_clocks();
 	clkdev_add_physbase(tclk, (unsigned int)DOVE_TIMER_BASE, NULL);
+	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI0_BASE, NULL);
+	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI1_BASE, NULL);
 	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
 			   (unsigned int)DOVE_TIMER_BASE, 0x30,
 			   IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-mvebu/include/mach/dove-regs.h b/arch/arm/mach-mvebu/include/mach/dove-regs.h
index 519457e..8b4319b 100644
--- a/arch/arm/mach-mvebu/include/mach/dove-regs.h
+++ b/arch/arm/mach-mvebu/include/mach/dove-regs.h
@@ -33,6 +33,9 @@
 #define DOVE_UART_BASE		(DOVE_INT_REGS_BASE + 0x12000)
 #define DOVE_UARTn_BASE(n)	(DOVE_UART_BASE + ((n) * 0x100))
 
+#define DOVE_SPI0_BASE		(DOVE_INT_REGS_BASE + 0x10600)
+#define DOVE_SPI1_BASE		(DOVE_INT_REGS_BASE + 0x14600)
+
 #define DOVE_BRIDGE_BASE	(DOVE_INT_REGS_BASE + 0x20000)
 #define  INT_REGS_BASE_MAP	0x080
 #define  BRIDGE_RSTOUT_MASK	0x108
-- 
1.7.10.4


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Re: [PATCH RESEND] ARM: mvebu: add clock aliases for spi0/spi1 on Dove

[Sascha Hauer]

On Fri, Jul 05, 2013 at 11:21:45PM +0200, Sebastian Hesselbarth wrote:
> This adds clock aliases for spi controllers found on Dove to allow
> spi driver to get tclk frequency.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> @Sascha: I forgot to update MVEBU SPI v4 patch numbering to indicate
> that this patch is also required for the SPI driver to find its clock
> with clk_get instead of clk_fixup.
> 
> As stated in the original patch for SPI clock aliases, I am not planing
> to add any more clk aliases like this but prefer to work on DT clk
> provider first.
> 
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: barebox@lists.infradead.org

Applied, thanks

Sascha

> ---
>  arch/arm/mach-mvebu/dove.c                   |    2 ++
>  arch/arm/mach-mvebu/include/mach/dove-regs.h |    3 +++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
> index 3909bf4..16ee116 100644
> --- a/arch/arm/mach-mvebu/dove.c
> +++ b/arch/arm/mach-mvebu/dove.c
> @@ -124,6 +124,8 @@ static int dove_init_soc(void)
>  	dove_remap_mc_regs();
>  	dove_init_clocks();
>  	clkdev_add_physbase(tclk, (unsigned int)DOVE_TIMER_BASE, NULL);
> +	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI0_BASE, NULL);
> +	clkdev_add_physbase(tclk, (unsigned int)DOVE_SPI1_BASE, NULL);
>  	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
>  			   (unsigned int)DOVE_TIMER_BASE, 0x30,
>  			   IORESOURCE_MEM, NULL);
> diff --git a/arch/arm/mach-mvebu/include/mach/dove-regs.h b/arch/arm/mach-mvebu/include/mach/dove-regs.h
> index 519457e..8b4319b 100644
> --- a/arch/arm/mach-mvebu/include/mach/dove-regs.h
> +++ b/arch/arm/mach-mvebu/include/mach/dove-regs.h
> @@ -33,6 +33,9 @@
>  #define DOVE_UART_BASE		(DOVE_INT_REGS_BASE + 0x12000)
>  #define DOVE_UARTn_BASE(n)	(DOVE_UART_BASE + ((n) * 0x100))
>  
> +#define DOVE_SPI0_BASE		(DOVE_INT_REGS_BASE + 0x10600)
> +#define DOVE_SPI1_BASE		(DOVE_INT_REGS_BASE + 0x14600)
> +
>  #define DOVE_BRIDGE_BASE	(DOVE_INT_REGS_BASE + 0x20000)
>  #define  INT_REGS_BASE_MAP	0x080
>  #define  BRIDGE_RSTOUT_MASK	0x108
> -- 
> 1.7.10.4
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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[PATCH v2 07/10] GPIO: add Marvell Orion/MVEBU SoC GPIO driver

[Sebastian Hesselbarth]

This adds a DT only driver for the GPIO controller found on Marvell
Orion/MVEBU SoCs (Armada 370/XP, Dove, Kirkwood, MV78x00, Orion5x).

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/Kconfig                        |    1 +
 arch/arm/mach-mvebu/include/mach/gpio.h |    6 ++
 drivers/gpio/Kconfig                    |    8 ++
 drivers/gpio/Makefile                   |    1 +
 drivers/gpio/gpio-orion.c               |  132 +++++++++++++++++++++++++++++++
 5 files changed, 148 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h
 create mode 100644 drivers/gpio/gpio-orion.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cfb82b0..c60deb4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -83,6 +83,7 @@ config ARCH_MVEBU
 	bool "Marvell EBU platforms"
 	select COMMON_CLK
 	select CLKDEV_LOOKUP
+	select GPIOLIB
 	select HAS_DEBUG_LL
 
 config ARCH_MXS
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 0000000..fee693e
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e976db4..d5ac532 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -30,6 +30,14 @@ config GPIO_GENERIC_PLATFORM
 config GPIO_IMX
 	def_bool ARCH_IMX
 
+config GPIO_ORION
+	bool "GPIO support for Marvell Orion/MVEBU SoCs"
+	depends on ARCH_MVEBU
+	help
+	  Say yes here to add the driver for the GPIO controller
+	  found on Marvell Orion and MVEBU SoCs (Armada 370/XP,
+	  Dove, Kirkwood, MV78x00, Orion5x).
+
 config GPIO_PL061
 	bool "PrimeCell PL061 GPIO support"
 	depends on ARM_AMBA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c1ec5bf..adb668f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_GPIO_BCM2835)	+= gpio-bcm2835.o
 obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
 obj-$(CONFIG_GPIO_GENERIC)	+= gpio-generic.o
 obj-$(CONFIG_GPIO_IMX)		+= gpio-imx.o
+obj-$(CONFIG_GPIO_ORION)	+= gpio-orion.o
 obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o
 obj-$(CONFIG_GPIO_STMPE)	+= gpio-stmpe.o
 obj-$(CONFIG_GPIO_TEGRA)	+= gpio-tegra.o
diff --git a/drivers/gpio/gpio-orion.c b/drivers/gpio/gpio-orion.c
new file mode 100644
index 0000000..855763e
--- /dev/null
+++ b/drivers/gpio/gpio-orion.c
@@ -0,0 +1,132 @@
+/*
+ * Marvell Orion/MVEBU SoC GPIO driver
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <malloc.h>
+
+struct orion_gpio_regs {
+	u32 data_o;
+	u32 data_o_en;
+	u32 blink;
+	u32 data_i_pol;
+	u32 data_i;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level_mask;
+};
+
+struct orion_gpio_chip {
+	struct gpio_chip chip;
+	struct orion_gpio_regs __iomem *regs;
+};
+
+static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned off)
+{
+	struct orion_gpio_chip *gpio =
+		container_of(chip, struct orion_gpio_chip, chip);
+	writel(readl(&gpio->regs->data_o_en) | BIT(off),
+		&gpio->regs->data_o_en);
+	return 0;
+}
+
+static int orion_gpio_direction_output(
+	struct gpio_chip *chip, unsigned off, int value)
+{
+	struct orion_gpio_chip *gpio =
+		container_of(chip, struct orion_gpio_chip, chip);
+	gpio->chip.ops->set(chip, off, value);
+	writel(readl(&gpio->regs->data_o_en) & ~BIT(off),
+		&gpio->regs->data_o_en);
+	return 0;
+}
+
+static int orion_gpio_get_value(struct gpio_chip *chip, unsigned off)
+{
+	struct orion_gpio_chip *gpio =
+		container_of(chip, struct orion_gpio_chip, chip);
+	return (readl(&gpio->regs->data_i) & BIT(off)) ? 1 : 0;
+}
+
+static void orion_gpio_set_value(
+	struct gpio_chip *chip, unsigned off, int value)
+{
+	struct orion_gpio_chip *gpio =
+		container_of(chip, struct orion_gpio_chip, chip);
+	u32 val;
+
+	val = readl(&gpio->regs->data_o);
+	if (value)
+		val |= BIT(off);
+	else
+		val &= ~BIT(off);
+	writel(val, &gpio->regs->data_o);
+}
+
+static struct gpio_ops orion_gpio_ops = {
+	.direction_input = orion_gpio_direction_input,
+	.direction_output = orion_gpio_direction_output,
+	.get = orion_gpio_get_value,
+	.set = orion_gpio_set_value,
+};
+
+static int orion_gpio_probe(struct device_d *dev)
+{
+	struct orion_gpio_chip *gpio;
+
+	dev->id = of_alias_get_id(dev->device_node, "gpio");
+	if (dev->id < 0)
+		return dev->id;
+
+	gpio = xzalloc(sizeof(*gpio));
+	gpio->regs = dev_request_mem_region(dev, 0);
+	if (!gpio->regs) {
+		free(gpio);
+		return -EINVAL;
+	}
+	gpio->chip.dev = dev;
+	gpio->chip.ops = &orion_gpio_ops;
+	gpio->chip.base = dev->id * 32;
+	gpio->chip.ngpio = 32;
+	of_property_read_u32(dev->device_node, "ngpios", &gpio->chip.ngpio);
+
+	gpiochip_add(&gpio->chip);
+
+	dev_dbg(dev, "probed gpio%d with base %d\n", dev->id, gpio->chip.base);
+
+	return 0;
+}
+
+static struct of_device_id orion_gpio_dt_ids[] = {
+	{ .compatible = "marvell,orion-gpio", },
+	{ }
+};
+
+static struct driver_d orion_gpio_driver = {
+	.name = "orion-gpio",
+	.probe = orion_gpio_probe,
+	.of_compatible = DRV_OF_COMPAT(orion_gpio_dt_ids),
+};
+
+static int orion_gpio_init(void)
+{
+	return platform_driver_register(&orion_gpio_driver);
+}
+postcore_initcall(orion_gpio_init);
-- 
1.7.2.5


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[PATCH v2 08/10] LED: add support for device tree parsing of gpio-leds

[Sebastian Hesselbarth]

This adds a driver option to probe GPIO LEDs from device tree compatible
with "gpio-leds" device tree nodes.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 drivers/led/Kconfig    |    4 ++++
 drivers/led/led-gpio.c |   45 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 0 deletions(-)

diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 8ca6ab8..3ead82e 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -7,6 +7,10 @@ config LED_GPIO
 	bool "gpio LED support"
 	depends on GENERIC_GPIO
 
+config LED_GPIO_OF
+	bool "support parsing gpio LEDs from device tree"
+	depends on LED_GPIO && OFTREE
+
 config LED_GPIO_RGB
 	bool "gpio rgb LED support"
 	depends on LED_GPIO
diff --git a/drivers/led/led-gpio.c b/drivers/led/led-gpio.c
index 08dc9ba..54f9264 100644
--- a/drivers/led/led-gpio.c
+++ b/drivers/led/led-gpio.c
@@ -18,8 +18,10 @@
  *
  */
 #include <common.h>
+#include <init.h>
 #include <led.h>
 #include <gpio.h>
+#include <of_gpio.h>
 
 static void led_gpio_set(struct led *led, unsigned int value)
 {
@@ -194,3 +196,46 @@ void led_gpio_rgb_unregister(struct gpio_led *led)
 	led_unregister(&led->led);
 }
 #endif /* CONFIG_LED_GPIO_RGB */
+
+#ifdef CONFIG_LED_GPIO_OF
+
+static int led_gpio_of_probe(struct device_d *dev)
+{
+	struct device_node *child;
+
+	for_each_child_of_node(dev->device_node, child) {
+		struct gpio_led *gled;
+		enum of_gpio_flags flags;
+		int gpio;
+
+		gpio = of_get_named_gpio_flags(child, "gpios", 0, &flags);
+		if (gpio < 0)
+			continue;
+
+		gled = xzalloc(sizeof(*gled));
+		gled->led.name = xstrdup(child->name);
+		gled->gpio = gpio;
+		gled->active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+		dev_dbg(dev, "register led %s on gpio%d, active_low = %d\n",
+			gled->led.name, gled->gpio, gled->active_low);
+
+		led_gpio_register(gled);
+	}
+
+	return 0;
+}
+
+static struct of_device_id led_gpio_of_ids[] = {
+	{ .compatible = "gpio-leds", },
+	{ }
+};
+
+static struct driver_d led_gpio_of_driver = {
+	.name  = "gpio-leds",
+	.probe = led_gpio_of_probe,
+	.of_compatible = DRV_OF_COMPAT(led_gpio_of_ids),
+};
+device_platform_driver(led_gpio_of_driver);
+
+#endif /* CONFIG LED_GPIO_OF */
-- 
1.7.2.5


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[PATCH v2 09/10] ARM: mvebu: add more options to SolidRun CuBox defconfig

[Sebastian Hesselbarth]

This patch updates SolidRun CuBox defconfig to more commands also valueable
for debug. Also, all future driver subsystems are enabled to ease driver
development.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- add CONFIG_CONSOLE_ACTIVATE_NONE (Suggested by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/configs/solidrun_cubox_defconfig |   72 +++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/solidrun_cubox_defconfig b/arch/arm/configs/solidrun_cubox_defconfig
index 1a27d81..61195ae 100644
--- a/arch/arm/configs/solidrun_cubox_defconfig
+++ b/arch/arm/configs/solidrun_cubox_defconfig
@@ -1,9 +1,81 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="dove-cubox"
 CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_DOVE=y
 CONFIG_AEABI=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
 CONFIG_DEBUG_LL=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_BASENAME=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_LOADY=y
 CONFIG_CMD_LOADS=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA224SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
 CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_WD=y
+CONFIG_OFDEVICE=y
 CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SPI_MVEBU=y
+CONFIG_I2C=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_DISK_AHCI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_LED=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_WATCHDOG=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BZLIB=y
+CONFIG_LZO_DECOMPRESS=y
-- 
1.7.2.5


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[PATCH v2 10/10] ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

[Sebastian Hesselbarth]

This imports dove.dtsi and dove-cubox.dts from Linux kernel with timer
node added.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v1->v2:
- add linux,stdoutpath property to chose node (Suggested by Sascha Hauer)
- whitespace fixes (Reported by Sascha Hauer)

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: barebox@lists.infradead.org
---
 arch/arm/dts/dove-cubox.dts |  155 +++++++++++++++++++++++
 arch/arm/dts/dove.dtsi      |  285 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 440 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/dove-cubox.dts
 create mode 100644 arch/arm/dts/dove.dtsi

diff --git a/arch/arm/dts/dove-cubox.dts b/arch/arm/dts/dove-cubox.dts
new file mode 100644
index 0000000..12a4642
--- /dev/null
+++ b/arch/arm/dts/dove-cubox.dts
@@ -0,0 +1,155 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	compatible = "solidrun,cubox", "marvell,dove";
+	model = "SolidRun CuBox";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x3f000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdoutpath = "/soc@f1000000/serial@12000";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_gpio_18>;
+		pinctrl-names = "default";
+
+		power {
+			label = "Power";
+			gpios = <&gpio0 18 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 1 0>;
+		};
+	};
+
+	clocks {
+		/* 25MHz reference crystal */
+		ref25: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+
+	video-card {
+		compatible = "marvell,dove-video-card";
+		reg = <0x3f000000 0x1000000>;
+		marvell,external-encoder = <&tda19988>;
+	};
+};
+
+&uart0 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&lcd0 {
+	status = "okay";
+	clocks = <&si5351 0>;
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	si5351: clock-generator {
+		compatible = "silabs,si5351a-msop";
+		reg = <0x60>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#clock-cells = <1>;
+
+		/* connect xtal input to 25MHz reference */
+		clocks = <&ref25>;
+
+		/* connect xtal input as source of pll0 and pll1 */
+		silabs,pll-source = <0 0>, <1 0>;
+
+		clkout0 {
+			reg = <0>;
+			silabs,drive-strength = <8>;
+			silabs,multisynth-source = <0>;
+			silabs,clock-source = <0>;
+			silabs,pll-master;
+		};
+
+		clkout1 {
+			reg = <1>;
+			silabs,drive-strength = <8>;
+			silabs,multisynth-source = <1>;
+			silabs,clock-source = <0>;
+			silabs,pll-master;
+		};
+
+		clkout2 {
+			reg = <2>;
+			silabs,multisynth-source = <1>;
+			silabs,clock-source = <0>;
+		};
+	};
+
+	tda19988: hdmi-encoder@70 {
+		compatible = "nxp,tda1998x";
+		reg = <0x70>;
+	};
+};
+
+&sdio0 {
+	status = "okay";
+	bus-width = <4>;
+	/* sdio0 card detect is connected to wrong pin on CuBox */
+	cd-gpios = <&gpio0 12 1>;
+};
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash@0 {
+		compatible = "winbond,w25q32", "m25p80";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>;
+	pinctrl-names = "default";
+
+	pmx_gpio_1: pmx-gpio-1 {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_gpio_12: pmx-gpio-12 {
+		marvell,pins = "mpp12";
+		marvell,function = "gpio";
+	};
+
+	pmx_gpio_18: pmx-gpio-18 {
+		marvell,pins = "mpp18";
+		marvell,function = "gpio";
+	};
+};
diff --git a/arch/arm/dts/dove.dtsi b/arch/arm/dts/dove.dtsi
new file mode 100644
index 0000000..4ee8db0
--- /dev/null
+++ b/arch/arm/dts/dove.dtsi
@@ -0,0 +1,285 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "marvell,dove";
+	model = "Marvell Armada 88AP510 SoC";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
+	soc@f1000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&intc>;
+
+		ranges = <0xc8000000 0xc8000000 0x0100000   /* CESA SRAM   1M */
+		          0xe0000000 0xe0000000 0x8000000   /* PCIe0 Mem 128M */
+		          0xe8000000 0xe8000000 0x8000000   /* PCIe1 Mem 128M */
+		          0xf0000000 0xf0000000 0x0100000   /* ScratchPad  1M */
+		          0x00000000 0xf1000000 0x1000000   /* SB/NB regs 16M */
+		          0xf2000000 0xf2000000 0x0100000   /* PCIe0 I/O   1M */
+		          0xf2100000 0xf2100000 0x0100000   /* PCIe0 I/O   1M */
+		          0xf8000000 0xf8000000 0x8000000>; /* BootROM   128M */
+
+		l2: l2-cache {
+			compatible = "marvell,tauros2-cache";
+			marvell,tauros2-cache-features = <0>;
+		};
+
+		timer: timer@20300 {
+			compatible = "marvell,orion-timer";
+                        reg = <0x20300 0x30>;
+		};
+
+		intc: interrupt-controller@20204 {
+			compatible = "marvell,orion-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x20204 0x04>, <0x20214 0x04>;
+		};
+
+		core_clk: core-clocks@d0214 {
+			compatible = "marvell,dove-core-clock";
+			reg = <0xd0214 0x4>;
+			#clock-cells = <1>;
+		};
+
+		gate_clk: clock-gating-control@d0038 {
+			compatible = "marvell,dove-gating-clock";
+			reg = <0xd0038 0x4>;
+			clocks = <&core_clk 0>;
+			#clock-cells = <1>;
+		};
+
+		thermal: thermal@d001c {
+			compatible = "marvell,dove-thermal";
+			reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+		};
+
+		uart0: serial@12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x20>;
+			reg-shift = <2>;
+			interrupts = <7>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart1: serial@12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x20>;
+			reg-shift = <2>;
+			interrupts = <8>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart2: serial@12200 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x20>;
+			reg-shift = <2>;
+			interrupts = <9>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		uart3: serial@12300 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x20>;
+			reg-shift = <2>;
+			interrupts = <10>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		gpio0: gpio@d0400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0400 0x20>;
+			ngpios = <32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <12>, <13>, <14>, <60>;
+		};
+
+		gpio1: gpio@d0420 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0420 0x20>;
+			ngpios = <32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <61>;
+		};
+
+		gpio2: gpio@e8400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xe8400 0x0c>;
+			ngpios = <8>;
+		};
+
+		pinctrl: pinctrl@d0200 {
+			compatible = "marvell,dove-pinctrl";
+			reg = <0xd0200 0x10>;
+			clocks = <&gate_clk 22>;
+		};
+
+		spi0: spi@10600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			interrupts = <6>;
+			reg = <0x10600 0x28>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		spi1: spi@14600 {
+			compatible = "marvell,dove-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			interrupts = <5>;
+			reg = <0x14600 0x28>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11>;
+			clock-frequency = <400000>;
+			timeout-ms = <1000>;
+			clocks = <&core_clk 0>;
+			status = "disabled";
+		};
+
+		ehci0: usb-host@50000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x50000 0x1000>;
+			interrupts = <24>;
+			clocks = <&gate_clk 0>;
+			status = "okay";
+		};
+
+		ehci1: usb-host@51000 {
+			compatible = "marvell,orion-ehci";
+			reg = <0x51000 0x1000>;
+			interrupts = <25>;
+			clocks = <&gate_clk 1>;
+			status = "okay";
+		};
+
+		sdio0: sdio@92000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x92000 0x100>;
+			interrupts = <35>, <37>;
+			clocks = <&gate_clk 8>;
+			status = "disabled";
+		};
+
+		sdio1: sdio@90000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x90000 0x100>;
+			interrupts = <36>, <38>;
+			clocks = <&gate_clk 9>;
+			status = "disabled";
+		};
+
+		sata0: sata@a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x2400>;
+			interrupts = <62>;
+			clocks = <&gate_clk 3>;
+			nr-ports = <1>;
+			status = "disabled";
+		};
+
+		rtc@d8500 {
+			compatible = "marvell,orion-rtc";
+			reg = <0xd8500 0x20>;
+		};
+
+		crypto: crypto@30000 {
+			compatible = "marvell,orion-crypto";
+			reg = <0x30000 0x10000>,
+			      <0xc8000000 0x800>;
+			reg-names = "regs", "sram";
+			interrupts = <31>;
+			clocks = <&gate_clk 15>;
+			status = "okay";
+		};
+
+		xor0: dma-engine@60800 {
+			compatible = "marvell,orion-xor";
+			reg = <0x60800 0x100
+			       0x60a00 0x100>;
+			clocks = <&gate_clk 23>;
+			status = "okay";
+
+			channel0 {
+				interrupts = <39>;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+
+			channel1 {
+				interrupts = <40>;
+				dmacap,memset;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+		};
+
+		xor1: dma-engine@60900 {
+			compatible = "marvell,orion-xor";
+			reg = <0x60900 0x100
+			       0x60b00 0x100>;
+			clocks = <&gate_clk 24>;
+			status = "okay";
+
+			channel0 {
+				interrupts = <42>;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+
+			channel1 {
+				interrupts = <43>;
+				dmacap,memset;
+				dmacap,memcpy;
+				dmacap,xor;
+			};
+		};
+
+		lcd0: lcd-controller@820000 {
+			compatible = "marvell,dove-lcd";
+			reg = <0x820000 0x200>;
+			interrupts = <47>;
+			clocks = <0>;
+			status = "disabled";
+		};
+
+		lcd1: lcd-controller@810000 {
+			compatible = "marvell,dove-lcd";
+			reg = <0x810000 0x200>;
+			interrupts = <46>;
+			clocks = <0>;
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.2.5


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Re: [PATCH v2 10/10] ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

[Sascha Hauer]

On Tue, Jul 02, 2013 at 08:30:49PM +0200, Sebastian Hesselbarth wrote:
> This imports dove.dtsi and dove-cubox.dts from Linux kernel with timer
> node added.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Applied with two small changes

First I added dove-cubox.dtb to the Makefile

> diff --git a/arch/arm/dts/dove-cubox.dts b/arch/arm/dts/dove-cubox.dts
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdoutpath = "/soc@f1000000/serial@12000";
> +	};

Then I learned something about dtc. The above can be written as

	linux,stdoutpath = &uart0;

Which expands to the nodes full path.

Sascha

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Re: [PATCH v2 10/10] ARM: mvebu: import DT files for Dove SoC and SolidRun CuBox

[Sebastian Hesselbarth]

On 07/04/13 09:32, Sascha Hauer wrote:
> On Tue, Jul 02, 2013 at 08:30:49PM +0200, Sebastian Hesselbarth wrote:
>> This imports dove.dtsi and dove-cubox.dts from Linux kernel with timer
>> node added.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
> Applied with two small changes
>
> First I added dove-cubox.dtb to the Makefile
>
>> diff --git a/arch/arm/dts/dove-cubox.dts b/arch/arm/dts/dove-cubox.dts
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +		linux,stdoutpath = "/soc@f1000000/serial@12000";
>> +	};
>
> Then I learned something about dtc. The above can be written as
>
> 	linux,stdoutpath = &uart0;
>
> Which expands to the nodes full path.

Great, I was going to think about adding linux,stdoutpath-phandle
just because of the freaking long name above.

Also, yesterday I realized that I updated solidrun_cubox_defconfig
with CONFIG_CONSOLE_ACTIVATE_NONE=y. Leaves it with no console.
I will retest with your changes but maybe I haven't yet fully
understood the dependencies here.

Sebastian


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