* [PATCH 1/8] ARM: am33xx: Add SRAM0 address/size defines
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 2/8] ARM: omap: fix omap_save_bootinfo Sascha Hauer
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index bd55da4..22ef3ca 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -115,11 +115,10 @@
#define AM33XX_VTP1_CTRL_REG 0x48140E10
/* OCMC */
-#define AM33XX_SRAM0_SIZE (0x1B400) /* 109 KB */
+#define AM33XX_SRAM0_START 0x402f0400
+#define AM33XX_SRAM0_SIZE (SZ_64K - SZ_1K)
#define AM33XX_SRAM_GPMC_STACK_SIZE (0x40)
-#define AM33XX_LOW_LEVEL_SRAM_STACK (AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE - 4)
-
/* DDR offsets */
#define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000
#define AM33XX_DDR_IO_CTRL 0x44E10E04
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 2/8] ARM: omap: fix omap_save_bootinfo
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
2013-08-22 20:36 ` [PATCH 1/8] ARM: am33xx: Add SRAM0 address/size defines Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 3/8] ARM: am33xx: Make uart0 mux init callable during early init Sascha Hauer
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
omap_save_bootinfo derefences the argument passed to barebox without
checking it for validity. This breaks 2nd stage booting where r0
is undefined. The best we can do is to check whether the pointer is
somewhere in SRAM and is word aligned. This at least makes sure that
we do not oops. This introduces SoC specific xxx_save_bootinfo variants
since the SRAM addresses/sizes differ between SoCs.
Additionally fix the prototype for omap_save_bootinfo. It uses r0, so
it must be passed this variable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/archosg9/lowlevel.c | 3 ++-
arch/arm/boards/beagle/lowlevel.c | 3 ++-
arch/arm/boards/beaglebone/lowlevel.c | 3 ++-
arch/arm/boards/omap343xdsp/lowlevel.c | 3 ++-
arch/arm/boards/omap3evm/lowlevel.c | 3 ++-
arch/arm/boards/panda/lowlevel.c | 3 ++-
arch/arm/boards/pcm049/lowlevel.c | 3 ++-
arch/arm/boards/pcm051/lowlevel.c | 2 +-
arch/arm/boards/phycard-a-l1/lowlevel.c | 3 ++-
arch/arm/boards/phycard-a-xl2/lowlevel.c | 3 ++-
arch/arm/mach-omap/include/mach/am33xx-generic.h | 17 +++++++++++++++++
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 2 ++
arch/arm/mach-omap/include/mach/generic.h | 2 +-
arch/arm/mach-omap/include/mach/omap3-generic.h | 21 +++++++++++++++++++++
arch/arm/mach-omap/include/mach/omap4-generic.h | 21 +++++++++++++++++++++
15 files changed, 81 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/mach-omap/include/mach/omap3-generic.h
create mode 100644 arch/arm/mach-omap/include/mach/omap4-generic.h
diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index 8be345b..6c93992 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -17,6 +17,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -67,7 +68,7 @@ static noinline void archosg9_init_lowlevel(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
index ef7e3c0..ad46386 100644
--- a/arch/arm/boards/beagle/lowlevel.c
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -6,6 +6,7 @@
#include <mach/control.h>
#include <mach/generic.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
#include <mach/syslib.h>
@@ -182,7 +183,7 @@ static int beagle_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index d871ca1..e6c490a 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -10,6 +10,7 @@
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/am33xx-mux.h>
+#include <mach/am33xx-generic.h>
#include <mach/wdt.h>
/* UART Defines */
@@ -251,7 +252,7 @@ static int beaglebone_board_init(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ am33xx_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
index 61b7f99..fcb9571 100644
--- a/arch/arm/boards/omap343xdsp/lowlevel.c
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -10,6 +10,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
/**
@@ -549,7 +550,7 @@ static int sdp343x_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
index ea92835..98f1476 100644
--- a/arch/arm/boards/omap3evm/lowlevel.c
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -9,6 +9,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
@@ -162,7 +163,7 @@ static int omap3_evm_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index a21d559..205aaaf 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -80,7 +81,7 @@ static void noinline panda_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 07cc1d7..4f39600 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -110,7 +111,7 @@ static void noinline pcm049_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c
index f4a1742..2ed4667 100644
--- a/arch/arm/boards/pcm051/lowlevel.c
+++ b/arch/arm/boards/pcm051/lowlevel.c
@@ -210,7 +210,7 @@ static int pcm051_board_init(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ am33xx_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
index 7855040..353b58f 100644
--- a/arch/arm/boards/phycard-a-l1/lowlevel.c
+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c
@@ -10,6 +10,7 @@
#include <mach/control.h>
#include <mach/syslib.h>
#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
#include <mach/sys_info.h>
/* Slower full frequency range default timings for x32 operation */
@@ -253,7 +254,7 @@ static int pcaal1_board_init(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap3_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 9a794b7..1ddf8a0 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -23,6 +23,7 @@
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
#include <mach/omap4-clock.h>
#include <mach/syslib.h>
#include <asm/barebox-arm.h>
@@ -90,7 +91,7 @@ static noinline void pcaaxl2_init_lowlevel(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
- omap_save_bootinfo();
+ omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index ba69caf..d9d2efb 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -1,6 +1,23 @@
#ifndef __MACH_AM33XX_GENERIC_H
#define __MACH_AM33XX_GENERIC_H
+#include <mach/generic.h>
+#include <mach/am33xx-silicon.h>
+
int am33xx_register_ethaddr(int eth_id, int mac_id);
+static inline void am33xx_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < AM33XX_SRAM0_START)
+ return;
+ if (i > AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
#endif /* __MACH_AM33XX_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 22ef3ca..f198a9a 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -17,6 +17,8 @@
#ifndef __ASM_ARCH_AM33XX_H
#define __ASM_ARCH_AM33XX_H
+#include <sizes.h>
+
/** AM335x Internal Bus Base addresses */
#define AM33XX_L4_WKUP_BASE 0x44C00000
#define AM33XX_L4_PER_BASE 0x48000000
diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h
index 3314faf..ec7a4ef 100644
--- a/arch/arm/mach-omap/include/mach/generic.h
+++ b/arch/arm/mach-omap/include/mach/generic.h
@@ -50,6 +50,6 @@ static inline int omap_set_barebox_part(struct omap_barebox_part *part)
#endif
extern uint32_t omap_bootinfo[3];
-void omap_save_bootinfo(void);
+void omap_save_bootinfo(void *data);
#endif
diff --git a/arch/arm/mach-omap/include/mach/omap3-generic.h b/arch/arm/mach-omap/include/mach/omap3-generic.h
new file mode 100644
index 0000000..7f0da4e
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap3-generic.h
@@ -0,0 +1,21 @@
+#ifndef __MACH_OMAP3_GENERIC_H
+#define __MACH_OMAP3_GENERIC_H
+
+#include <mach/generic.h>
+#include <mach/omap3-silicon.h>
+
+static inline void omap3_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < OMAP3_SRAM_BASE)
+ return;
+ if (i > OMAP3_SRAM_BASE + SZ_64K)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
+#endif /* __MACH_OMAP3_GENERIC_H */
diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h
new file mode 100644
index 0000000..44f5a12
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/omap4-generic.h
@@ -0,0 +1,21 @@
+#ifndef __MACH_OMAP4_GENERIC_H
+#define __MACH_OMAP4_GENERIC_H
+
+#include <mach/generic.h>
+#include <mach/omap4-silicon.h>
+
+static inline void omap4_save_bootinfo(uint32_t *info)
+{
+ unsigned long i = (unsigned long)info;
+
+ if (i & 0x3)
+ return;
+ if (i < OMAP44XX_SRAM_BASE)
+ return;
+ if (i > OMAP44XX_SRAM_BASE + SZ_64K)
+ return;
+
+ omap_save_bootinfo(info);
+}
+
+#endif /* __MACH_OMAP4_GENERIC_H */
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/8] ARM: am33xx: Make uart0 mux init callable during early init
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
2013-08-22 20:36 ` [PATCH 1/8] ARM: am33xx: Add SRAM0 address/size defines Sascha Hauer
2013-08-22 20:36 ` [PATCH 2/8] ARM: omap: fix omap_save_bootinfo Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 4/8] ARM: cpuinfo: display the core name and version Sascha Hauer
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
The am33xx pinmux functions use global variables which are not
accessible during early init. To make the setup of an early debug
uart easier convert am33xx_enable_uart0_pin_mux to not use global
variables.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/am33xx_mux.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c
index 8318713..e92bc27 100644
--- a/arch/arm/mach-omap/am33xx_mux.c
+++ b/arch/arm/mach-omap/am33xx_mux.c
@@ -21,12 +21,6 @@
#define MUX_CFG(value, offset) \
__raw_writel(value, (AM33XX_CTRL_BASE + offset));
-static const __maybe_unused struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
static const __maybe_unused struct module_pin_mux uart2_pin_mux[] = {
{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART2_RXD */
{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
@@ -299,7 +293,12 @@ void am33xx_enable_i2c2_pin_mux(void)
void am33xx_enable_uart0_pin_mux(void)
{
- configure_module_pin_mux(uart0_pin_mux);
+ /*
+ * no global variables for UART to make this callable
+ * during early init.
+ */
+ MUX_CFG((MODE(0) | PULLUP_EN | RXACTIVE), OFFSET(uart0_rxd));
+ MUX_CFG((MODE(0) | PULLUDEN), OFFSET(uart0_txd));
}
void am33xx_enable_uart2_pin_mux(void)
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 4/8] ARM: cpuinfo: display the core name and version
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
` (2 preceding siblings ...)
2013-08-22 20:36 ` [PATCH 3/8] ARM: am33xx: Make uart0 mux init callable during early init Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 5/8] ARM: am33xx: implement cpu revision decoding Sascha Hauer
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
From: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cpuinfo.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index 8aea4b4..260d47b 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -31,6 +31,12 @@
#define CPU_ARCH_ARMv6 8
#define CPU_ARCH_ARMv7 9
+#define ARM_CPU_PART_CORTEX_A5 0xC050
+#define ARM_CPU_PART_CORTEX_A7 0xC070
+#define ARM_CPU_PART_CORTEX_A8 0xC080
+#define ARM_CPU_PART_CORTEX_A9 0xC090
+#define ARM_CPU_PART_CORTEX_A15 0xC0F0
+
static void decode_cache(unsigned long size)
{
int linelen = 1 << ((size & 0x3) + 3);
@@ -154,6 +160,33 @@ static int do_cpuinfo(int argc, char *argv[])
printf("implementer: %s\narchitecture: %s\n",
implementer, architecture);
+ if (cpu_arch == CPU_ARCH_ARMv7) {
+ unsigned int major, minor;
+ char *part;
+ major = (mainid >> 20) & 0xf;
+ minor = mainid & 0xf;
+ switch (mainid & 0xfff0) {
+ case ARM_CPU_PART_CORTEX_A5:
+ part = "Cortex-A5";
+ break;
+ case ARM_CPU_PART_CORTEX_A7:
+ part = "Cortex-A7";
+ break;
+ case ARM_CPU_PART_CORTEX_A8:
+ part = "Cortex-A8";
+ break;
+ case ARM_CPU_PART_CORTEX_A9:
+ part = "Cortex-A9";
+ break;
+ case ARM_CPU_PART_CORTEX_A15:
+ part = "Cortex-A15";
+ break;
+ default:
+ part = "unknown";
+ }
+ printf("core: %s r%up%u\n", part, major, minor);
+ }
+
if (cache & (1 << 24)) {
/* separate I/D cache */
printf("I-cache: ");
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 5/8] ARM: am33xx: implement cpu revision decoding
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
` (3 preceding siblings ...)
2013-08-22 20:36 ` [PATCH 4/8] ARM: cpuinfo: display the core name and version Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 6/8] ARM: am33xx: beaglebone: split out DDR2 init for BB White Sascha Hauer
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
From: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/am33xx_generic.c | 34 +++++++++++++++++++++++-
arch/arm/mach-omap/include/mach/am33xx-generic.h | 2 ++
arch/arm/mach-omap/include/mach/am33xx-silicon.h | 1 +
arch/arm/mach-omap/include/mach/sys_info.h | 10 +++++--
4 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index a653ef7..558d069 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
- * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de>
+ * (C) Copyright 2012-2013 Jan Luebbe <j.luebbe@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -38,6 +38,38 @@ void __noreturn reset_cpu(unsigned long addr)
}
/**
+ * @brief Extract the AM33xx ES revision
+ *
+ * The significance of the CPU revision depends upon the cpu type.
+ * Latest known revision is considered default.
+ *
+ * @return silicon version
+ */
+u32 am33xx_get_cpu_rev(void)
+{
+ u32 version, retval;
+
+ version = (readl(AM33XX_IDCODE_REG) >> 28) & 0xF;
+
+ switch (version) {
+ case 0:
+ retval = AM335X_ES1_0;
+ break;
+ case 1:
+ retval = AM335X_ES2_0;
+ break;
+ case 2:
+ /*
+ * Fall through the default case.
+ */
+ default:
+ retval = AM335X_ES2_1;
+ }
+
+ return retval;
+}
+
+/**
* @brief Get the upper address of current execution
*
* we can use this to figure out if we are running in SRAM /
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
index d9d2efb..ec22ad2 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-generic.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -6,6 +6,8 @@
int am33xx_register_ethaddr(int eth_id, int mac_id);
+u32 am33xx_get_cpu_rev(void);
+
static inline void am33xx_save_bootinfo(uint32_t *info)
{
unsigned long i = (unsigned long)info;
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index f198a9a..9328cc9 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -71,6 +71,7 @@
/* CTRL */
#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
+#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600)
/* Watchdog Timer */
#define AM33XX_WDT_BASE 0x44E35000
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index 4d9b138..fce5895 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -40,6 +40,7 @@
#define CPU_1710 0x1710
#define CPU_2420 0x2420
#define CPU_2430 0x2430
+#define CPU_3350 0x3350
#define CPU_3430 0x3430
#define CPU_3630 0x3630
@@ -54,6 +55,10 @@
#define OMAP34XX_ES3 cpu_revision(CPU_3430, 3)
#define OMAP34XX_ES3_1 cpu_revision(CPU_3430, 4)
+#define AM335X_ES1_0 cpu_revision(CPU_3350, 0)
+#define AM335X_ES2_0 cpu_revision(CPU_3350, 1)
+#define AM335X_ES2_1 cpu_revision(CPU_3350, 2)
+
#define OMAP36XX_ES1 cpu_revision(CPU_3630, 0)
#define OMAP36XX_ES1_1 cpu_revision(CPU_3630, 1)
#define OMAP36XX_ES1_2 cpu_revision(CPU_3630, 2)
@@ -76,8 +81,9 @@
/**
* Hawkeye definitions to identify silicon families
*/
-#define OMAP_HAWKEYE_34XX 0xB7AE
-#define OMAP_HAWKEYE_36XX 0xB891
+#define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */
+#define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */
+#define OMAP_HAWKEYE_335X 0xB944 /* AM335x */
/** These are implemented by the System specific code in omapX-generic.c */
u32 get_cpu_type(void);
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 6/8] ARM: am33xx: beaglebone: split out DDR2 init for BB White
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
` (4 preceding siblings ...)
2013-08-22 20:36 ` [PATCH 5/8] ARM: am33xx: implement cpu revision decoding Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 7/8] ARM: am33xx: beaglebone: configure I2C EEPROM Sascha Hauer
2013-08-22 20:36 ` [PATCH 8/8] ARM: am33xx: beaglebone: add support for beaglebone black with DDR3 RAM Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
From: Jan Luebbe <jlu@pengutronix.de>
To make place for the DDR3 init for the BB black.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/beaglebone/Makefile | 2 +-
arch/arm/boards/beaglebone/ddr.h | 1 +
arch/arm/boards/beaglebone/ddr2.c | 178 ++++++++++++++++++++++++++++++++++
arch/arm/boards/beaglebone/lowlevel.c | 175 +--------------------------------
4 files changed, 184 insertions(+), 172 deletions(-)
create mode 100644 arch/arm/boards/beaglebone/ddr.h
create mode 100644 arch/arm/boards/beaglebone/ddr2.c
diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
index 092c31d..7ec0c8b 100644
--- a/arch/arm/boards/beaglebone/Makefile
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -1,2 +1,2 @@
-lwl-y += lowlevel.o
+lwl-y += lowlevel.o ddr2.o
obj-y += board.o
diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h
new file mode 100644
index 0000000..d2f0c95
--- /dev/null
+++ b/arch/arm/boards/beaglebone/ddr.h
@@ -0,0 +1 @@
+void beaglebone_config_ddr2(void);
diff --git a/arch/arm/boards/beaglebone/ddr2.c b/arch/arm/boards/beaglebone/ddr2.c
new file mode 100644
index 0000000..42a099d
--- /dev/null
+++ b/arch/arm/boards/beaglebone/ddr2.c
@@ -0,0 +1,178 @@
+#include <init.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/armlinux.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT 0x80000000
+#define EMIF_SDRAM 0x00004650
+#define EMIF_PHYCFG 0x2
+#define DDR_PHY_RESET (0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN 0x1
+#define DDR_PHY_READY (0x1 << 2)
+#define VTP_CTRL_READY (0x1 << 5)
+#define VTP_CTRL_ENABLE (0x1 << 6)
+#define VTP_CTRL_LOCK_EN (0x1 << 4)
+#define VTP_CTRL_START_EN (0x1)
+#define DDR2_RATIO 0x80 /* for mDDR */
+#define CMD_FORCE 0x00 /* common #def */
+#define CMD_DELAY 0x00
+
+#define EMIF_READ_LATENCY 0x05
+#define EMIF_TIM1 0x0666B3D6
+#define EMIF_TIM2 0x143731DA
+#define EMIF_TIM3 0x00000347
+#define EMIF_SDCFG 0x43805332
+#define EMIF_SDREF 0x0000081a
+#define DDR2_DLL_LOCK_DIFF 0x0
+#define DDR2_RD_DQS 0x12
+#define DDR2_PHY_FIFO_WE 0x80
+
+#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_WR_DQS 0x00
+#define DDR2_PHY_WRLVL 0x00
+#define DDR2_PHY_GATELVL 0x00
+#define DDR2_PHY_WR_DATA 0x40
+#define PHY_RANK0_DELAY 0x01
+#define PHY_DLL_LOCK_DIFF 0x0
+#define DDR_IOCTRL_VALUE 0x18B
+
+static void beaglebone_data_macro_config_ddr2(int dataMacroNum)
+{
+ u32 BaseAddrOffset = 0x00;
+
+ if (dataMacroNum == 1)
+ BaseAddrOffset = 0xA4;
+
+ __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_RD_DQS>>2,
+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_WR_DQS>>2,
+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+ (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_WRLVL>>2,
+ (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+ (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_GATELVL>>2,
+ (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_FIFO_WE>>2,
+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_WR_DATA>>2,
+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
+ __raw_writel(PHY_DLL_LOCK_DIFF,
+ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
+}
+
+static void beaglebone_cmd_macro_config_ddr2(void)
+{
+ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
+}
+
+static void beaglebone_config_vtp_ddr2(void)
+{
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
+ AM33XX_VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
+ AM33XX_VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
+ AM33XX_VTP0_CTRL_REG);
+
+ /* Poll for READY */
+ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
+}
+
+static void beaglebone_config_emif_ddr2(void)
+{
+ u32 i;
+
+ /*Program EMIF0 CFG Registers*/
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+ for (i = 0; i < 5000; i++) {
+
+ }
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+}
+
+void beaglebone_config_ddr2(void)
+{
+ enable_ddr_clocks();
+
+ beaglebone_config_vtp_ddr2();
+
+ beaglebone_cmd_macro_config_ddr2();
+ beaglebone_data_macro_config_ddr2(0);
+ beaglebone_data_macro_config_ddr2(1);
+
+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
+
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
+
+ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
+ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
+
+ beaglebone_config_emif_ddr2();
+}
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index e6c490a..e869a7b 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -13,6 +13,8 @@
#include <mach/am33xx-generic.h>
#include <mach/wdt.h>
+#include "ddr.h"
+
/* UART Defines */
#define UART_SYSCFG_OFFSET (0x54)
#define UART_SYSSTS_OFFSET (0x58)
@@ -21,176 +23,6 @@
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
-/* AM335X EMIF Register values */
-#define EMIF_SDMGT 0x80000000
-#define EMIF_SDRAM 0x00004650
-#define EMIF_PHYCFG 0x2
-#define DDR_PHY_RESET (0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN 0x1
-#define DDR_PHY_READY (0x1 << 2)
-#define VTP_CTRL_READY (0x1 << 5)
-#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_LOCK_EN (0x1 << 4)
-#define VTP_CTRL_START_EN (0x1)
-#define DDR2_RATIO 0x80 /* for mDDR */
-#define CMD_FORCE 0x00 /* common #def */
-#define CMD_DELAY 0x00
-
-#define EMIF_READ_LATENCY 0x05
-#define EMIF_TIM1 0x0666B3D6
-#define EMIF_TIM2 0x143731DA
-#define EMIF_TIM3 0x00000347
-#define EMIF_SDCFG 0x43805332
-#define EMIF_SDREF 0x0000081a
-#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RD_DQS 0x12
-#define DDR2_PHY_FIFO_WE 0x80
-
-#define DDR2_INVERT_CLKOUT 0x00
-#define DDR2_WR_DQS 0x00
-#define DDR2_PHY_WRLVL 0x00
-#define DDR2_PHY_GATELVL 0x00
-#define DDR2_PHY_WR_DATA 0x40
-#define PHY_RANK0_DELAY 0x01
-#define PHY_DLL_LOCK_DIFF 0x0
-#define DDR_IOCTRL_VALUE 0x18B
-
-static void beaglebone_data_macro_config(int dataMacroNum)
-{
- u32 BaseAddrOffset = 0x00;
-
- if (dataMacroNum == 1)
- BaseAddrOffset = 0xA4;
-
- __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_RD_DQS>>2,
- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_WR_DQS>>2,
- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
- (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_WRLVL>>2,
- (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
- (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_GATELVL>>2,
- (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_FIFO_WE>>2,
- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
- __raw_writel(DDR2_PHY_WR_DATA>>2,
- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
- __raw_writel(PHY_DLL_LOCK_DIFF,
- (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
-}
-
-static void beaglebone_cmd_macro_config(void)
-{
- __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
-
- __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
-
- __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
- __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
- __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
-}
-
-static void beaglebone_config_vtp(void)
-{
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
- AM33XX_VTP0_CTRL_REG);
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
- AM33XX_VTP0_CTRL_REG);
- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
- AM33XX_VTP0_CTRL_REG);
-
- /* Poll for READY */
- while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
-}
-
-static void beaglebone_config_emif_ddr2(void)
-{
- u32 i;
-
- /*Program EMIF0 CFG Registers*/
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
- for (i = 0; i < 5000; i++) {
-
- }
-
- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-}
-
-static void beaglebone_config_ddr(void)
-{
- enable_ddr_clocks();
-
- beaglebone_config_vtp();
-
- beaglebone_cmd_macro_config();
- beaglebone_data_macro_config(0);
- beaglebone_data_macro_config(1);
-
- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
-
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
-
- __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
- __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
-
- beaglebone_config_emif_ddr2();
-}
-
/*
* early system init of muxing and clocks.
*/
@@ -201,7 +33,8 @@ void beaglebone_sram_init(void)
/* Setup the PLLs and the clocks for the peripherals */
pll_init(MPUPLL_M_500);
- beaglebone_config_ddr();
+ if (get_cpu_rev() == AM335X_ES1_0)
+ beaglebone_config_ddr2();
/* UART softreset */
uart_base = AM33XX_UART0_BASE;
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 7/8] ARM: am33xx: beaglebone: configure I2C EEPROM
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
` (5 preceding siblings ...)
2013-08-22 20:36 ` [PATCH 6/8] ARM: am33xx: beaglebone: split out DDR2 init for BB White Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
2013-08-22 20:36 ` [PATCH 8/8] ARM: am33xx: beaglebone: add support for beaglebone black with DDR3 RAM Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
From: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/beaglebone/board.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index b3f39ea..ccb7004 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -97,11 +97,20 @@ static void beaglebone_eth_init(void)
am33xx_add_cpsw(&cpsw_data);
}
+static struct i2c_board_info i2c0_devices[] = {
+ {
+ I2C_BOARD_INFO("24c256", 0x50)
+ },
+};
+
static int beaglebone_devices_init(void)
{
am33xx_add_mmc0(NULL);
am33xx_enable_i2c0_pin_mux();
+ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+ am33xx_add_i2c0(NULL);
+
beaglebone_eth_init();
armlinux_set_bootparams((void *)0x80000100);
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 8/8] ARM: am33xx: beaglebone: add support for beaglebone black with DDR3 RAM
2013-08-22 20:36 [PATCH] OMAP fixes and beaglebone black support Sascha Hauer
` (6 preceding siblings ...)
2013-08-22 20:36 ` [PATCH 7/8] ARM: am33xx: beaglebone: configure I2C EEPROM Sascha Hauer
@ 2013-08-22 20:36 ` Sascha Hauer
7 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2013-08-22 20:36 UTC (permalink / raw)
To: barebox
From: Jan Luebbe <jlu@pengutronix.de>
Also allow configuration of the DDR PLL from board code
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/beaglebone/Makefile | 2 +-
arch/arm/boards/beaglebone/beaglebone.h | 9 ++
arch/arm/boards/beaglebone/board.c | 46 ++++++-
arch/arm/boards/beaglebone/ddr.h | 1 +
arch/arm/boards/beaglebone/ddr3.c | 155 +++++++++++++++++++++++
arch/arm/boards/beaglebone/lowlevel.c | 19 ++-
arch/arm/mach-omap/am33xx_clock.c | 9 +-
arch/arm/mach-omap/include/mach/am33xx-clock.h | 5 +-
arch/arm/mach-omap/include/mach/am33xx-devices.h | 6 +
9 files changed, 238 insertions(+), 14 deletions(-)
create mode 100644 arch/arm/boards/beaglebone/beaglebone.h
create mode 100644 arch/arm/boards/beaglebone/ddr3.c
diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
index 7ec0c8b..eb2ffec 100644
--- a/arch/arm/boards/beaglebone/Makefile
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -1,2 +1,2 @@
-lwl-y += lowlevel.o ddr2.o
+lwl-y += lowlevel.o ddr2.o ddr3.o
obj-y += board.o
diff --git a/arch/arm/boards/beaglebone/beaglebone.h b/arch/arm/boards/beaglebone/beaglebone.h
new file mode 100644
index 0000000..25c5b0e
--- /dev/null
+++ b/arch/arm/boards/beaglebone/beaglebone.h
@@ -0,0 +1,9 @@
+#ifndef __BOARD_BEAGLEBONE_H
+#define __BOARD_BEAGLEBONE_H
+
+static inline int is_beaglebone_black(void)
+{
+ return am33xx_get_cpu_rev() != AM335X_ES1_0;
+}
+
+#endif /* __BOARD_BEAGLEBONE_H */
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index ccb7004..dcaa573 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -26,6 +26,8 @@
#include <init.h>
#include <driver.h>
#include <envfs.h>
+#include <environment.h>
+#include <globalvar.h>
#include <sizes.h>
#include <io.h>
#include <ns16550.h>
@@ -49,6 +51,8 @@
#include <mach/am33xx-generic.h>
#include <mach/cpsw.h>
+#include "beaglebone.h"
+
#ifdef CONFIG_DRIVER_SERIAL_NS16550
/**
@@ -68,7 +72,10 @@ console_initcall(beaglebone_console_init);
static int beaglebone_mem_init(void)
{
- omap_add_ram0(SZ_256M);
+ if (is_beaglebone_black())
+ omap_add_ram0(SZ_512M);
+ else
+ omap_add_ram0(SZ_256M);
return 0;
}
@@ -103,19 +110,54 @@ static struct i2c_board_info i2c0_devices[] = {
},
};
+static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE)}, /* MMC1_DAT4 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {-1},
+};
+
static int beaglebone_devices_init(void)
{
+ am33xx_enable_mmc0_pin_mux();
am33xx_add_mmc0(NULL);
+ if (is_beaglebone_black()) {
+ configure_module_pin_mux(mmc1_pin_mux);
+ am33xx_add_mmc1(NULL);
+ }
+
am33xx_enable_i2c0_pin_mux();
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
am33xx_add_i2c0(NULL);
beaglebone_eth_init();
+ return 0;
+}
+device_initcall(beaglebone_devices_init);
+
+static int beaglebone_env_init(void)
+{
+ int black = is_beaglebone_black();
+
+#if defined(CONFIG_GLOBALVAR)
+ globalvar_add_simple("board.variant");
+ setenv("global.board.variant", black ? "boneblack" : "bone");
+#endif
+
+ printf("detected 'BeagleBone %s'\n", black ? "Black" : "White");
+
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_BEAGLEBONE);
return 0;
}
-device_initcall(beaglebone_devices_init);
+late_initcall(beaglebone_env_init);
diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h
index d2f0c95..46c2504 100644
--- a/arch/arm/boards/beaglebone/ddr.h
+++ b/arch/arm/boards/beaglebone/ddr.h
@@ -1 +1,2 @@
void beaglebone_config_ddr2(void);
+void beaglebone_config_ddr3(void);
diff --git a/arch/arm/boards/beaglebone/ddr3.c b/arch/arm/boards/beaglebone/ddr3.c
new file mode 100644
index 0000000..643a94d
--- /dev/null
+++ b/arch/arm/boards/beaglebone/ddr3.c
@@ -0,0 +1,155 @@
+#include <init.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/armlinux.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT 0x80000000
+#define EMIF_SDRAM 0x00004650
+#define EMIF_PHYCFG 0x2
+#define DDR_PHY_RESET (0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN 0x1
+#define DDR_PHY_READY (0x1 << 2)
+#define VTP_CTRL_READY (0x1 << 5)
+#define VTP_CTRL_ENABLE (0x1 << 6)
+#define VTP_CTRL_LOCK_EN (0x1 << 4)
+#define VTP_CTRL_START_EN (0x1)
+#define DDR2_RATIO 0x80 /* for mDDR */
+#define CMD_FORCE 0x00 /* common #def */
+#define CMD_DELAY 0x00
+
+#define EMIF_READ_LATENCY 0x100007
+#define EMIF_TIM1 0x0AAAD4DB
+#define EMIF_TIM2 0x266B7FDA
+#define EMIF_TIM3 0x501F867F
+#define EMIF_SDCFG 0x61C05332
+#define EMIF_SDREF 0xC30
+#define ZQ_CFG 0x50074BE4
+#define DDR2_DLL_LOCK_DIFF 0x1
+#define DDR2_RD_DQS 0x38
+#define DDR2_WR_DQS 0x44
+#define DDR2_PHY_FIFO_WE 0x94
+#define DDR2_PHY_WR_DATA 0x7D
+
+#define DDR2_INVERT_CLKOUT 0x0
+#define PHY_RANK0_DELAY 0x01
+#define PHY_DLL_LOCK_DIFF 0x0
+#define DDR_IOCTRL_VALUE 0x18B
+
+static void beaglebone_data_macro_config_ddr3(int dataMacroNum)
+{
+ u32 BaseAddrOffset = 0x00;
+
+ if (dataMacroNum == 1)
+ BaseAddrOffset = 0xA4;
+
+ __raw_writel(DDR2_RD_DQS,
+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_WR_DQS,
+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_FIFO_WE,
+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(DDR2_PHY_WR_DATA,
+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
+ __raw_writel(PHY_DLL_LOCK_DIFF,
+ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
+}
+
+static void beaglebone_cmd_macro_config_ddr3(void)
+{
+ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
+
+ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
+ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
+ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
+}
+
+static void beaglebone_config_vtp_ddr3(void)
+{
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
+ AM33XX_VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
+ AM33XX_VTP0_CTRL_REG);
+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
+ AM33XX_VTP0_CTRL_REG);
+
+ /* Poll for READY */
+ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
+}
+
+static void beaglebone_config_emif_ddr3(void)
+{
+ u32 i;
+
+ /*Program EMIF0 CFG Registers*/
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+ for (i = 0; i < 5000; i++) {
+
+ }
+
+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+}
+
+void beaglebone_config_ddr3(void)
+{
+ enable_ddr_clocks();
+
+ beaglebone_config_vtp_ddr3();
+
+ beaglebone_cmd_macro_config_ddr3();
+ beaglebone_data_macro_config_ddr3(0);
+ beaglebone_data_macro_config_ddr3(1);
+
+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
+
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
+
+ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
+ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
+
+ beaglebone_config_emif_ddr3();
+}
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index e869a7b..0cc9179 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -14,6 +14,7 @@
#include <mach/wdt.h>
#include "ddr.h"
+#include "beaglebone.h"
/* UART Defines */
#define UART_SYSCFG_OFFSET (0x54)
@@ -31,10 +32,13 @@ void beaglebone_sram_init(void)
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
- pll_init(MPUPLL_M_500);
-
- if (get_cpu_rev() == AM335X_ES1_0)
+ if (is_beaglebone_black()) {
+ pll_init(MPUPLL_M_500, DDRPLL_M_400);
+ beaglebone_config_ddr3();
+ } else {
+ pll_init(MPUPLL_M_500, DDRPLL_M_266);
beaglebone_config_ddr2();
+ }
/* UART softreset */
uart_base = AM33XX_UART0_BASE;
@@ -85,11 +89,18 @@ static int beaglebone_board_init(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
+ unsigned sdram;
+
am33xx_save_bootinfo(data);
arm_cpu_lowlevel_init();
beaglebone_board_init();
- barebox_arm_entry(0x80000000, SZ_256M, 0);
+ if (is_beaglebone_black())
+ sdram = SZ_512M;
+ else
+ sdram = SZ_256M;
+
+ barebox_arm_entry(0x80000000, sdram, 0);
}
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
index 9928e9f..e0ba197 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -248,7 +248,7 @@ static void per_pll_config(void)
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
}
-static void ddr_pll_config(void)
+static void ddr_pll_config(int ddrpll_M)
{
u32 clkmode, clksel, div_m2;
@@ -263,7 +263,7 @@ static void ddr_pll_config(void)
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
clksel = clksel & (~0x7ffff);
- clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
+ clksel = clksel | ((ddrpll_M << 0x8) | DDRPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 & 0xFFFFFFE0;
@@ -288,18 +288,17 @@ void enable_ddr_clocks(void)
PRCM_L3_GCLK_ACTIVITY));
/* Poll if module is functional */
while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
-
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
-void pll_init(int mpupll_M)
+void pll_init(int mpupll_M, int ddrpll_M)
{
mpu_pll_config(mpupll_M);
core_pll_config();
per_pll_config();
- ddr_pll_config();
+ ddr_pll_config(ddrpll_M);
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h
index 968509e..3f86d14 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h
@@ -53,7 +53,8 @@
/* DDR Freq is 266 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M 266
+#define DDRPLL_M_266 266
+#define DDRPLL_M_400 400
#define DDRPLL_N (OSC - 1)
#define DDRPLL_M2 1
@@ -187,7 +188,7 @@
#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
-extern void pll_init(int mpupll_M);
+extern void pll_init(int mpupll_M, int ddrpll_M);
extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h
index 6a4d901..6691980 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-devices.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h
@@ -31,6 +31,12 @@ static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data *
AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
+static inline struct device_d *am33xx_add_mmc1(struct omap_hsmmc_platform_data *pdata)
+{
+ return add_generic_device("omap4-hsmmc", 1, NULL,
+ AM33XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
+}
+
static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_data)
{
return add_generic_device("cpsw", 0, NULL,
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread