From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCbdH-0001vy-QM for barebox@lists.infradead.org; Thu, 22 Aug 2013 20:37:45 +0000 From: Sascha Hauer Date: Thu, 22 Aug 2013 22:36:57 +0200 Message-Id: <1377203819-23074-7-git-send-email-s.hauer@pengutronix.de> In-Reply-To: <1377203819-23074-1-git-send-email-s.hauer@pengutronix.de> References: <1377203819-23074-1-git-send-email-s.hauer@pengutronix.de> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH 6/8] ARM: am33xx: beaglebone: split out DDR2 init for BB White To: barebox@lists.infradead.org From: Jan Luebbe To make place for the DDR3 init for the BB black. Signed-off-by: Jan Luebbe Signed-off-by: Sascha Hauer --- arch/arm/boards/beaglebone/Makefile | 2 +- arch/arm/boards/beaglebone/ddr.h | 1 + arch/arm/boards/beaglebone/ddr2.c | 178 ++++++++++++++++++++++++++++++++++ arch/arm/boards/beaglebone/lowlevel.c | 175 +-------------------------------- 4 files changed, 184 insertions(+), 172 deletions(-) create mode 100644 arch/arm/boards/beaglebone/ddr.h create mode 100644 arch/arm/boards/beaglebone/ddr2.c diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile index 092c31d..7ec0c8b 100644 --- a/arch/arm/boards/beaglebone/Makefile +++ b/arch/arm/boards/beaglebone/Makefile @@ -1,2 +1,2 @@ -lwl-y += lowlevel.o +lwl-y += lowlevel.o ddr2.o obj-y += board.o diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h new file mode 100644 index 0000000..d2f0c95 --- /dev/null +++ b/arch/arm/boards/beaglebone/ddr.h @@ -0,0 +1 @@ +void beaglebone_config_ddr2(void); diff --git a/arch/arm/boards/beaglebone/ddr2.c b/arch/arm/boards/beaglebone/ddr2.c new file mode 100644 index 0000000..42a099d --- /dev/null +++ b/arch/arm/boards/beaglebone/ddr2.c @@ -0,0 +1,178 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +/* AM335X EMIF Register values */ +#define EMIF_SDMGT 0x80000000 +#define EMIF_SDRAM 0x00004650 +#define EMIF_PHYCFG 0x2 +#define DDR_PHY_RESET (0x1 << 10) +#define DDR_FUNCTIONAL_MODE_EN 0x1 +#define DDR_PHY_READY (0x1 << 2) +#define VTP_CTRL_READY (0x1 << 5) +#define VTP_CTRL_ENABLE (0x1 << 6) +#define VTP_CTRL_LOCK_EN (0x1 << 4) +#define VTP_CTRL_START_EN (0x1) +#define DDR2_RATIO 0x80 /* for mDDR */ +#define CMD_FORCE 0x00 /* common #def */ +#define CMD_DELAY 0x00 + +#define EMIF_READ_LATENCY 0x05 +#define EMIF_TIM1 0x0666B3D6 +#define EMIF_TIM2 0x143731DA +#define EMIF_TIM3 0x00000347 +#define EMIF_SDCFG 0x43805332 +#define EMIF_SDREF 0x0000081a +#define DDR2_DLL_LOCK_DIFF 0x0 +#define DDR2_RD_DQS 0x12 +#define DDR2_PHY_FIFO_WE 0x80 + +#define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_WR_DQS 0x00 +#define DDR2_PHY_WRLVL 0x00 +#define DDR2_PHY_GATELVL 0x00 +#define DDR2_PHY_WR_DATA 0x40 +#define PHY_RANK0_DELAY 0x01 +#define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_IOCTRL_VALUE 0x18B + +static void beaglebone_data_macro_config_ddr2(int dataMacroNum) +{ + u32 BaseAddrOffset = 0x00; + + if (dataMacroNum == 1) + BaseAddrOffset = 0xA4; + + __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) + |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), + (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_RD_DQS>>2, + (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) + |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), + (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_WR_DQS>>2, + (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) + |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), + (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_WRLVL>>2, + (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) + |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), + (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_GATELVL>>2, + (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) + |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), + (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_FIFO_WE>>2, + (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) + |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); + __raw_writel(DDR2_PHY_WR_DATA>>2, + (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); + __raw_writel(PHY_DLL_LOCK_DIFF, + (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); +} + +static void beaglebone_cmd_macro_config_ddr2(void) +{ + __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); + + __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); + + __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); + __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); + __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); + __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); + __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); +} + +static void beaglebone_config_vtp_ddr2(void) +{ + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, + AM33XX_VTP0_CTRL_REG); + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), + AM33XX_VTP0_CTRL_REG); + __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, + AM33XX_VTP0_CTRL_REG); + + /* Poll for READY */ + while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); +} + +static void beaglebone_config_emif_ddr2(void) +{ + u32 i; + + /*Program EMIF0 CFG Registers*/ + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); + __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); + __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); + __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); + __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); + __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); + __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); + __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); + + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); + + /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); + __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ + __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); + __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + + for (i = 0; i < 5000; i++) { + + } + + /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); + __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ + __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); + __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); + __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); +} + +void beaglebone_config_ddr2(void) +{ + enable_ddr_clocks(); + + beaglebone_config_vtp_ddr2(); + + beaglebone_cmd_macro_config_ddr2(); + beaglebone_data_macro_config_ddr2(0); + beaglebone_data_macro_config_ddr2(1); + + __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); + __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); + + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); + __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); + + __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); + __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); + + beaglebone_config_emif_ddr2(); +} diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index e6c490a..e869a7b 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -13,6 +13,8 @@ #include #include +#include "ddr.h" + /* UART Defines */ #define UART_SYSCFG_OFFSET (0x54) #define UART_SYSSTS_OFFSET (0x58) @@ -21,176 +23,6 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) -/* AM335X EMIF Register values */ -#define EMIF_SDMGT 0x80000000 -#define EMIF_SDRAM 0x00004650 -#define EMIF_PHYCFG 0x2 -#define DDR_PHY_RESET (0x1 << 10) -#define DDR_FUNCTIONAL_MODE_EN 0x1 -#define DDR_PHY_READY (0x1 << 2) -#define VTP_CTRL_READY (0x1 << 5) -#define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_LOCK_EN (0x1 << 4) -#define VTP_CTRL_START_EN (0x1) -#define DDR2_RATIO 0x80 /* for mDDR */ -#define CMD_FORCE 0x00 /* common #def */ -#define CMD_DELAY 0x00 - -#define EMIF_READ_LATENCY 0x05 -#define EMIF_TIM1 0x0666B3D6 -#define EMIF_TIM2 0x143731DA -#define EMIF_TIM3 0x00000347 -#define EMIF_SDCFG 0x43805332 -#define EMIF_SDREF 0x0000081a -#define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RD_DQS 0x12 -#define DDR2_PHY_FIFO_WE 0x80 - -#define DDR2_INVERT_CLKOUT 0x00 -#define DDR2_WR_DQS 0x00 -#define DDR2_PHY_WRLVL 0x00 -#define DDR2_PHY_GATELVL 0x00 -#define DDR2_PHY_WR_DATA 0x40 -#define PHY_RANK0_DELAY 0x01 -#define PHY_DLL_LOCK_DIFF 0x0 -#define DDR_IOCTRL_VALUE 0x18B - -static void beaglebone_data_macro_config(int dataMacroNum) -{ - u32 BaseAddrOffset = 0x00; - - if (dataMacroNum == 1) - BaseAddrOffset = 0xA4; - - __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) - |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), - (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_RD_DQS>>2, - (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); - __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) - |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), - (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_WR_DQS>>2, - (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); - __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) - |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), - (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_PHY_WRLVL>>2, - (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); - __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) - |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), - (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_PHY_GATELVL>>2, - (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); - __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) - |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), - (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_PHY_FIFO_WE>>2, - (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); - __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) - |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), - (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); - __raw_writel(DDR2_PHY_WR_DATA>>2, - (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); - __raw_writel(PHY_DLL_LOCK_DIFF, - (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); -} - -static void beaglebone_cmd_macro_config(void) -{ - __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); - __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); - __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); - __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); - __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); - - __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); - __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); - __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); - __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); - __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); - - __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); - __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); - __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); - __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); - __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); -} - -static void beaglebone_config_vtp(void) -{ - __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, - AM33XX_VTP0_CTRL_REG); - __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), - AM33XX_VTP0_CTRL_REG); - __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, - AM33XX_VTP0_CTRL_REG); - - /* Poll for READY */ - while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); -} - -static void beaglebone_config_emif_ddr2(void) -{ - u32 i; - - /*Program EMIF0 CFG Registers*/ - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); - - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); - - /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); - __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - - for (i = 0; i < 5000; i++) { - - } - - /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); - __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); - - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -} - -static void beaglebone_config_ddr(void) -{ - enable_ddr_clocks(); - - beaglebone_config_vtp(); - - beaglebone_cmd_macro_config(); - beaglebone_data_macro_config(0); - beaglebone_data_macro_config(1); - - __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); - __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); - - __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); - __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); - __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); - __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); - __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); - - __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); - __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); - - beaglebone_config_emif_ddr2(); -} - /* * early system init of muxing and clocks. */ @@ -201,7 +33,8 @@ void beaglebone_sram_init(void) /* Setup the PLLs and the clocks for the peripherals */ pll_init(MPUPLL_M_500); - beaglebone_config_ddr(); + if (get_cpu_rev() == AM335X_ES1_0) + beaglebone_config_ddr2(); /* UART softreset */ uart_base = AM33XX_UART0_BASE; -- 1.8.4.rc3 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox