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From: Lucas Stach <dev@lynxeye.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/8] tegra: speed up system bus
Date: Tue,  3 Dec 2013 20:56:56 +0100	[thread overview]
Message-ID: <1386100622-8498-4-git-send-email-dev@lynxeye.de> (raw)
In-Reply-To: <1386100622-8498-1-git-send-email-dev@lynxeye.de>

We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra20-car.h | 12 ++++++++++++
 drivers/clk/tegra/clk-tegra20.c                |  7 +++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index d4cb238..d4ff6fb 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -53,6 +53,18 @@
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_RUN	2
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_IDLE	1
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_STDBY	0
+#define CRC_SCLK_BURST_POLICY_FIQ_SRC_SHIFT	12
+#define CRC_SCLK_BURST_POLICY_IRQ_SRC_SHIFT	8
+#define CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT	4
+#define CRC_SCLK_BURST_POLICY_IDLE_SRC_SHIFT	0
+#define CRC_SCLK_BURST_POLICY_SRC_CLKM		0
+#define CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1	1
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4	2
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT3	3
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT2	4
+#define CRC_SCLK_BURST_POLICY_SRC_CLKD		5
+#define CRC_SCLK_BURST_POLICY_SRC_CLKS		6
+#define CRC_SCLK_BURST_POLICY_SRC_PLLM_OUT1	7
 
 #define CRC_SUPER_SCLK_DIV		0x02c
 #define CRC_SUPER_SDIV_ENB		(1 << 31)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index e70f99a..b94b7bc 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -325,6 +325,13 @@ static int tegra20_car_probe(struct device_d *dev)
 
 	tegra_init_from_table(init_table, clks, clk_max);
 
+	/* speed up system bus */
+	writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<
+	       CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT |
+	       CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1 <<
+	       CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT,
+	       car_base + CRC_SCLK_BURST_POLICY);
+
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
-- 
1.8.3.1


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  parent reply	other threads:[~2013-12-03 19:53 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-03 19:56 [PATCH 0/8] tegra-next Lucas Stach
2013-12-03 19:56 ` [PATCH] gpio: reduce noise when parsing DT Lucas Stach
2013-12-03 19:56 ` [PATCH 1/8] tegra: fix fallout from relocatable code changes in PLLX init Lucas Stach
2013-12-03 19:56 ` Lucas Stach [this message]
2013-12-03 19:56 ` [PATCH 3/8] tegra: switch main CPU complex to PLLX early Lucas Stach
2013-12-03 19:56 ` [PATCH 4/8] gpio: tegra: remove leftover debug code Lucas Stach
2013-12-03 19:56 ` [PATCH 5/8] clk: tegra: add SDMMC clocks Lucas Stach
2013-12-03 19:57 ` [PATCH 6/8] tegra: add SDMMC controller driver Lucas Stach
2013-12-03 19:57 ` [PATCH 7/8] dts: tegra: add SDMMC nodes Lucas Stach
2013-12-03 19:57 ` [PATCH 8/8] dts: tegra: activate SDMMC on Colibri T20 Lucas Stach
2013-12-04 16:01 ` [PATCH 0/8] tegra-next Sascha Hauer

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