* [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux
@ 2014-01-07 18:12 Lucas Stach
2014-01-07 18:12 ` [PATCH 02/10] ARM: imx6q: update sabrelite DT Lucas Stach
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
This makes it possible to pull other DT changes from
the linux kernel repo. Plus it will make it possible
to slim down the i.MX6 dtbs at a later point.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6dl.dtsi | 1 +
arch/arm/dts/imx6q.dtsi | 1 +
arch/arm/dts/imx6qdl-pingrp.h | 526 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 528 insertions(+)
create mode 100644 arch/arm/dts/imx6qdl-pingrp.h
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index e9cb589..cdf31c7 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -9,6 +9,7 @@
*/
#include "imx6dl-pinfunc.h"
+#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index 0377cce..84ed89e 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -9,6 +9,7 @@
*/
#include "imx6q-pinfunc.h"
+#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
diff --git a/arch/arm/dts/imx6qdl-pingrp.h b/arch/arm/dts/imx6qdl-pingrp.h
new file mode 100644
index 0000000..8d71b13
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-pingrp.h
@@ -0,0 +1,526 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6QDL_PINGRP_H
+#define __DTS_IMX6QDL_PINGRP_H
+
+#define MX6QDL_AUDMUX_PINGRP1 \
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+
+#define MX6QDL_AUDMUX_PINGRP2 \
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+
+#define MX6QDL_AUDMUX_PINGRP3 \
+ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \
+ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \
+
+#define MX6QDL_AUDMUX_PINGRP4 \
+ MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \
+ MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+
+#define MX6QDL_ECSPI1_PINGRP1 \
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 \
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+
+#define MX6QDL_ECSPI1_PINGRP2 \
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 \
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 \
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+
+#define MX6QDL_ECSPI3_PINGRP1 \
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 \
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 \
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+
+#define MX6QDL_ENET_PINGRP1 \
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 \
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+
+#define MX6QDL_ENET_PINGRP2 \
+ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 \
+ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+
+#define MX6QDL_ENET_PINGRP3 \
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 \
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+
+#define MX6QDL_ESAI_PINGRP1 \
+ MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 \
+ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
+ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
+ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
+ MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 \
+ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
+ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
+ MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 \
+ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
+
+#define MX6QDL_ESAI_PINGRP2 \
+ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
+ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
+ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
+ MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 \
+ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
+ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
+ MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 \
+ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 \
+ MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 \
+ MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
+
+#define MX6QDL_FLEXCAN1_PINGRP1 \
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 \
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+
+#define MX6QDL_FLEXCAN1_PINGRP2 \
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 \
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+
+#define MX6QDL_FLEXCAN2_PINGRP1 \
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 \
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+
+#define MX6QDL_GPMI_NAND_PINGRP1 \
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 \
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+
+#define MX6QDL_GPMI_NAND_PINGRP1_NODQS \
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+
+#define MX6QDL_HDMI_HDCP_PINGRP1 \
+ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 \
+ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+
+#define MX6QDL_HDMI_HDCP_PINGRP2 \
+ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
+ MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
+
+#define MX6QDL_HDMI_HDCP_PINGRP3 \
+ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
+ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+
+#define MX6QDL_HDMI_CEC_PINGRP1 \
+ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+
+#define MX6QDL_HDMI_CEC_PINGRP2 \
+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+
+#define MX6QDL_I2C1_PINGRP1 \
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 \
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+
+#define MX6QDL_I2C1_PINGRP2 \
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 \
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+
+#define MX6QDL_I2C2_PINGRP1 \
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+
+#define MX6QDL_I2C2_PINGRP2 \
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 \
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+
+#define MX6QDL_I2C2_PINGRP3 \
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+
+#define MX6QDL_I2C3_PINGRP1 \
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 \
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+
+#define MX6QDL_I2C3_PINGRP2 \
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+
+#define MX6QDL_I2C3_PINGRP3 \
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 \
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+
+#define MX6QDL_I2C3_PINGRP4 \
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+
+#define MX6QDL_IPU1_PINGRP1 \
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 \
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 \
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 \
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 \
+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 \
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 \
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 \
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 \
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 \
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 \
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 \
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 \
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 \
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 \
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 \
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 \
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 \
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 \
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 \
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 \
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 \
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 \
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 \
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 \
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 \
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 \
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 \
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 \
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+
+/* parallel camera */
+#define MX6QDL_IPU1_PINGRP2 \
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 \
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+
+/* parallel port 16-bit */
+#define MX6QDL_IPU1_PINGRP3 \
+ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+
+#define MX6QDL_MLB_PINGRP1 \
+ MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 \
+ MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
+ MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
+
+#define MX6QDL_MLB_PINGRP2 \
+ MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 \
+ MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
+ MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
+
+#define MX6QDL_PWM1_PINGRP1 \
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+
+#define MX6QDL_PWM3_PINGRP1 \
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+
+#define MX6QDL_SPDIF_PINGRP1 \
+ MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
+
+#define MX6QDL_SPDIF_PINGRP2 \
+ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 \
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+
+#define MX6QDL_SPDIF_PINGRP3 \
+ MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
+
+#define MX6QDL_UART1_PINGRP1 \
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+
+#define MX6QDL_UART1_PINGRP2 \
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+
+#define MX6QDL_UART2_PINGRP1 \
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+
+/* DTE mode */
+#define MX6QDL_UART2_PINGRP2 \
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 \
+ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+
+#define MX6QDL_UART2_PINGRP3 \
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+
+#define MX6QDL_UART3_PINGRP1 \
+ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 \
+ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 \
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+
+#define MX6QDL_UART3_PINGRP2 \
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 \
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+
+#define MX6QDL_UART3_PINGRP3 \
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+
+#define MX6QDL_UART4_PINGRP1 \
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+
+#define MX6QDL_UART5_PINGRP1 \
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+
+#define MX6QDL_USBOTG_PINGRP1 \
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+
+#define MX6QDL_USBOTG_PINGRP2 \
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+
+#define MX6QDL_USBH2_PINGRP1 \
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 \
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
+
+#define MX6QDL_USBH2_PINGRP2 \
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
+
+#define MX6QDL_USBH3_PINGRP1 \
+ MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 \
+ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
+
+#define MX6QDL_USBH3_PINGRP2 \
+ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
+
+#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD1_CMD__SD1_CMD pad \
+ MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
+
+#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \
+ MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \
+ MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \
+ MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \
+ MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad
+
+#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD2_CMD__SD2_CMD pad \
+ MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
+
+#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \
+ MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad
+
+#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD3_CMD__SD3_CMD pad \
+ MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
+
+#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \
+ MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad
+
+#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD4_CMD__SD4_CMD pad \
+ MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3
+
+#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \
+ MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad
+
+#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9)
+#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9)
+
+#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9)
+#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9)
+
+#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9)
+#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9)
+
+#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9)
+#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059)
+#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9)
+#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9)
+
+#define MX6QDL_WEIM_CS0_PINGRP1 \
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+
+#define MX6QDL_WEIM_NOR_PINGRP1 \
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 \
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 \
+ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 \
+ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 \
+ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 \
+ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 \
+ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 \
+ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 \
+ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 \
+ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 \
+ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 \
+ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 \
+ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 \
+ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 \
+ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 \
+ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 \
+ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 \
+ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 \
+ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 \
+ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 \
+ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 \
+ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 \
+ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 \
+ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 \
+ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 \
+ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 \
+ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 \
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 \
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 \
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 \
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 \
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 \
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 \
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 \
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 \
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 \
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 \
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 \
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 \
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 \
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 \
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 \
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+
+#endif /* __DTS_IMX6QDL_PINGRP_H */
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 02/10] ARM: imx6q: update sabrelite DT
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 03/10] ARM: imx6: update SabreSD DTs Lucas Stach
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6q-sabrelite.dts | 157 +++++++++++++++++++++++++++------------
1 file changed, 111 insertions(+), 46 deletions(-)
diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts
index fd3ffa9..5ef994d 100644
--- a/arch/arm/dts/imx6q-sabrelite.dts
+++ b/arch/arm/dts/imx6q-sabrelite.dts
@@ -32,25 +32,30 @@
regulators {
compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_2p5v: 2p5v {
+ reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
+ reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
- reg_3p3v: 3p3v {
+ reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
+ reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
- reg_usb_otg_vbus: usb_otg_vbus {
+ reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
+ reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -74,17 +79,24 @@
};
};
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
+
#address-cells = <1>;
#size-cells = <1>;
@@ -100,16 +112,34 @@
};
};
-&ssi1 {
- fsl,mode = "i2s-slave";
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks 201>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- hog {
+ imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
@@ -122,6 +152,63 @@
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <MX6QDL_USDHC4_PINGRP_D4>;
+ };
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: hsd100pxn1 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <220>;
+ hfront-porch = <40>;
+ vback-porch = <21>;
+ vfront-porch = <7>;
+ hsync-len = <60>;
+ vsync-len = <10>;
+ };
+ };
};
};
@@ -129,13 +216,18 @@
barebox,provide-mac-address = <&fec 0x620>;
};
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
+&sata {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_1>;
- disable-over-current;
- phy-mode = "utmi";
- dr_mode = "host";
+ pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
@@ -145,17 +237,17 @@
status = "okay";
};
-&fec {
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_1>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio3 23 0>;
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <®_3p3v>;
@@ -164,36 +256,9 @@
&usdhc4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_2>;
+ pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <®_3p3v>;
status = "okay";
};
-
-&audmux {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux_1>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2_1>;
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1>;
-
- codec: sgtl5000@0a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&clks 169>;
- VDDA-supply = <®_2p5v>;
- VDDIO-supply = <®_3p3v>;
- };
-};
--
1.8.4.2
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 03/10] ARM: imx6: update SabreSD DTs
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
2014-01-07 18:12 ` [PATCH 02/10] ARM: imx6q: update sabrelite DT Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 04/10] ARM: imx6: update phytec-pfla02 DT Lucas Stach
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6q-sabresd.dts | 20 +---
arch/arm/dts/imx6qdl-sabresd.dtsi | 231 +++++++++++++++++++++++++++++++++++++-
2 files changed, 228 insertions(+), 23 deletions(-)
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
index 021b924..efe0e59 100644
--- a/arch/arm/dts/imx6q-sabresd.dts
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -20,24 +20,10 @@
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
chosen {
- linux,stdout-path = "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000";
+ linux,stdout-path = &uart1;
};
};
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- hog {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
- >;
- };
- };
+&sata {
+ status = "okay";
};
diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
index 0d32278..b64611c 100644
--- a/arch/arm/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -17,15 +17,36 @@
regulators {
compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_usb_otg_vbus: usb_otg_vbus {
+ reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
+ reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
+
+ reg_usb_h1_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 29 0>;
+ enable-active-high;
+ };
+
+ reg_audio: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "wm8962-supply";
+ gpio = <&gpio4 10 0>;
+ enable-active-high;
+ };
};
gpio-keys {
@@ -34,49 +55,246 @@
volume-up {
label = "Volume Up";
gpios = <&gpio1 4 0>;
+ gpio-key,wakeup;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 5 0>;
+ gpio-key,wakeup;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
+
+ sound {
+ compatible = "fsl,imx6q-sabresd-wm8962",
+ "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "MICBIAS", "AMIC",
+ "IN3R", "MICBIAS",
+ "DMIC", "MICBIAS",
+ "DMICDAT", "DMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ status = "okay";
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 9 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p32";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
};
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_1>;
+ pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 0>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks 201>;
+ DCVDD-supply = <®_audio>;
+ DBVDD-supply = <®_audio>;
+ AVDD-supply = <®_audio>;
+ CPVDD-supply = <®_audio>;
+ MICVDD-supply = <®_audio>;
+ PLLVDD-supply = <®_audio>;
+ SPKVDD1-supply = <®_audio>;
+ SPKVDD2-supply = <®_audio>;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+ 0x0013 /* 2:FN_DMICCLK */
+ 0x0000 /* 3:Default */
+ 0x8014 /* 4:FN_DMICCDAT */
+ 0x0000 /* 5:Default */
+ >;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ egalax_ts@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <7 2>;
+ wakeup-gpios = <&gpio6 7 0>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6qdl-sabresd {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX6QDL_ECSPI1_PINGRP2>;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX6QDL_I2C1_PINGRP2>;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <MX6QDL_PWM1_PINGRP1>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX6QDL_USDHC2_PINGRP_D8>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
+ };
+ };
+};
+
+&ldb {
status = "okay";
+
+ lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: hsd100pxn1 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <220>;
+ hfront-porch = <40>;
+ vback-porch = <21>;
+ vfront-porch = <7>;
+ hsync-len = <60>;
+ vsync-len = <10>;
+ };
+ };
+ };
};
&ocotp1 {
barebox,provide-mac-address = <&fec 0x620>;
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&ssi2 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_1>;
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_2>;
+ pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_1>;
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
@@ -84,7 +302,8 @@
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
--
1.8.4.2
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 04/10] ARM: imx6: update phytec-pfla02 DT
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
2014-01-07 18:12 ` [PATCH 02/10] ARM: imx6q: update sabrelite DT Lucas Stach
2014-01-07 18:12 ` [PATCH 03/10] ARM: imx6: update SabreSD DTs Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 05/10] ARM: imx6: update Carrier-1 DTs Lucas Stach
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6q-phytec-pfla02.dtsi | 144 +++++++++++++++++++++++++++++-----
1 file changed, 125 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
index d113f7f..b615491 100644
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
@@ -22,7 +22,7 @@
&ecspi3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3_1>;
+ pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
@@ -35,34 +35,140 @@
};
&i2c1 {
- status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
- eeprom: m24c32@50 {
- compatible = "st,24c32", "at24";
+ eeprom@50 {
+ compatible = "atmel,24c32";
reg = <0x50>;
};
+
+ pmic@58 {
+ compatible = "dialog,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <17 0x8>; /* active-low GPIO4_17 */
+
+ regulators {
+ vddcore_reg: bcore1 {
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vddsoc_reg: bcore2 {
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vdd_ddr3_reg: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_reg: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_buckmem_reg: bmem {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_reg: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_io_reg: ldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_mx6_snvs_reg: ldo5 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_pmic_io_reg: ldo6 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_sd0_reg: ldo9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_sd1_reg: ldo10 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_mx6_high_reg: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ };
+ };
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- hog {
+ imx6q-phytec-pfla02 {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
>;
};
- };
- pfla02 {
- pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <MX6QDL_ECSPI3_PINGRP1>;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP3>;
+ };
+
+ pinctrl_gpmi_nand: gpmigrp {
+ fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc3_cdwp: usdhc3cdwp {
fsl,pins = <
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
@@ -70,7 +176,7 @@
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_3>;
+ pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "disabled";
@@ -93,7 +199,7 @@
&gpmi {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
#address-cells = <1>;
@@ -116,13 +222,13 @@
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4_1>;
+ pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
@@ -130,8 +236,8 @@
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2
- &pinctrl_usdhc3_pfla02>;
+ pinctrl-0 = <&pinctrl_usdhc3
+ &pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";
--
1.8.4.2
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 05/10] ARM: imx6: update Carrier-1 DTs
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (2 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 04/10] ARM: imx6: update phytec-pfla02 DT Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 06/10] ARM: imx6: update TQ DTs Lucas Stach
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6dl-cubox-i-carrier-1.dts | 6 +++++-
arch/arm/dts/imx6qdl-microsom.dtsi | 6 +++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts b/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts
index 88c3ef7..1f13f03 100644
--- a/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts
+++ b/arch/arm/dts/imx6dl-cubox-i-carrier-1.dts
@@ -51,7 +51,7 @@
&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1>;
+ pinctrl-0 = <&pinctrl_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
@@ -87,6 +87,10 @@
MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071
>;
};
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ };
};
};
diff --git a/arch/arm/dts/imx6qdl-microsom.dtsi b/arch/arm/dts/imx6qdl-microsom.dtsi
index 1d6d56d..85e43bf 100644
--- a/arch/arm/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/dts/imx6qdl-microsom.dtsi
@@ -58,12 +58,16 @@
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ };
};
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_1>;
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 06/10] ARM: imx6: update TQ DTs
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (3 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 05/10] ARM: imx6: update Carrier-1 DTs Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 07/10] ARM: imx6: update GK802 DT Lucas Stach
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6qdl-mba6x.dtsi | 16 ++++++++++++++--
arch/arm/dts/imx6qdl-tqma6x.dtsi | 34 +++++++++++++++++++++++++++++-----
2 files changed, 43 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-mba6x.dtsi b/arch/arm/dts/imx6qdl-mba6x.dtsi
index ec002c6..dbf43c2 100644
--- a/arch/arm/dts/imx6qdl-mba6x.dtsi
+++ b/arch/arm/dts/imx6qdl-mba6x.dtsi
@@ -96,7 +96,7 @@
&audmux {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux_2>;
+ pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
@@ -112,6 +112,18 @@
status = "okay";
};
+&iomuxc {
+ imx6qdl-mba6x {
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
+ };
+ };
+};
+
&i2c1 {
codec: tlv320@18 {
compatible = "ti,tlv320aic23";
@@ -172,7 +184,7 @@
&usbotg {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_1>;
+ pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
diff --git a/arch/arm/dts/imx6qdl-tqma6x.dtsi b/arch/arm/dts/imx6qdl-tqma6x.dtsi
index 668fa25..ce18e23 100644
--- a/arch/arm/dts/imx6qdl-tqma6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tqma6x.dtsi
@@ -11,7 +11,7 @@
&ecspi1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
status = "okay";
@@ -25,23 +25,47 @@
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_1>;
+ pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
status = "okay";
};
+&iomuxc {
+ imx6qdl-tqma6x {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX6QDL_I2C1_PINGRP2>;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
+ };
+ };
+};
+
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_2>;
+ pinctrl-0 = <&pinctrl_i2c1>;
};
&i2c3 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_2>;
+ pinctrl-0 = <&pinctrl_i2c3>;
pmic: pf0100@08 {
compatible = "pf0100-regulator";
@@ -155,7 +179,7 @@
&usdhc3 { /* eMMC */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_1>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
bus-width = <8>;
status = "okay";
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 07/10] ARM: imx6: update GK802 DT
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (4 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 06/10] ARM: imx6: update TQ DTs Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 08/10] ARM: imx6: update DMO RealQ7 DT Lucas Stach
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6q-gk802.dts | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx6q-gk802.dts b/arch/arm/dts/imx6q-gk802.dts
index b34a491..7cb06ef 100644
--- a/arch/arm/dts/imx6q-gk802.dts
+++ b/arch/arm/dts/imx6q-gk802.dts
@@ -99,6 +99,22 @@
>;
};
};
+
+ uart {
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ };
+ };
+
+ usdhc {
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <MX6QDL_USDHC4_PINGRP_D4>;
+ };
+ };
};
&uart2 {
@@ -107,7 +123,7 @@
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4_1>;
+ pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
@@ -130,7 +146,7 @@
/* External microSD */
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
cd-gpios = <&gpio6 11 0>;
vmmc-supply = <®_3p3v>;
@@ -140,7 +156,7 @@
/* Internal microSD */
&usdhc4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_2>;
+ pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
vmmc-supply = <®_3p3v>;
status = "okay";
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 08/10] ARM: imx6: update DMO RealQ7 DT
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (5 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 07/10] ARM: imx6: update GK802 DT Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 09/10] ARM: imx6: update DFI FS700 M60 DT Lucas Stach
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6q-dmo-realq7.dts | 34 ++++++++++++++++++++++++++++++----
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx6q-dmo-realq7.dts b/arch/arm/dts/imx6q-dmo-realq7.dts
index 5057c0b..f713947 100644
--- a/arch/arm/dts/imx6q-dmo-realq7.dts
+++ b/arch/arm/dts/imx6q-dmo-realq7.dts
@@ -116,7 +116,7 @@
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_1>;
+ pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
@@ -294,6 +294,10 @@
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
>;
};
+
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ };
};
pfuze {
@@ -329,6 +333,28 @@
>;
};
};
+
+ enet {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ };
+ };
+
+ usb {
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ };
+ };
+
+ usdhc {
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
+ };
+ };
};
&sata {
@@ -356,21 +382,21 @@
&usbotg {
vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_1>;
+ pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <®_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_1>;
+ pinctrl-0 = <&pinctrl_usdhc4>;
vmmc-supply = <®_3p3v>;
non-removable;
bus-width = <8>;
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 09/10] ARM: imx6: update DFI FS700 M60 DT
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (6 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 08/10] ARM: imx6: update DMO RealQ7 DT Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-07 18:12 ` [PATCH 10/10] ARM: imx6: remove old pingroups Lucas Stach
2014-01-10 8:23 ` [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi | 44 +++++++++++++++++++++++++++------
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
index 04bb213..5744147 100644
--- a/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -33,7 +33,7 @@
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_1>;
+ pinctrl-0 = <&pinctrl_enet>;
status = "okay";
phy-mode = "rgmii";
};
@@ -42,7 +42,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- hog {
+ imx6qdl-dfi-fs700-m60 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
@@ -52,12 +52,40 @@
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* SD2 card detect */
>;
};
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <MX6QDL_I2C2_PINGRP1>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
+ };
};
};
&i2c2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_1>;
+ pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pf0100@08 {
@@ -74,7 +102,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_1>;
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
@@ -87,7 +115,7 @@
&usbotg {
vbus-supply = <®_usb_otg_vbus>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg_2>;
+ pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
phy_type = "utmi";
dr_mode = "host";
@@ -96,19 +124,19 @@
&usdhc2 { /* module slot */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_2>;
+ pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio2 2 0>;
status = "okay";
};
&usdhc3 { /* baseboard slot */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
+ pinctrl-0 = <&pinctrl_usdhc3>;
};
&usdhc4 { /* eMMC */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4_1>;
+ pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
status = "okay";
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 10/10] ARM: imx6: remove old pingroups
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (7 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 09/10] ARM: imx6: update DFI FS700 M60 DT Lucas Stach
@ 2014-01-07 18:12 ` Lucas Stach
2014-01-10 8:23 ` [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Lucas Stach @ 2014-01-07 18:12 UTC (permalink / raw)
To: barebox
From: Lucas Stach <dev@lynxeye.de>
Keeps the size of the compiles DTs down.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
arch/arm/dts/imx6qdl.dtsi | 298 ----------------------------------------------
1 file changed, 298 deletions(-)
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index a574958..9e0276c 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -555,304 +555,6 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
-
- /* shared pinctrl settings */
- audmux {
- pinctrl_audmux_1: audmux-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
- >;
- };
-
- pinctrl_audmux_2: audmux-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
- >;
- };
- };
-
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- >;
- };
-
- pinctrl_ecspi1_2: ecspi1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- >;
- };
- };
-
- ecspi3 {
- pinctrl_ecspi3_1: ecspi3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
- >;
- };
- };
-
- enet {
- pinctrl_enet_1: enetgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- >;
- };
-
- pinctrl_enet_2: enetgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- >;
- };
-
- pinctrl_enet_3: enetgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- >;
- };
- };
-
- gpmi-nand {
- pinctrl_gpmi_nand_1: gpmi-nand-1 {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
- MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
- };
-
- i2c1 {
- pinctrl_i2c1_1: i2c1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c1_2: i2c1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
- >;
- };
- };
-
- i2c2 {
- pinctrl_i2c2_1: i2c2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
- >;
- };
- };
-
- i2c3 {
- pinctrl_i2c3_1: i2c3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
- };
-
- uart1 {
- pinctrl_uart1_1: uart1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
- >;
- };
- };
-
- uart2 {
- pinctrl_uart2_1: uart2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
- };
-
- uart4 {
- pinctrl_uart4_1: uart4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
- };
-
- usbotg {
- pinctrl_usbotg_1: usbotggrp-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usbotg_2: usbotggrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
- >;
- };
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2_2: usdhc2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc3_2: usdhc3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
- };
-
- usdhc4 {
- pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc4_2: usdhc4grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- >;
- };
- };
};
ldb: ldb@020e0008 {
--
1.8.4.2
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
` (8 preceding siblings ...)
2014-01-07 18:12 ` [PATCH 10/10] ARM: imx6: remove old pingroups Lucas Stach
@ 2014-01-10 8:23 ` Sascha Hauer
9 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2014-01-10 8:23 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Tue, Jan 07, 2014 at 07:12:47PM +0100, Lucas Stach wrote:
> From: Lucas Stach <dev@lynxeye.de>
>
> This makes it possible to pull other DT changes from
> the linux kernel repo. Plus it will make it possible
> to slim down the i.MX6 dtbs at a later point.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
Applied, thanks
Sascha
> ---
> arch/arm/dts/imx6dl.dtsi | 1 +
> arch/arm/dts/imx6q.dtsi | 1 +
> arch/arm/dts/imx6qdl-pingrp.h | 526 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 528 insertions(+)
> create mode 100644 arch/arm/dts/imx6qdl-pingrp.h
>
> diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
> index e9cb589..cdf31c7 100644
> --- a/arch/arm/dts/imx6dl.dtsi
> +++ b/arch/arm/dts/imx6dl.dtsi
> @@ -9,6 +9,7 @@
> */
>
> #include "imx6dl-pinfunc.h"
> +#include "imx6qdl-pingrp.h"
> #include "imx6qdl.dtsi"
>
> / {
> diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
> index 0377cce..84ed89e 100644
> --- a/arch/arm/dts/imx6q.dtsi
> +++ b/arch/arm/dts/imx6q.dtsi
> @@ -9,6 +9,7 @@
> */
>
> #include "imx6q-pinfunc.h"
> +#include "imx6qdl-pingrp.h"
> #include "imx6qdl.dtsi"
>
> / {
> diff --git a/arch/arm/dts/imx6qdl-pingrp.h b/arch/arm/dts/imx6qdl-pingrp.h
> new file mode 100644
> index 0000000..8d71b13
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-pingrp.h
> @@ -0,0 +1,526 @@
> +/*
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DTS_IMX6QDL_PINGRP_H
> +#define __DTS_IMX6QDL_PINGRP_H
> +
> +#define MX6QDL_AUDMUX_PINGRP1 \
> + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \
> + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \
> + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \
> + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
> +
> +#define MX6QDL_AUDMUX_PINGRP2 \
> + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \
> + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \
> + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \
> + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
> +
> +#define MX6QDL_AUDMUX_PINGRP3 \
> + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \
> + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \
> + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \
> +
> +#define MX6QDL_AUDMUX_PINGRP4 \
> + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \
> + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \
> + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
> +
> +#define MX6QDL_ECSPI1_PINGRP1 \
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 \
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> +
> +#define MX6QDL_ECSPI1_PINGRP2 \
> + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 \
> + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 \
> + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
> +
> +#define MX6QDL_ECSPI3_PINGRP1 \
> + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 \
> + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 \
> + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
> +
> +#define MX6QDL_ENET_PINGRP1 \
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 \
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> +
> +#define MX6QDL_ENET_PINGRP2 \
> + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 \
> + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> +
> +#define MX6QDL_ENET_PINGRP3 \
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 \
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 \
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 \
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> +
> +#define MX6QDL_ESAI_PINGRP1 \
> + MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 \
> + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
> + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
> + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
> + MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 \
> + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
> + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
> + MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 \
> + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
> +
> +#define MX6QDL_ESAI_PINGRP2 \
> + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
> + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
> + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
> + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 \
> + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
> + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
> + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 \
> + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 \
> + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 \
> + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
> +
> +#define MX6QDL_FLEXCAN1_PINGRP1 \
> + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 \
> + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
> +
> +#define MX6QDL_FLEXCAN1_PINGRP2 \
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 \
> + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
> +
> +#define MX6QDL_FLEXCAN2_PINGRP1 \
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 \
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
> +
> +#define MX6QDL_GPMI_NAND_PINGRP1 \
> + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
> + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
> + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
> + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
> + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
> + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
> + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
> + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
> + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
> + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
> + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
> + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
> + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 \
> + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> +
> +#define MX6QDL_GPMI_NAND_PINGRP1_NODQS \
> + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
> + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
> + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
> + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
> + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
> + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
> + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
> + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
> + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
> + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
> + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
> + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
> + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
> + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> +
> +#define MX6QDL_HDMI_HDCP_PINGRP1 \
> + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 \
> + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
> +
> +#define MX6QDL_HDMI_HDCP_PINGRP2 \
> + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
> + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
> +
> +#define MX6QDL_HDMI_HDCP_PINGRP3 \
> + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
> + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
> +
> +#define MX6QDL_HDMI_CEC_PINGRP1 \
> + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
> +
> +#define MX6QDL_HDMI_CEC_PINGRP2 \
> + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
> +
> +#define MX6QDL_I2C1_PINGRP1 \
> + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 \
> + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C1_PINGRP2 \
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 \
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> +
> +#define MX6QDL_I2C2_PINGRP1 \
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
> + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C2_PINGRP2 \
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 \
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C2_PINGRP3 \
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C3_PINGRP1 \
> + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 \
> + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C3_PINGRP2 \
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C3_PINGRP3 \
> + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 \
> + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
> +
> +#define MX6QDL_I2C3_PINGRP4 \
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
> + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
> +
> +#define MX6QDL_IPU1_PINGRP1 \
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 \
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 \
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 \
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 \
> + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 \
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 \
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 \
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 \
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 \
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 \
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 \
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 \
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 \
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 \
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 \
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 \
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 \
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 \
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 \
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 \
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 \
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 \
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 \
> + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 \
> + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 \
> + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 \
> + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 \
> + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 \
> + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
> +
> +/* parallel camera */
> +#define MX6QDL_IPU1_PINGRP2 \
> + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
> + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 \
> + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
> + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
> + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
> +
> +/* parallel port 16-bit */
> +#define MX6QDL_IPU1_PINGRP3 \
> + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
> + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
> + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
> + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
> + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
> +
> +#define MX6QDL_MLB_PINGRP1 \
> + MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 \
> + MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
> + MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
> +
> +#define MX6QDL_MLB_PINGRP2 \
> + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 \
> + MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
> + MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
> +
> +#define MX6QDL_PWM1_PINGRP1 \
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> +
> +#define MX6QDL_PWM3_PINGRP1 \
> + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
> +
> +#define MX6QDL_SPDIF_PINGRP1 \
> + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
> +
> +#define MX6QDL_SPDIF_PINGRP2 \
> + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 \
> + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> +
> +#define MX6QDL_SPDIF_PINGRP3 \
> + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
> +
> +#define MX6QDL_UART1_PINGRP1 \
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_UART1_PINGRP2 \
> + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_UART2_PINGRP1 \
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> +
> +/* DTE mode */
> +#define MX6QDL_UART2_PINGRP2 \
> + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 \
> + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
> +
> +#define MX6QDL_UART2_PINGRP3 \
> + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_UART3_PINGRP1 \
> + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 \
> + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 \
> + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
> +
> +#define MX6QDL_UART3_PINGRP2 \
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 \
> + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
> +
> +#define MX6QDL_UART3_PINGRP3 \
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_UART4_PINGRP1 \
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_UART5_PINGRP1 \
> + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 \
> + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
> +
> +#define MX6QDL_USBOTG_PINGRP1 \
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
> +
> +#define MX6QDL_USBOTG_PINGRP2 \
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> +
> +#define MX6QDL_USBH2_PINGRP1 \
> + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 \
> + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
> +
> +#define MX6QDL_USBH2_PINGRP2 \
> + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
> +
> +#define MX6QDL_USBH3_PINGRP1 \
> + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 \
> + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
> +
> +#define MX6QDL_USBH3_PINGRP2 \
> + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
> +
> +#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD1_CMD__SD1_CMD pad \
> + MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
> +
> +#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \
> + MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \
> + MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \
> + MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \
> + MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad
> +
> +#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD2_CMD__SD2_CMD pad \
> + MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
> +
> +#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \
> + MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \
> + MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \
> + MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \
> + MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad
> +
> +#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD3_CMD__SD3_CMD pad \
> + MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
> +
> +#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \
> + MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad
> +
> +#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD4_CMD__SD4_CMD pad \
> + MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3
> +
> +#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \
> + MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad
> +
> +#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9)
> +#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9)
> +
> +#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9)
> +#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9)
> +
> +#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9)
> +#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9)
> +
> +#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9)
> +#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059)
> +#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9)
> +#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9)
> +
> +#define MX6QDL_WEIM_CS0_PINGRP1 \
> + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
> +
> +#define MX6QDL_WEIM_NOR_PINGRP1 \
> + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 \
> + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 \
> + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 \
> + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 \
> + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 \
> + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 \
> + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 \
> + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 \
> + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 \
> + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 \
> + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 \
> + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 \
> + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 \
> + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 \
> + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 \
> + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 \
> + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 \
> + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 \
> + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 \
> + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 \
> + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 \
> + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 \
> + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 \
> + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 \
> + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 \
> + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 \
> + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 \
> + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 \
> + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 \
> + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 \
> + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 \
> + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 \
> + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 \
> + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 \
> + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 \
> + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 \
> + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 \
> + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 \
> + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 \
> + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 \
> + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 \
> + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 \
> + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
> +
> +#endif /* __DTS_IMX6QDL_PINGRP_H */
> --
> 1.8.4.2
>
>
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-01-10 8:24 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-01-07 18:12 [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Lucas Stach
2014-01-07 18:12 ` [PATCH 02/10] ARM: imx6q: update sabrelite DT Lucas Stach
2014-01-07 18:12 ` [PATCH 03/10] ARM: imx6: update SabreSD DTs Lucas Stach
2014-01-07 18:12 ` [PATCH 04/10] ARM: imx6: update phytec-pfla02 DT Lucas Stach
2014-01-07 18:12 ` [PATCH 05/10] ARM: imx6: update Carrier-1 DTs Lucas Stach
2014-01-07 18:12 ` [PATCH 06/10] ARM: imx6: update TQ DTs Lucas Stach
2014-01-07 18:12 ` [PATCH 07/10] ARM: imx6: update GK802 DT Lucas Stach
2014-01-07 18:12 ` [PATCH 08/10] ARM: imx6: update DMO RealQ7 DT Lucas Stach
2014-01-07 18:12 ` [PATCH 09/10] ARM: imx6: update DFI FS700 M60 DT Lucas Stach
2014-01-07 18:12 ` [PATCH 10/10] ARM: imx6: remove old pingroups Lucas Stach
2014-01-10 8:23 ` [PATCH 01/10] ARM: imx6: pull imx6qdl-pingrp.h from linux Sascha Hauer
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