* [PATCH 01/15] mci: imx-esdhc: Add i.MX25 compatible entry
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 02/15] ARM: dts: Add i.MX25 devicetree files Sascha Hauer
` (13 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 7664e7b..c5cf0ae 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -592,6 +592,8 @@ static int fsl_esdhc_probe(struct device_d *dev)
static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
{
+ .compatible = "fsl,imx25-esdhc",
+ }, {
.compatible = "fsl,imx51-esdhc",
}, {
.compatible = "fsl,imx53-esdhc",
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 02/15] ARM: dts: Add i.MX25 devicetree files
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
2014-01-31 14:23 ` [PATCH 01/15] mci: imx-esdhc: Add i.MX25 compatible entry Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 03/15] ARM: dts: i.MX25: Add mmc aliases Sascha Hauer
` (12 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-pinfunc.h | 494 ++++++++++++++++++++++++++++++++++++++
arch/arm/dts/imx25.dtsi | 552 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 1046 insertions(+)
create mode 100644 arch/arm/dts/imx25-pinfunc.h
create mode 100644 arch/arm/dts/imx25.dtsi
diff --git a/arch/arm/dts/imx25-pinfunc.h b/arch/arm/dts/imx25-pinfunc.h
new file mode 100644
index 0000000..9238a95
--- /dev/null
+++ b/arch/arm/dts/imx25-pinfunc.h
@@ -0,0 +1,494 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ * Based on imx35-pinfunc.h in the same directory Which is:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX25_PINFUNC_H
+#define __DTS_IMX25_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
+#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
+#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
+
+#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
+#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
+
+#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
+#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
+
+#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
+#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
+#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
+
+#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
+#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
+#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
+
+#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
+#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
+#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
+
+#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
+#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
+#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
+
+#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
+#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
+#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
+
+#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
+#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
+#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
+
+#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
+#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
+#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
+
+#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
+#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000
+#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000
+
+#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000
+#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000
+#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000
+
+#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000
+#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000
+#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000
+
+#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000
+#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000
+#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000
+
+#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
+#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000
+#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
+#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
+#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
+
+#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
+#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
+#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
+#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
+
+#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
+#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
+
+#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
+#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
+#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
+
+#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
+#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
+#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
+
+#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
+#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000
+#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000
+#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000
+
+#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000
+#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000
+
+#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
+#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
+#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
+
+#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
+#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
+#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
+
+#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
+#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
+#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
+
+#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
+#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
+
+#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
+#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
+
+#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
+#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
+#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000
+
+#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
+#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
+#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000
+
+#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
+#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
+#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000
+
+#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
+#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000
+
+#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
+#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000
+
+#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
+#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000
+
+#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
+#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000
+
+#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
+#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000
+
+#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
+#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000
+
+#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
+#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000
+
+#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
+#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000
+
+#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000
+#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000
+#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000
+
+#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000
+#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000
+#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000
+
+#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000
+#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000
+
+#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000
+#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000
+
+#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000
+#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000
+
+#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000
+#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000
+
+#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000
+#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000
+
+#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000
+#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
+
+#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
+#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
+
+#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
+#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
+
+#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
+#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
+
+#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
+#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
+
+#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
+
+#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
+
+#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
+
+#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
+
+#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
+#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000
+
+#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000
+#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000
+
+#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000
+#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
+
+#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
+
+#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
+#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
+#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
+
+#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000
+#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000
+#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
+
+#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
+#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
+#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
+
+#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
+#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
+
+#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
+#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
+#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
+
+#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
+#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
+#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
+
+#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
+#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
+#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
+#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
+#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
+
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
+
+#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
+#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000
+
+#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000
+#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
+
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
+
+#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
+#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
+
+#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
+#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
+
+#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
+#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
+#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
+
+#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
+#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
+#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
+
+#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
+#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
+
+#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
+#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
+
+#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
+#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
+#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
+
+#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
+#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
+#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
+#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
+#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
+#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000
+#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
+#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
+
+#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
+#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
+#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
+#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
+#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
+
+#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000
+#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001
+#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000
+#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001
+#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
+#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
+
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000
+
+#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000
+#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000
+#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000
+
+#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
+#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
+
+#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
+
+#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
+#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
+#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
+
+#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
+#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
+#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
+
+#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
+#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
+
+#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
+#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
+#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
+
+#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
+
+#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
+
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
+
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
+
+#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
+#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
+#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
+
+#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
+#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000
+
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
+
+#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/dts/imx25.dtsi b/arch/arm/dts/imx25.dtsi
new file mode 100644
index 0000000..32f760e
--- /dev/null
+++ b/arch/arm/dts/imx25.dtsi
@@ -0,0 +1,552 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx25-pinfunc.h"
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ spi2 = &spi3;
+ usb0 = &usbotg;
+ usb1 = &usbhost1;
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ asic: asic-interrupt-controller@68000000 {
+ compatible = "fsl,imx25-asic", "fsl,avic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x68000000 0x8000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&asic>;
+ ranges;
+
+ aips@43f00000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x43f00000 0x100000>;
+ ranges;
+
+ i2c1: i2c@43f80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f80000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@43f84000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f84000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <10>;
+ status = "disabled";
+ };
+
+ can1: can@43f88000 {
+ compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+ reg = <0x43f88000 0x4000>;
+ interrupts = <43>;
+ clocks = <&clks 75>, <&clks 75>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can2: can@43f8c000 {
+ compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
+ reg = <0x43f8c000 0x4000>;
+ interrupts = <44>;
+ clocks = <&clks 76>, <&clks 76>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial@43f90000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x43f90000 0x4000>;
+ interrupts = <45>;
+ clocks = <&clks 120>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@43f94000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x43f94000 0x4000>;
+ interrupts = <32>;
+ clocks = <&clks 121>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c2: i2c@43f98000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
+ reg = <0x43f98000 0x4000>;
+ clocks = <&clks 48>;
+ clock-names = "";
+ interrupts = <4>;
+ status = "disabled";
+ };
+
+ owire@43f9c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x43f9c000 0x4000>;
+ clocks = <&clks 51>;
+ clock-names = "";
+ interrupts = <2>;
+ status = "disabled";
+ };
+
+ spi1: cspi@43fa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x43fa4000 0x4000>;
+ clocks = <&clks 62>, <&clks 62>;
+ clock-names = "ipg", "per";
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ kpp@43fa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x43fa8000 0x4000>;
+ clocks = <&clks 102>;
+ clock-names = "";
+ interrupts = <24>;
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@43fac000 {
+ compatible = "fsl,imx25-iomuxc";
+ reg = <0x43fac000 0x4000>;
+ };
+
+ audmux: audmux@43fb0000 {
+ compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
+ reg = <0x43fb0000 0x4000>;
+ status = "disabled";
+ };
+ };
+
+ spba@50000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x40000>;
+ ranges;
+
+ spi3: cspi@50004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x50004000 0x4000>;
+ interrupts = <0>;
+ clocks = <&clks 80>, <&clks 80>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial@50008000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x50008000 0x4000>;
+ interrupts = <5>;
+ clocks = <&clks 123>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial@5000c000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x5000c000 0x4000>;
+ interrupts = <18>;
+ clocks = <&clks 122>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ spi2: cspi@50010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
+ reg = <0x50010000 0x4000>;
+ clocks = <&clks 79>, <&clks 79>;
+ clock-names = "ipg", "per";
+ interrupts = <13>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@50014000 {
+ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+ reg = <0x50014000 0x4000>;
+ interrupts = <11>;
+ clocks = <&clks 118>;
+ clock-names = "ipg";
+ dmas = <&sdma 24 1 0>,
+ <&sdma 25 1 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ esai@50018000 {
+ reg = <0x50018000 0x4000>;
+ interrupts = <7>;
+ };
+
+ uart5: serial@5002c000 {
+ compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+ reg = <0x5002c000 0x4000>;
+ interrupts = <40>;
+ clocks = <&clks 124>, <&clks 57>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ tsc: tsc@50030000 {
+ compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
+ reg = <0x50030000 0x4000>;
+ interrupts = <46>;
+ clocks = <&clks 119>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ ssi1: ssi@50034000 {
+ compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
+ reg = <0x50034000 0x4000>;
+ interrupts = <12>;
+ clocks = <&clks 117>;
+ clock-names = "ipg";
+ dmas = <&sdma 28 1 0>,
+ <&sdma 29 1 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ fec: ethernet@50038000 {
+ compatible = "fsl,imx25-fec";
+ reg = <0x50038000 0x4000>;
+ interrupts = <57>;
+ clocks = <&clks 88>, <&clks 65>;
+ clock-names = "ipg", "ahb";
+ status = "disabled";
+ };
+ };
+
+ aips@53f00000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x53f00000 0x100000>;
+ ranges;
+
+ clks: ccm@53f80000 {
+ compatible = "fsl,imx25-ccm";
+ reg = <0x53f80000 0x4000>;
+ interrupts = <31>;
+ #clock-cells = <1>;
+ };
+
+ gpt4: timer@53f84000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f84000 0x4000>;
+ clocks = <&clks 9>, <&clks 45>;
+ clock-names = "ipg", "per";
+ interrupts = <1>;
+ };
+
+ gpt3: timer@53f88000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f88000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <29>;
+ };
+
+ gpt2: timer@53f8c000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f8c000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <53>;
+ };
+
+ gpt1: timer@53f90000 {
+ compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
+ reg = <0x53f90000 0x4000>;
+ clocks = <&clks 9>, <&clks 47>;
+ clock-names = "ipg", "per";
+ interrupts = <54>;
+ };
+
+ epit1: timer@53f94000 {
+ compatible = "fsl,imx25-epit";
+ reg = <0x53f94000 0x4000>;
+ interrupts = <28>;
+ };
+
+ epit2: timer@53f98000 {
+ compatible = "fsl,imx25-epit";
+ reg = <0x53f98000 0x4000>;
+ interrupts = <27>;
+ };
+
+ gpio4: gpio@53f9c000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53f9c000 0x4000>;
+ interrupts = <23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm2: pwm@53fa0000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fa0000 0x4000>;
+ clocks = <&clks 106>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <36>;
+ };
+
+ gpio3: gpio@53fa4000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <16>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm3: pwm@53fa8000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fa8000 0x4000>;
+ clocks = <&clks 107>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <41>;
+ };
+
+ esdhc1: esdhc@53fb4000 {
+ compatible = "fsl,imx25-esdhc";
+ reg = <0x53fb4000 0x4000>;
+ interrupts = <9>;
+ clocks = <&clks 86>, <&clks 63>, <&clks 45>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ esdhc2: esdhc@53fb8000 {
+ compatible = "fsl,imx25-esdhc";
+ reg = <0x53fb8000 0x4000>;
+ interrupts = <8>;
+ clocks = <&clks 87>, <&clks 64>, <&clks 46>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ lcdc: lcdc@53fbc000 {
+ compatible = "fsl,imx25-fb", "fsl,imx21-fb";
+ reg = <0x53fbc000 0x4000>;
+ interrupts = <39>;
+ clocks = <&clks 103>, <&clks 66>, <&clks 49>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ slcdc@53fc0000 {
+ reg = <0x53fc0000 0x4000>;
+ interrupts = <38>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@53fc8000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ reg = <0x53fc8000 0x4000>;
+ clocks = <&clks 108>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <42>;
+ };
+
+ gpio1: gpio@53fcc000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fcc000 0x4000>;
+ interrupts = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@53fd0000 {
+ compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
+ reg = <0x53fd0000 0x4000>;
+ interrupts = <51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sdma: sdma@53fd4000 {
+ compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
+ reg = <0x53fd4000 0x4000>;
+ clocks = <&clks 112>, <&clks 68>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ interrupts = <34>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
+ };
+
+ wdog@53fdc000 {
+ compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
+ reg = <0x53fdc000 0x4000>;
+ clocks = <&clks 126>;
+ clock-names = "";
+ interrupts = <55>;
+ };
+
+ pwm1: pwm@53fe0000 {
+ compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
+ #pwm-cells = <2>;
+ reg = <0x53fe0000 0x4000>;
+ clocks = <&clks 105>, <&clks 36>;
+ clock-names = "ipg", "per";
+ interrupts = <26>;
+ };
+
+ iim: iim@53ff0000 {
+ compatible = "fsl,imx25-iim", "fsl,imx27-iim";
+ reg = <0x53ff0000 0x4000>;
+ interrupts = <19>;
+ clocks = <&clks 99>;
+ };
+
+ usbphy1: usbphy@1 {
+ compatible = "nop-usbphy";
+ status = "disabled";
+ };
+
+ usbphy2: usbphy@2 {
+ compatible = "nop-usbphy";
+ status = "disabled";
+ };
+
+ usbotg: usb@53ff4000 {
+ compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+ reg = <0x53ff4000 0x0200>;
+ interrupts = <37>;
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,usbmisc = <&usbmisc 0>;
+ status = "disabled";
+ };
+
+ usbhost1: usb@53ff4400 {
+ compatible = "fsl,imx25-usb", "fsl,imx27-usb";
+ reg = <0x53ff4400 0x0200>;
+ interrupts = <35>;
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,usbmisc = <&usbmisc 1>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@53ff4600 {
+ #index-cells = <1>;
+ compatible = "fsl,imx25-usbmisc";
+ clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+ clock-names = "ipg", "ahb", "per";
+ reg = <0x53ff4600 0x00f>;
+ status = "disabled";
+ };
+
+ dryice@53ffc000 {
+ compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
+ reg = <0x53ffc000 0x4000>;
+ clocks = <&clks 81>;
+ clock-names = "ipg";
+ interrupts = <25>;
+ };
+ };
+
+ emi@80000000 {
+ compatible = "fsl,emi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x3b002000>;
+ ranges;
+
+ nfc: nand@bb000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fsl,imx25-nand";
+ reg = <0xbb000000 0x2000>;
+ clocks = <&clks 50>;
+ clock-names = "";
+ interrupts = <33>;
+ status = "disabled";
+ };
+ };
+ };
+};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 03/15] ARM: dts: i.MX25: Add mmc aliases
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
2014-01-31 14:23 ` [PATCH 01/15] mci: imx-esdhc: Add i.MX25 compatible entry Sascha Hauer
2014-01-31 14:23 ` [PATCH 02/15] ARM: dts: Add i.MX25 devicetree files Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 04/15] ARM: dts: i.MX25: remove disabled status of usbmisc unit Sascha Hauer
` (11 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx25.dtsi b/arch/arm/dts/imx25.dtsi
index 32f760e..80ecd1f 100644
--- a/arch/arm/dts/imx25.dtsi
+++ b/arch/arm/dts/imx25.dtsi
@@ -21,6 +21,8 @@
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
+ mmc0 = &esdhc1;
+ mmc2 = &esdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 04/15] ARM: dts: i.MX25: remove disabled status of usbmisc unit
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (2 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 03/15] ARM: dts: i.MX25: Add mmc aliases Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 05/15] ARM: i.MX25: Add missing GPT clock lookups Sascha Hauer
` (10 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/imx25.dtsi b/arch/arm/dts/imx25.dtsi
index 80ecd1f..c6c0714 100644
--- a/arch/arm/dts/imx25.dtsi
+++ b/arch/arm/dts/imx25.dtsi
@@ -519,7 +519,6 @@
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
clock-names = "ipg", "ahb", "per";
reg = <0x53ff4600 0x00f>;
- status = "disabled";
};
dryice@53ffc000 {
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 05/15] ARM: i.MX25: Add missing GPT clock lookups
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (3 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 04/15] ARM: dts: i.MX25: remove disabled status of usbmisc unit Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 06/15] ARM: dts: Add i.MX25 Karo TX25 dts Sascha Hauer
` (9 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Only one GPT will be used, but with devicetree support we can't predict
which one it is, so we need the clock lookup for all GPTs to ensure
that the timer gets its clock.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/karo-tx25/lowlevel.c | 9 +++++++--
arch/arm/dts/Makefile | 1 +
arch/arm/mach-imx/clk-imx25.c | 3 +++
arch/arm/mach-imx/include/mach/imx25-regs.h | 3 +++
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 11f4138..a3a7784 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -75,9 +75,12 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
writel(esdctl, esdctlreg);
}
+extern char __dtb_imx25_karo_tx25_start[];
+
void __bare_init __naked barebox_arm_reset_vector(void)
{
uint32_t r;
+ uint32_t fdt;
arm_cpu_lowlevel_init();
@@ -136,6 +139,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
setup_uart();
+ fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset();
+
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0xa0000000)
@@ -161,8 +166,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
- imx25_barebox_boot_nand_external(0);
+ imx25_barebox_boot_nand_external(fdt);
#endif
out:
- imx25_barebox_entry(0);
+ imx25_barebox_entry(fdt);
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1718bde..ecfa5d9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -48,6 +48,7 @@ pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o
pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
+pbl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 9817990..4d8631c 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -140,6 +140,9 @@ static int imx25_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index 9ab0fb3..7181276 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -35,6 +35,9 @@
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000)
+#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000)
+#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000)
#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 06/15] ARM: dts: Add i.MX25 Karo TX25 dts
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (4 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 05/15] ARM: i.MX25: Add missing GPT clock lookups Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 07/15] ARM: dts: i.MX25: Add iram to devicetree Sascha Hauer
` (8 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx25-karo-tx25.dts | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
create mode 100644 arch/arm/dts/imx25-karo-tx25.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ecfa5d9..07508e3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-phytec-phycore.dtb
+dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb
dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \
imx27-phytec-phycard-s-som.dtb
dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
new file mode 100644
index 0000000..f8db366
--- /dev/null
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx25.dtsi"
+
+/ {
+ model = "Ka-Ro TX25";
+ compatible = "karo,imx25-tx25", "fsl,imx25";
+
+ memory {
+ reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&fec {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&nfc {
+ nand-on-flash-bbt;
+ status = "okay";
+};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 07/15] ARM: dts: i.MX25: Add iram to devicetree
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (5 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 06/15] ARM: dts: Add i.MX25 Karo TX25 dts Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 08/15] ARM: dts: Karo TX25: Add pinctrl nodes Sascha Hauer
` (7 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/imx25.dtsi b/arch/arm/dts/imx25.dtsi
index c6c0714..003c43c 100644
--- a/arch/arm/dts/imx25.dtsi
+++ b/arch/arm/dts/imx25.dtsi
@@ -530,6 +530,11 @@
};
};
+ iram: sram@78000000 {
+ compatible = "mmio-sram";
+ reg = <0x78000000 0x20000>;
+ };
+
emi@80000000 {
compatible = "fsl,emi-bus", "simple-bus";
#address-cells = <1>;
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 08/15] ARM: dts: Karo TX25: Add pinctrl nodes
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (6 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 07/15] ARM: dts: i.MX25: Add iram to devicetree Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 09/15] ARM: dts: Karo TX25: Add phy-reset-gpio Sascha Hauer
` (6 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-karo-tx25.dts | 53 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index f8db366..aeb1fce 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -21,16 +21,69 @@
};
};
+&iomuxc {
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
+ MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
+ MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
+ MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
+ MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */
+ MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
+ >;
+ };
+
+ pinctrl_nfc: nfcgrp {
+ fsl,pins = <
+ MX25_PAD_NF_CE0__NF_CE0 0x80000000
+ MX25_PAD_NFWE_B__NFWE_B 0x80000000
+ MX25_PAD_NFRE_B__NFRE_B 0x80000000
+ MX25_PAD_NFALE__NFALE 0x80000000
+ MX25_PAD_NFCLE__NFCLE 0x80000000
+ MX25_PAD_NFWP_B__NFWP_B 0x80000000
+ MX25_PAD_NFRB__NFRB 0x80000000
+ MX25_PAD_D7__D7 0x80000000
+ MX25_PAD_D6__D6 0x80000000
+ MX25_PAD_D5__D5 0x80000000
+ MX25_PAD_D4__D4 0x80000000
+ MX25_PAD_D3__D3 0x80000000
+ MX25_PAD_D2__D2 0x80000000
+ MX25_PAD_D1__D1 0x80000000
+ MX25_PAD_D0__D0 0x80000000
+ >;
+ };
+};
+
&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "okay";
};
&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nfc>;
nand-on-flash-bbt;
status = "okay";
};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 09/15] ARM: dts: Karo TX25: Add phy-reset-gpio
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (7 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 08/15] ARM: dts: Karo TX25: Add pinctrl nodes Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 10/15] ARM: dts: Karo TX25: add missing nfc properties Sascha Hauer
` (5 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-karo-tx25.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index aeb1fce..c82df09 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -77,6 +77,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
+ phy-reset-gpios = <&gpio4 7 0>;
phy-mode = "rmii";
status = "okay";
};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 10/15] ARM: dts: Karo TX25: add missing nfc properties
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (8 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 09/15] ARM: dts: Karo TX25: Add phy-reset-gpio Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 11/15] ARM: dts: Karo TX25: add phy supply for fec Sascha Hauer
` (4 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-karo-tx25.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index c82df09..b142445 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -86,5 +86,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-bus-width = <8>;
status = "okay";
};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 11/15] ARM: dts: Karo TX25: add phy supply for fec
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (9 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 10/15] ARM: dts: Karo TX25: add missing nfc properties Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 12/15] ARM: dts: Karo TX25: add barebox specifics Sascha Hauer
` (3 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-karo-tx25.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index b142445..182704e 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -16,6 +16,21 @@
model = "Ka-Ro TX25";
compatible = "karo,imx25-tx25", "fsl,imx25";
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_fec_phy: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 9 0>;
+ };
+ };
+
memory {
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
};
@@ -79,6 +94,7 @@
pinctrl-0 = <&pinctrl_fec>;
phy-reset-gpios = <&gpio4 7 0>;
phy-mode = "rmii";
+ phy-supply = <®_fec_phy>;
status = "okay";
};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 12/15] ARM: dts: Karo TX25: add barebox specifics
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (10 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 11/15] ARM: dts: Karo TX25: add phy supply for fec Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support Sascha Hauer
` (2 subsequent siblings)
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx25-karo-tx25.dts | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index 182704e..d661463 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -16,6 +16,15 @@
model = "Ka-Ro TX25";
compatible = "karo,imx25-tx25", "fsl,imx25";
+ chosen {
+ linux,stdout-path = &uart1;
+
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &nfc, "partname:environment";
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -98,11 +107,37 @@
status = "okay";
};
+&iim {
+ barebox,provide-mac-address = <&fec 0 26>;
+};
+
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-bus-width = <8>;
status = "okay";
+
+ partition@0 {
+ label = "boot";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@1 {
+ label = "environment";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition@2 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ partition@3 {
+ label = "root";
+ reg = <0x500000 0x7b00000>;
+ };
};
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (11 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 12/15] ARM: dts: Karo TX25: add barebox specifics Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:35 ` Alexander Shiyan
2014-01-31 14:23 ` [PATCH 14/15] ARM: i.MX: cleanup bootmode selection Sascha Hauer
2014-01-31 14:23 ` [PATCH 15/15] ARM: i.MX: Karo TX25: Switch to multiboard support Sascha Hauer
14 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/karo-tx25/board.c | 130 ++++++++++--------------------------
arch/arm/configs/tx25stk5_defconfig | 19 +++---
2 files changed, 47 insertions(+), 102 deletions(-)
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 7cdeecc..b4d553e 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -17,6 +17,8 @@
*
*/
+#define pr_fmt(fmt) "tx25: " fmt
+
#include <common.h>
#include <init.h>
#include <driver.h>
@@ -31,8 +33,6 @@
#include <partition.h>
#include <generated/mach-types.h>
#include <mach/imx-nand.h>
-#include <fec.h>
-#include <nand.h>
#include <mach/iomux-mx25.h>
#include <mach/generic.h>
#include <mach/iim.h>
@@ -41,78 +41,51 @@
#include <mach/bbu.h>
#include <asm/mmu.h>
-static struct fec_platform_data fec_info = {
- .xcv_type = PHY_INTERFACE_MODE_RMII,
- .phy_addr = 0x1f,
-};
-
-struct imx_nand_platform_data nand_info = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static iomux_v3_cfg_t karo_tx25_padsd_fec[] = {
- MX25_PAD_D11__GPIO_4_9, /* FEC PHY power on pin */
- MX25_PAD_D13__GPIO_4_7, /* FEC reset */
- MX25_PAD_FEC_MDC__FEC_MDC,
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_TDATA0__FEC_TDATA0,
- MX25_PAD_FEC_TDATA1__FEC_TDATA1,
- MX25_PAD_FEC_TX_EN__FEC_TX_EN,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-};
-
#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
+static struct gpio fec_gpios[] = {
+ {
+ .gpio = TX25_FEC_PWR_GPIO,
+ .flags = GPIOF_OUT_INIT_LOW,
+ .label = "fec-pwr",
+ }, {
+ .gpio = TX25_FEC_RST_GPIO,
+ .flags = GPIOF_OUT_INIT_LOW,
+ .label = "fec-rst",
+ },
+};
+
static void noinline gpio_fec_active(void)
{
- mxc_iomux_v3_setup_multiple_pads(karo_tx25_padsd_fec,
- ARRAY_SIZE(karo_tx25_padsd_fec));
+ int ret;
/* power down phy, put into reset */
- gpio_direction_output(TX25_FEC_PWR_GPIO, 0);
- gpio_direction_output(TX25_FEC_RST_GPIO, 0);
+ ret = gpio_request_array(fec_gpios, ARRAY_SIZE(fec_gpios));
+ if (ret) {
+ pr_err("Failed to request fec gpios: %s\n", strerror(-ret));
+ return;
+ }
udelay(10);
- /* power up phy, get out of reset */
- gpio_direction_output(TX25_FEC_PWR_GPIO, 1);
- gpio_direction_output(TX25_FEC_RST_GPIO, 1);
+ /* power up phy, but leave in reset */
+ gpio_set_value(TX25_FEC_PWR_GPIO, 1);
udelay(100);
- /* apply a reset to the powered phy again */
- gpio_direction_output(TX25_FEC_RST_GPIO, 0);
- udelay(100);
- gpio_direction_output(TX25_FEC_RST_GPIO, 1);
+ /* FEC driver picks up the reset gpio later */
+ gpio_free(TX25_FEC_RST_GPIO);
}
-static int tx25_devices_init(void)
+static int tx25_init(void)
{
- gpio_fec_active();
-
- imx25_iim_register_fec_ethaddr();
- imx25_add_fec(&fec_info);
-
- if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14))
- nand_info.width = 2;
-
- imx25_add_nand(&nand_info);
+ if (!of_machine_is_compatible("karo,imx25-tx25"))
+ return 0;
- devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
- dev_add_bb_dev("self_raw", "self0");
-
- devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
- dev_add_bb_dev("env_raw", "env0");
-
- add_mem_device("sram0", 0x78000000, 128 * 1024,
- IORESOURCE_MEM_WRITEABLE);
+ gpio_fec_active();
+ barebox_set_hostname("tx25");
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());
@@ -122,44 +95,7 @@ static int tx25_devices_init(void)
return 0;
}
-device_initcall(tx25_devices_init);
-
-static iomux_v3_cfg_t tx25_pads[] = {
- MX25_PAD_D12__GPIO_4_8,
- MX25_PAD_D10__GPIO_4_10,
- MX25_PAD_NF_CE0__NF_CE0,
- MX25_PAD_NFWE_B__NFWE_B,
- MX25_PAD_NFRE_B__NFRE_B,
- MX25_PAD_NFALE__NFALE,
- MX25_PAD_NFCLE__NFCLE,
- MX25_PAD_NFWP_B__NFWP_B,
- MX25_PAD_NFRB__NFRB,
- MX25_PAD_D7__D7,
- MX25_PAD_D6__D6,
- MX25_PAD_D5__D5,
- MX25_PAD_D4__D4,
- MX25_PAD_D3__D3,
- MX25_PAD_D2__D2,
- MX25_PAD_D1__D1,
- MX25_PAD_D0__D0,
- MX25_PAD_UART1_TXD__UART1_TXD,
- MX25_PAD_UART1_RXD__UART1_RXD,
- MX25_PAD_UART1_CTS__UART1_CTS,
- MX25_PAD_UART1_RTS__UART1_RTS,
-};
-
-static int tx25_console_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(tx25_pads, ARRAY_SIZE(tx25_pads));
-
- barebox_set_model("Ka-Ro TX25");
- barebox_set_hostname("tx25");
-
- imx25_add_uart0();
- return 0;
-}
-
-console_initcall(tx25_console_init);
+console_initcall(tx25_init);
static iomux_v3_cfg_t tx25_lcdc_gpios[] = {
MX25_PAD_A18__GPIO_2_4, /* LCD Reset (active LOW) */
@@ -236,6 +172,12 @@ static struct imx_fb_platform_data tx25_fb_data = {
static int tx25_init_fb(void)
{
+ if (!IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX))
+ return 0;
+
+ if (!of_machine_is_compatible("karo,imx25-tx25"))
+ return 0;
+
tx25_fb_enable(0);
mxc_iomux_v3_setup_multiple_pads(tx25_lcdc_gpios,
diff --git a/arch/arm/configs/tx25stk5_defconfig b/arch/arm/configs/tx25stk5_defconfig
index 365a940..32a6183 100644
--- a/arch/arm/configs/tx25stk5_defconfig
+++ b/arch/arm/configs/tx25stk5_defconfig
@@ -1,7 +1,8 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="imx25-karo-tx25"
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
-CONFIG_ARCH_IMX25=y
CONFIG_MACH_TX25=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
@@ -17,6 +18,7 @@ CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx25/env"
CONFIG_RESET_SOURCE=y
@@ -28,9 +30,7 @@ CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_DIRNAME=y
CONFIG_CMD_LN=y
-CONFIG_CMD_READLINK=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
@@ -40,7 +40,6 @@ CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
-CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
@@ -51,10 +50,10 @@ CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OFTREE_PROBE=y
-CONFIG_CMD_MTEST=y
-CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
CONFIG_CMD_SPLASH=y
+CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
@@ -63,20 +62,24 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_WD=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
-CONFIG_UBI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
+CONFIG_SRAM=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_FS_TFTP=y
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support
2014-01-31 14:23 ` [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support Sascha Hauer
@ 2014-01-31 14:35 ` Alexander Shiyan
2014-02-01 18:13 ` Sascha Hauer
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Shiyan @ 2014-01-31 14:35 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Пятница, 31 января 2014, 15:23 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boards/karo-tx25/board.c | 130 ++++++++++--------------------------
...
> #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
> #define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
>
> +static struct gpio fec_gpios[] = {
> + {
> + .gpio = TX25_FEC_PWR_GPIO,
> + .flags = GPIOF_OUT_INIT_LOW,
> + .label = "fec-pwr",
> + }, {
> + .gpio = TX25_FEC_RST_GPIO,
> + .flags = GPIOF_OUT_INIT_LOW,
> + .label = "fec-rst",
> + },
> +};
You have added these pins to DTS in PATCH 08/15.
What a reason to setup it twice?
---
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support
2014-01-31 14:35 ` Alexander Shiyan
@ 2014-02-01 18:13 ` Sascha Hauer
2014-02-01 18:24 ` Alexander Shiyan
0 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2014-02-01 18:13 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Fri, Jan 31, 2014 at 06:35:36PM +0400, Alexander Shiyan wrote:
> Пятница, 31 января 2014, 15:23 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/boards/karo-tx25/board.c | 130 ++++++++++--------------------------
> ...
> > #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
> > #define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
> >
> > +static struct gpio fec_gpios[] = {
> > + {
> > + .gpio = TX25_FEC_PWR_GPIO,
> > + .flags = GPIOF_OUT_INIT_LOW,
> > + .label = "fec-pwr",
> > + }, {
> > + .gpio = TX25_FEC_RST_GPIO,
> > + .flags = GPIOF_OUT_INIT_LOW,
> > + .label = "fec-rst",
> > + },
> > +};
>
> You have added these pins to DTS in PATCH 08/15.
> What a reason to setup it twice?
08/15 only adds the pinctrl nodes. The code here is to power on the phy
as we do not have regulator support yet. Hm I just wonder if this works
as expected. I did the phy power on before the fec driver initializes,
but this also means that the phy power on is done before the pinctrl is
configured.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support
2014-02-01 18:13 ` Sascha Hauer
@ 2014-02-01 18:24 ` Alexander Shiyan
2014-02-01 18:37 ` Sascha Hauer
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Shiyan @ 2014-02-01 18:24 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Суббота, 1 февраля 2014, 19:13 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> On Fri, Jan 31, 2014 at 06:35:36PM +0400, Alexander Shiyan wrote:
> > Пятница, 31 января 2014, 15:23 +01:00 от Sascha Hauer
> <s.hauer@pengutronix.de>:
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > arch/arm/boards/karo-tx25/board.c | 130
> ++++++++++--------------------------
> > ...
> > > #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
> > > #define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
> > >
> > > +static struct gpio fec_gpios[] = {
> > > + {
> > > + .gpio = TX25_FEC_PWR_GPIO,
> > > + .flags = GPIOF_OUT_INIT_LOW,
> > > + .label = "fec-pwr",
> > > + }, {
> > > + .gpio = TX25_FEC_RST_GPIO,
> > > + .flags = GPIOF_OUT_INIT_LOW,
> > > + .label = "fec-rst",
> > > + },
> > > +};
> >
> > You have added these pins to DTS in PATCH 08/15.
> > What a reason to setup it twice?
>
> 08/15 only adds the pinctrl nodes. The code here is to power on the phy
> as we do not have regulator support yet.
Ok, I agree about PWR pin, but what about RST? Afaik we can handle
it from the FEC driver code.
---
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support
2014-02-01 18:24 ` Alexander Shiyan
@ 2014-02-01 18:37 ` Sascha Hauer
0 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-02-01 18:37 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Sat, Feb 01, 2014 at 10:24:59PM +0400, Alexander Shiyan wrote:
> Суббота, 1 февраля 2014, 19:13 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> > On Fri, Jan 31, 2014 at 06:35:36PM +0400, Alexander Shiyan wrote:
> > > Пятница, 31 января 2014, 15:23 +01:00 от Sascha Hauer
> > <s.hauer@pengutronix.de>:
> > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > ---
> > > > arch/arm/boards/karo-tx25/board.c | 130
> > ++++++++++--------------------------
> > > ...
> > > > #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9)
> > > > #define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7)
> > > >
> > > > +static struct gpio fec_gpios[] = {
> > > > + {
> > > > + .gpio = TX25_FEC_PWR_GPIO,
> > > > + .flags = GPIOF_OUT_INIT_LOW,
> > > > + .label = "fec-pwr",
> > > > + }, {
> > > > + .gpio = TX25_FEC_RST_GPIO,
> > > > + .flags = GPIOF_OUT_INIT_LOW,
> > > > + .label = "fec-rst",
> > > > + },
> > > > +};
> > >
> > > You have added these pins to DTS in PATCH 08/15.
> > > What a reason to setup it twice?
> >
> > 08/15 only adds the pinctrl nodes. The code here is to power on the phy
> > as we do not have regulator support yet.
>
> Ok, I agree about PWR pin, but what about RST? Afaik we can handle
> it from the FEC driver code.
It is handled in the FEC driver code. The code above just makes sure
that the phy is still in reset after it's powered up. The reset is then
released later in the FEC driver.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 14/15] ARM: i.MX: cleanup bootmode selection
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (12 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 13/15] ARM: i.MX25: Karo TX25: Switch to devicetree support Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
2014-01-31 14:23 ` [PATCH 15/15] ARM: i.MX: Karo TX25: Switch to multiboard support Sascha Hauer
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Which bootmode is selected has no longer to be chosen by Kconfig. The
boards can decide themselves which bootmode they want to support. This
makes it unnecesary to ask the user which bootmode shall be supported,
so the "Select boot mode" becomes invisible and both support will be
compiled in as needed by the boards. NAND_IMX_BOOT goes away and the
already existing ARCH_IMX_EXTERNAL_BOOT_NAND can now be used for the
boards to depend on external nand boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 10 ++++-----
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 4 ++--
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 25 +++++++++++----------
.../boards/freescale-mx25-3-stack/lowlevel_init.S | 5 +++--
.../boards/freescale-mx35-3-stack/lowlevel_init.S | 4 ++--
arch/arm/boards/guf-cupid/lowlevel.c | 21 ++++++++---------
arch/arm/boards/guf-neso/lowlevel.c | 11 ++++-----
arch/arm/boards/imx21ads/lowlevel_init.S | 5 +++--
arch/arm/boards/pcm037/lowlevel.c | 14 ++++++------
arch/arm/boards/pcm038/lowlevel.c | 10 ++++-----
arch/arm/boards/pcm043/lowlevel.c | 25 +++++++++++----------
arch/arm/boards/phycard-i.MX27/lowlevel.c | 4 ----
arch/arm/mach-imx/Kconfig | 26 +++++-----------------
13 files changed, 76 insertions(+), 88 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index 07659f5..f0bf2c7 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -127,12 +127,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* setup a stack to be able to call imx25_barebox_boot_nand_external() */
- arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* setup a stack to be able to call imx25_barebox_boot_nand_external() */
+ arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12);
- imx25_barebox_boot_nand_external(0);
-#endif
+ imx25_barebox_boot_nand_external(0);
+ }
out:
imx25_barebox_entry(0);
}
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index ae1391c..f8e3c23 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -123,13 +123,13 @@ barebox_arm_reset_vector:
1:
sdram_init
-#ifdef CONFIG_NAND_IMX_BOOT
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* Setup a temporary stack in SDRAM */
ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
mov r0, #0
b imx27_barebox_boot_nand_external
-#endif /* CONFIG_NAND_IMX_BOOT */
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
b imx27_barebox_entry
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index d03e110..b8ba3c8 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -130,18 +130,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- r &= ~(0xf << 28);
- r |= 0x1 << 28;
- writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
-
- imx35_barebox_boot_nand_external(0);
-#endif
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* Speed up NAND controller by adjusting the NFC divider */
+ r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+ r &= ~(0xf << 28);
+ r |= 0x1 << 28;
+ writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+
+ /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
+ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+
+ imx35_barebox_boot_nand_external(0);
+ }
+
out:
imx35_barebox_entry(0);
}
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index 8446c6f..4ca4c82 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -97,13 +97,14 @@ barebox_arm_reset_vector:
ldr r3, ESDCTL_DELAY5
str r3, [r0, #0x30]
-#ifdef CONFIG_NAND_IMX_BOOT
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
+
/* Setup a temporary stack in SRAM */
ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
mov r0, #0
b imx25_barebox_boot_nand_external
-#endif /* CONFIG_NAND_IMX_BOOT */
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
b imx25_barebox_entry
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index cb9ed0a..6d37f35 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -154,13 +154,13 @@ barebox_arm_reset_vector:
ldr r3, =ESDCTL_DELAY_LINE5
str r3, [r0, #0x30]
-#ifdef CONFIG_NAND_IMX_BOOT
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* Setup a temporary stack in internal SRAM */
ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
mov r0, #0
b imx35_barebox_boot_nand_external
-#endif /* CONFIG_NAND_IMX_BOOT */
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
b imx35_barebox_entry
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index d5dce16..4c0de9c 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -306,18 +306,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */
setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* Speed up NAND controller by adjusting the NFC divider */
- r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- r0 &= ~(0xf << 28);
- r0 |= 0x1 << 28;
- writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* Speed up NAND controller by adjusting the NFC divider */
+ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+ r0 &= ~(0xf << 28);
+ r0 |= 0x1 << 28;
+ writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+ /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
+ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+
+ imx35_barebox_boot_nand_external(0);
+ }
- imx35_barebox_boot_nand_external(0);
-#endif
out:
imx35_barebox_entry(0);
}
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index c3323ee..d26ee73 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -86,12 +86,13 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* setup a stack to be able to call imx27_barebox_boot_nand_external() */
- arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* setup a stack to be able to call imx27_barebox_boot_nand_external() */
+ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
+
+ imx27_barebox_boot_nand_external(0);
+ }
- imx27_barebox_boot_nand_external(0);
-#endif
out:
imx27_barebox_entry(0);
}
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index 09ca4a4..471390f 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -118,12 +118,13 @@ barebox_arm_reset_vector:
ldr r1, =0x6419a007
str r1, [r0]
-#ifdef CONFIG_NAND_IMX_BOOT
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND {
+
/* Setup a temporary stack in SRAM */
ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4
b imx21_barebox_boot_nand_external
-#endif /* CONFIG_NAND_IMX_BOOT */
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
ret:
mov r0, #0xc0000000
diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c
index ae2d8c0..cd894c2 100644
--- a/arch/arm/boards/pcm037/lowlevel.c
+++ b/arch/arm/boards/pcm037/lowlevel.c
@@ -125,12 +125,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
#endif
-#ifdef CONFIG_NAND_IMX_BOOT
- /* setup a stack to be able to call imx31_barebox_boot_nand_external() */
- arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* setup a stack to be able to call imx31_barebox_boot_nand_external() */
+ arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
- imx31_barebox_boot_nand_external(0);
-#else
- imx31_barebox_entry(0);
-#endif
+ imx31_barebox_boot_nand_external(0);
+ } else {
+ imx31_barebox_entry(0);
+ }
}
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index bb948f1..4f55af8 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -93,12 +93,12 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* setup a stack to be able to call mx27_barebox_boot_nand_external() */
- arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* setup a stack to be able to call mx27_barebox_boot_nand_external() */
+ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
- imx27_barebox_boot_nand_external(0);
-#endif
+ imx27_barebox_boot_nand_external(0);
+ }
out:
imx27_barebox_entry(0);
}
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index 64b0382..8376bb4 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -182,18 +182,19 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* enable Auto-Refresh */
writel(0x00002000, esdctl_base + IMX_ESDCTL1);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* Speed up NAND controller by adjusting the NFC divider */
- r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- r &= ~(0xf << 28);
- r |= 0x1 << 28;
- writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
-
- imx35_barebox_boot_nand_external(0);
-#endif
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
+ /* Speed up NAND controller by adjusting the NFC divider */
+ r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+ r &= ~(0xf << 28);
+ r |= 0x1 << 28;
+ writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
+
+ /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
+ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+
+ imx35_barebox_boot_nand_external(0);
+ }
+
out:
imx35_barebox_entry(0);
}
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c
index 33de1c0..5b3bdaf 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel.c
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c
@@ -99,9 +99,5 @@ void __bare_init __naked barebox_arm_reset_vector(void)
sdram_init();
-#ifdef CONFIG_NAND_IMX_BOOT
imx27_barebox_boot_nand_external(0);
-#else
- imx27_barebox_entry(0);
-#endif
}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 359f06c..55038e8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -38,8 +38,9 @@ config ARCH_TEXT_BASE
default 0x4fc00000 if MACH_PHYTEC_PFLA02
default 0x4fc00000 if MACH_DFI_FS700_M60
-choice
- prompt "Select boot mode"
+config ARCH_IMX_INTERNAL_BOOT
+ bool "support internal boot mode"
+ depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
depends on !HAVE_PBL_MULTI_IMAGES
help
i.MX processors support two different boot modes. With the internal
@@ -58,16 +59,6 @@ choice
The external boot mode is supported on older i.MX processors (i.MX1,
i.MX21, i.MX25, i.MX27, i.MX31, i.MX35).
-config ARCH_IMX_INTERNAL_BOOT
- bool "support internal boot mode"
- depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
-
-config ARCH_IMX_EXTERNAL_BOOT
- bool "support external boot mode"
- depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35
-
-endchoice
-
config ARCH_IMX_IMXIMAGE
bool
default y
@@ -105,16 +96,10 @@ config ARCH_IMX_INTERNAL_BOOT_SERIAL
endchoice
-config NAND_IMX_BOOT
- bool
- depends on ARCH_IMX_EXTERNAL_BOOT_NAND
- default y
-
config ARCH_IMX_EXTERNAL_BOOT_NAND
bool
- depends on !ARCH_IMX1
- prompt "Support Starting barebox from NAND"
- depends on ARCH_IMX_EXTERNAL_BOOT
+ depends on ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35
+ prompt "Support Starting barebox from NAND in external bootmode"
config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
bool
@@ -319,6 +304,7 @@ config MACH_PCA100
bool "phyCard-i.MX27"
select ARCH_IMX27
select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 15/15] ARM: i.MX: Karo TX25: Switch to multiboard support
2014-01-31 14:23 i.MX25 devicetree support Sascha Hauer
` (13 preceding siblings ...)
2014-01-31 14:23 ` [PATCH 14/15] ARM: i.MX: cleanup bootmode selection Sascha Hauer
@ 2014-01-31 14:23 ` Sascha Hauer
14 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2014-01-31 14:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/karo-tx25/board.c | 2 +-
arch/arm/boards/karo-tx25/lowlevel.c | 26 +++++++++++++++-----------
arch/arm/configs/tx25stk5_defconfig | 20 ++++++++++++++++----
arch/arm/mach-imx/Kconfig | 14 +++++++-------
images/Makefile.imx | 5 +++++
5 files changed, 44 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index b4d553e..59c81b2 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -89,7 +89,7 @@ static int tx25_init(void)
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());
- imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
+ imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
BBU_HANDLER_FLAG_DEFAULT);
return 0;
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index a3a7784..be27bc7 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -75,12 +75,9 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
writel(esdctl, esdctlreg);
}
-extern char __dtb_imx25_karo_tx25_start[];
-
-void __bare_init __naked barebox_arm_reset_vector(void)
+static void __bare_init karo_tx25_common_init(uint32_t fdt)
{
uint32_t r;
- uint32_t fdt;
arm_cpu_lowlevel_init();
@@ -139,8 +136,6 @@ void __bare_init __naked barebox_arm_reset_vector(void)
setup_uart();
- fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset();
-
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0xa0000000)
@@ -162,12 +157,21 @@ void __bare_init __naked barebox_arm_reset_vector(void)
setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL);
setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL);
-#ifdef CONFIG_NAND_IMX_BOOT
- /* setup a stack to be able to call imx25_barebox_boot_nand_external() */
- arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
-
imx25_barebox_boot_nand_external(fdt);
-#endif
+
out:
imx25_barebox_entry(fdt);
}
+
+extern char __dtb_imx25_karo_tx25_start[];
+
+ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2)
+{
+ uint32_t fdt;
+
+ arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
+
+ fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset();
+
+ karo_tx25_common_init(fdt);
+}
diff --git a/arch/arm/configs/tx25stk5_defconfig b/arch/arm/configs/tx25stk5_defconfig
index 32a6183..5c9338d 100644
--- a/arch/arm/configs/tx25stk5_defconfig
+++ b/arch/arm/configs/tx25stk5_defconfig
@@ -1,14 +1,24 @@
-CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="imx25-karo-tx25"
CONFIG_ARCH_IMX=y
-CONFIG_ARCH_IMX_EXTERNAL_BOOT=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
+CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TX25=y
+CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
+CONFIG_MACH_FREESCALE_MX51_PDK=y
+CONFIG_MACH_FREESCALE_MX53_LOCO=y
+CONFIG_MACH_TQMA53=y
+CONFIG_MACH_FREESCALE_MX53_VMX53=y
+CONFIG_MACH_PHYTEC_PFLA02=y
+CONFIG_MACH_DFI_FS700_M60=y
+CONFIG_MACH_REALQ7=y
+CONFIG_MACH_GK802=y
+CONFIG_MACH_TQMA6X=y
+CONFIG_MACH_SABRELITE=y
+CONFIG_MACH_NITROGEN6X=y
+CONFIG_MACH_SOLIDRUN_HUMMINGBOARD=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
-CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x91d00000
CONFIG_MALLOC_SIZE=0x1000000
@@ -26,6 +36,7 @@ CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
@@ -77,6 +88,7 @@ CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
+CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_SRAM=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 55038e8..f60ef2c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -167,6 +167,13 @@ config IMX_MULTI_BOARDS
if IMX_MULTI_BOARDS
+config MACH_TX25
+ bool "Ka-Ro TX25"
+ select ARCH_IMX25
+ select ARCH_IMX_EXTERNAL_BOOT_NAND
+ help
+ Say Y here if you are using the Ka-Ro tx25 board
+
config MACH_EFIKA_MX_SMARTBOOK
bool "Efika MX smartbook"
select ARCH_IMX51
@@ -275,13 +282,6 @@ config MACH_FREESCALE_MX25_3STACK
Say Y here if you are using the Freescale MX25 3stack board equipped
with a Freescale i.MX25 Processor
-config MACH_TX25
- bool "Ka-Ro TX25"
- select ARCH_IMX25
- select HAVE_DEFAULT_ENVIRONMENT_NEW
- help
- Say Y here if you are using the Ka-Ro tx25 board
-
# ----------------------------------------------------------
comment "i.MX27 Boards"
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 3318fcf..dd12242 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -9,6 +9,11 @@ $(obj)/%.imximg: $(obj)/% FORCE
board = $(srctree)/arch/$(ARCH)/boards
+# ----------------------- i.MX25 based boards ---------------------------
+pblx-$(CONFIG_MACH_TX25) += start_imx25_karo_tx25
+FILE_barebox-karo-tx25.img = start_imx25_karo_tx25.pblx
+image-$(CONFIG_MACH_TX25) += barebox-karo-tx25.img
+
# ----------------------- i.MX51 based boards ---------------------------
pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage
CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg
--
1.8.5.3
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^ permalink raw reply [flat|nested] 20+ messages in thread