[PATCH v2 0/8] Lowlevel Tegra3 support

[PATCH v2 0/8] Lowlevel Tegra3 support

[Lucas Stach]

This is the very basic Tegra3 support. All highlevel things
like pinmux and other drivers still missing.

Allows to start the high performance CPU cluster on Tegra3
and start executing code there.

v2: Use __always_inline compiler macro.

Lucas Stach (8):
  tegra: add -fno-jump-tables to lowlevel code
  tegra: lowlevel: switch to __always_inline macro
  tegra: add break to switch statements
  tegra: add lowlevel delay function
  tegra: add Tegra3 to relevant lowlevel functions
  tegra: add lowlevel DVC
  tegra: set AHB clock rate early
  tegra: add Tegra3 startup

 arch/arm/mach-tegra/Makefile                    |  4 +-
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 72 +++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/lowlevel.h     | 85 ++++++++++++++++++++++---
 arch/arm/mach-tegra/include/mach/tegra20-car.h  | 12 ++++
 arch/arm/mach-tegra/include/mach/tegra30-car.h  | 31 +++++++++
 arch/arm/mach-tegra/include/mach/tegra30-flow.h | 23 +++++++
 arch/arm/mach-tegra/tegra_avp_init.c            | 46 ++++++++++++-
 7 files changed, 261 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-car.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-flow.h

-- 
1.8.5.3


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[PATCH v2 1/8] tegra: add -fno-jump-tables to lowlevel code

[Lucas Stach]

Lowlevel code runs when not relocated yet, so we have to make extra sure
not to emit jump-tables with absolute adresses when evaluating switch
statements.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0fa8430..791d5d4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
-CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
-CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
+CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
 lwl-y += tegra_avp_init.o
 lwl-y += tegra_maincomplex_init.o
 obj-y += tegra20.o
-- 
1.8.5.3


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[PATCH v2 2/8] tegra: lowlevel: switch to __always_inline macro

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 472348a..fb06e4f 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -21,6 +21,7 @@
  * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
  */
 
+#include <linux/compiler.h>
 #include <sizes.h>
 #include <io.h>
 #include <mach/iomap.h>
@@ -40,7 +41,7 @@
 #define T20_ODMDATA_UARTID_SHIFT	15
 #define T20_ODMDATA_UARTID_MASK		(7 << T20_ODMDATA_UARTID_SHIFT)
 
-static inline __attribute__((always_inline))
+static __always_inline
 u32 tegra_get_odmdata(void)
 {
 	u32 bctsize, bctptr, odmdata;
@@ -63,7 +64,7 @@ enum tegra_chiptype {
 	TEGRA20 = 0,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 enum tegra_chiptype tegra_get_chiptype(void)
 {
 	u32 hidrev;
@@ -78,7 +79,7 @@ enum tegra_chiptype tegra_get_chiptype(void)
 	}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_get_num_cores(void)
 {
 	switch (tegra_get_chiptype()) {
@@ -92,7 +93,7 @@ int tegra_get_num_cores(void)
 }
 
 /* Runtime data */
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_cpu_is_maincomplex(void)
 {
 	u32 tag0;
@@ -102,7 +103,7 @@ int tegra_cpu_is_maincomplex(void)
 	return (tag0 & 0xff) == 0x55;
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint32_t tegra20_get_ramsize(void)
 {
 	switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
@@ -125,7 +126,7 @@ static long uart_id_to_base[] = {
 	TEGRA_UARTE_BASE,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 long tegra20_get_debuguart_base(void)
 {
 	u32 odmdata;
@@ -152,7 +153,7 @@ long tegra20_get_debuguart_base(void)
 #define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
 #define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
 
-static inline unsigned __attribute__((always_inline))
+static __always_inline
 int tegra_get_osc_clock(void)
 {
 	u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
@@ -172,7 +173,7 @@ int tegra_get_osc_clock(void)
 	}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void tegra_cpu_lowlevel_setup(void)
 {
 	uint32_t r;
-- 
1.8.5.3


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[PATCH v2 3/8] tegra: add break to switch statements

[Lucas Stach]

Avoids a possible miscompilation.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index fb06e4f..20de1b2 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -74,8 +74,10 @@ enum tegra_chiptype tegra_get_chiptype(void)
 	switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
 	case 0x20:
 		return TEGRA20;
+		break;
 	default:
 		return TEGRA_UNK_REV;
+		break;
 	}
 }
 
@@ -110,11 +112,14 @@ uint32_t tegra20_get_ramsize(void)
 		T20_ODMDATA_RAMSIZE_SHIFT) {
 	case 1:
 		return SZ_256M;
+		break;
 	default:
 	case 2:
 		return SZ_512M;
+		break;
 	case 3:
 		return SZ_1G;
+		break;
 	}
 }
 
@@ -162,14 +167,19 @@ int tegra_get_osc_clock(void)
 		CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
 	case 0:
 		return 13000000;
+		break;
 	case 1:
 		return 19200000;
+		break;
 	case 2:
 		return 12000000;
+		break;
 	case 3:
 		return 26000000;
+		break;
 	default:
 		return 0;
+		break;
 	}
 }
 
-- 
1.8.5.3


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[PATCH v2 4/8] tegra: add lowlevel delay function

[Lucas Stach]

For proper startup we need to give clocks and IO signals some time to
stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit
pickier.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 44 +++++++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra_avp_init.c        |  5 ++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 20de1b2..85ab7ef 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -183,6 +183,49 @@ int tegra_get_osc_clock(void)
 	}
 }
 
+#define TIMER_CNTR_1US	0x00
+#define TIMER_USEC_CFG	0x04
+
+static __always_inline
+void tegra_ll_delay_setup(void)
+{
+	u32 reg;
+
+	/*
+	 * calibrate timer to run at 1MHz
+	 * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
+	 * representing the divisor and bits [8:15] representing the dividend
+	 * each in n+1 form.
+	 */
+	switch (tegra_get_osc_clock()) {
+	case 12000000:
+		reg = 0x000b;
+		break;
+	case 13000000:
+		reg = 0x000c;
+		break;
+	case 19200000:
+		reg = 0x045f;
+		break;
+	case 26000000:
+		reg = 0x0019;
+		break;
+	default:
+		reg = 0;
+		break;
+	}
+
+	writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG);
+}
+
+static __always_inline
+void tegra_ll_delay_usec(int delay)
+{
+	int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay;
+
+	while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0);
+}
+
 static __always_inline
 void tegra_cpu_lowlevel_setup(void)
 {
@@ -193,6 +236,7 @@ void tegra_cpu_lowlevel_setup(void)
 	r &= ~0x1f;
 	r |= 0xd3;
 	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+	tegra_ll_delay_setup();
 }
 
 /* reset vector for the AVP, to be called from board reset vector */
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 2c2d6fc..9f8ccf3 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -158,6 +158,9 @@ static void start_cpu0_clocks(void)
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
 	reg |= CRC_CLK_OUT_ENB_L_CPU;
 	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
+
+	/* give clocks some time to settle */
+	tegra_ll_delay_usec(300);
 }
 
 static void maincomplex_powerup(void)
@@ -175,6 +178,8 @@ static void maincomplex_powerup(void)
 		reg = readl(TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
 		reg |= PMC_REMOVE_CLAMPING_CMD_CPU;
 		writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
+
+		tegra_ll_delay_usec(1000);
 	}
 }
 void tegra_avp_reset_vector(uint32_t boarddata)
-- 
1.8.5.3


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[PATCH v2 5/8] tegra: add Tegra3 to relevant lowlevel functions

[Lucas Stach]

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 85ab7ef..b39e30e 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -62,6 +62,7 @@ u32 tegra_get_odmdata(void)
 enum tegra_chiptype {
 	TEGRA_UNK_REV = -1,
 	TEGRA20 = 0,
+	TEGRA30 = 1,
 };
 
 static __always_inline
@@ -75,6 +76,9 @@ enum tegra_chiptype tegra_get_chiptype(void)
 	case 0x20:
 		return TEGRA20;
 		break;
+	case 0x30:
+		return TEGRA30;
+		break;
 	default:
 		return TEGRA_UNK_REV;
 		break;
@@ -88,6 +92,9 @@ int tegra_get_num_cores(void)
 	case TEGRA20:
 		return 2;
 		break;
+	case TEGRA30:
+		return 4;
+		break;
 	default:
 		return 0;
 		break;
-- 
1.8.5.3


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[PATCH v2 6/8] tegra: add lowlevel DVC

[Lucas Stach]

Allows to talk to external PMIC devices to bring up CPU rail.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h | 72 +++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/lowlevel.h     |  7 ++-
 arch/arm/mach-tegra/include/mach/tegra20-car.h  |  8 +++
 3 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/lowlevel-dvc.h

diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
new file mode 100644
index 0000000..f7f6328
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/compiler.h>
+#include "mach/tegra20-car.h"
+#include "mach/lowlevel.h"
+
+static __always_inline
+void tegra_dvc_init(void)
+{
+	int div;
+	u32 reg;
+
+	/* reset DVC controller and enable clock */
+	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET);
+	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+	reg |= CRC_CLK_OUT_ENB_H_DVC;
+	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+
+	/* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */
+	div = ((tegra_get_osc_clock() * 3) >> 22) - 1;
+	writel((div) | (3 << 30),
+	       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC);
+
+	/* clear DVC reset */
+	tegra_ll_delay_usec(3);
+	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
+}
+
+#define TEGRA_I2C_CNFG		0x00
+#define TEGRA_I2C_CMD_ADDR0	0x04
+#define TEGRA_I2C_CMD_DATA1	0x0c
+#define TEGRA_I2C_SEND_2_BYTES	0x0a02
+
+static __always_inline
+void tegra_dvc_write_addr(u32 addr, u32 config)
+{
+	writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0);
+	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static __always_inline
+void tegra_dvc_write_data(u32 data, u32 config)
+{
+	writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1);
+	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static inline __attribute__((always_inline))
+void tegra30_tps65911_cpu_rail_enable(void)
+{
+	tegra_dvc_write_addr(0x5a, 2);
+	/* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */
+	tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(1000);
+	/* reg 27, VDDctrl enable */
+	tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+}
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index b39e30e..0fad195 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,6 +21,9 @@
  * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
  */
 
+#ifndef __TEGRA_LOWLEVEL_H
+#define __TEGRA_LOWLEVEL_H
+
 #include <linux/compiler.h>
 #include <sizes.h>
 #include <io.h>
@@ -251,3 +254,5 @@ void tegra_avp_reset_vector(uint32_t boarddata);
 
 /* reset vector for the main CPU complex */
 void tegra_maincomplex_entry(void);
+
+#endif /* __TEGRA_LOWLEVEL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index 64873d7..a5441de 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -46,6 +46,9 @@
 #define CRC_CLK_OUT_ENB_L_AC97		(1 << 3)
 #define CRC_CLK_OUT_ENB_L_CPU		(1 << 0)
 
+#define CRC_CLK_OUT_ENB_H		0x014
+#define CRC_CLK_OUT_ENB_H_DVC		(1 << 15)
+
 #define CRC_CCLK_BURST_POLICY		0x020
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT	28
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ	8
@@ -273,6 +276,11 @@
 
 #define CRC_RST_DEV_L_CLR		0x304
 
+#define CRC_RST_DEV_H_SET		0x308
+#define CRC_RST_DEV_H_DVC		(1 << 15)
+
+#define CRC_RST_DEV_H_CLR		0x30c
+
 #define CRC_RST_CPU_CMPLX_SET		0x340
 
 #define CRC_RST_CPU_CMPLX_CLR		0x344
-- 
1.8.5.3


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[PATCH v2 7/8] tegra: set AHB clock rate early

[Lucas Stach]

Avoids glitches in later starup phases.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra20-car.h | 4 ++++
 arch/arm/mach-tegra/tegra_avp_init.c           | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index a5441de..161e3d8 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -112,6 +112,10 @@
 #define CRC_SUPER_SDIV_DIVISOR_SHIFT	0
 #define CRC_SUPER_SDIV_DIVISOR_MASK	(0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT)
 
+#define CRC_CLK_SYSTEM_RATE		0x030
+#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT	4
+#define CRC_CLK_SYSTEM_RATE_APB_SHIFT	0
+
 #define CRC_CLK_CPU_CMPLX		0x04c
 #define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP	(1 << 11)
 #define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP	(1 << 10)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 9f8ccf3..4dd1330 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -149,6 +149,9 @@ static void start_cpu0_clocks(void)
 	       TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
 	writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
 
+	writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
+	       TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
+
 	/* deassert clock stop for cpu 0 */
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
 	reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
-- 
1.8.5.3


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[PATCH v2 8/8] tegra: add Tegra3 startup

[Lucas Stach]

Sets up MSELECT to let main CPUs talk to peripheral devices and starts
high performance A9 CPU cluster.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/include/mach/tegra30-car.h  | 31 ++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/tegra30-flow.h | 23 +++++++++++++++
 arch/arm/mach-tegra/tegra_avp_init.c            | 38 ++++++++++++++++++++++++-
 3 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-car.h
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra30-flow.h

diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
new file mode 100644
index 0000000..ce11060
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Register definitions */
+#define CRC_CLK_OUT_ENB_V		0x360
+#define CRC_CLK_OUT_ENB_V_MSELECT	(1 << 3)
+
+#define CRC_CLK_SOURCE_MSEL		0x3b4
+#define CRC_CLK_SOURCE_MSEL_SRC_SHIFT	30
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLP	0
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLC	1
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLM	2
+#define CRC_CLK_SOURCE_MSEL_SRC_CLKM	3
+
+#define CRC_RST_DEV_V_SET		0x430
+#define CRC_RST_DEV_V_MSELECT		(1 << 3)
+
+#define CRC_RST_DEV_V_CLR		0x434
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-flow.h b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
new file mode 100644
index 0000000..50a3030
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define FLOW_HALT_CPU_EVENTS		0x000
+#define FLOW_MODE_NONE			0
+#define FLOW_MODE_STOP			2
+
+#define FLOW_CLUSTER_CONTROL		0x02c
+#define FLOW_CLUSTER_CONTROL_ACTIVE_G	(0 << 0)
+#define FLOW_CLUSTER_CONTROL_ACTIVE_LP	(1 << 0)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 4dd1330..3314db4 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
  *
  * Partly based on code (C) Copyright 2010-2011
  * NVIDIA Corporation <www.nvidia.com>
@@ -23,6 +23,8 @@
 #include <mach/lowlevel.h>
 #include <mach/tegra20-car.h>
 #include <mach/tegra20-pmc.h>
+#include <mach/tegra30-car.h>
+#include <mach/tegra30-flow.h>
 
 /* instruct the PMIC to enable the CPU power rail */
 static void enable_maincomplex_powerrail(void)
@@ -84,6 +86,12 @@ static struct pll_config pllx_config_table[][4] = {
 		{1000, 12, 0, 12},	/* OSC 12.0 MHz */
 		{1000, 26, 0, 12},	/* OSC 26.0 MHz */
 	}, /* TEGRA 20 */
+	{
+		{862, 8,  0, 8},
+		{583, 8,  0, 4},
+		{700, 6,  0, 8},
+		{700, 13, 0, 8},
+	}, /* TEGRA 30 */
 };
 
 static void init_pllx(void)
@@ -152,6 +160,20 @@ static void start_cpu0_clocks(void)
 	writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
 	       TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
 
+	if (tegra_get_chiptype() >= TEGRA30) {
+		/* init MSELECT */
+		writel(CRC_RST_DEV_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET);
+		writel((CRC_CLK_SOURCE_MSEL_SRC_PLLP <<
+		       CRC_CLK_SOURCE_MSEL_SRC_SHIFT) | 2,
+		       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
+		writel(CRC_CLK_OUT_ENB_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
+		tegra_ll_delay_usec(3);
+		writel(CRC_RST_DEV_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
+	}
+
 	/* deassert clock stop for cpu 0 */
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
 	reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
@@ -185,10 +207,24 @@ static void maincomplex_powerup(void)
 		tegra_ll_delay_usec(1000);
 	}
 }
+
+static void tegra_cluster_switch_hp(void)
+{
+	u32 reg;
+
+	reg = readl(TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
+	reg &= ~FLOW_CLUSTER_CONTROL_ACTIVE_LP;
+	writel(reg, TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
+}
+
 void tegra_avp_reset_vector(uint32_t boarddata)
 {
 	int num_cores;
 
+	/* we want to bring up the high performance CPU complex */
+	if (tegra_get_chiptype() == TEGRA30)
+		tegra_cluster_switch_hp();
+
 	/* get the number of cores in the main CPU complex of the current SoC */
 	num_cores = tegra_get_num_cores();
 
-- 
1.8.5.3


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