NXP Layerscape

NXP Layerscape

[Barbier, Renaud]

I received a NXP  LS1046A-RDB

I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
I programmed the image in the alternative SPI bank as per NXP instructions:
=>	tftp $load_addr
=>	sf erase 0 +$filesize && sf write $load_addr 0 $filesize

Barebox does not boot.

I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
My understanding is that barebox is one image and shall be programmed at offset 0 of the SPI (0x40000000)


At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.

Any return on experience is welcome.

Cheers,
Renaud


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Re: NXP Layerscape

[Ahmad Fatoum]

Hello Barbier,

On 10.06.21 15:49, Barbier, Renaud wrote:
> I received a NXP  LS1046A-RDB

It doesn't reboot cleanly with a USB serial adapter attached!
Jfyi, gave me a scare first time, when I thought I broke something ^^.

> 
> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
> I programmed the image in the alternative SPI bank as per NXP instructions:
> =>	tftp $load_addr
> =>	sf erase 0 +$filesize && sf write $load_addr 0 $filesize
> 
> Barebox does not boot.
> 
> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
> My understanding is that barebox is one image and shall be programmed at offset 0 of the SPI (0x40000000)

Can't comment on that. Sascha did the integration.

> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
> 
> Any return on experience is welcome.

Can comment on that: Last time I did this, I wrote some documentation:
https://www.barebox.org/doc/latest/boards/layerscape.html

There I flashed barebox from another barebox booted from SD-Card.
I'd assume that should still work. I can't recall how the CPLD
needed to be tickled, but it would be helpful to know whether doing
it like described in the documentation doesn't work for you.

Cheers,
Ahmad

> 
> Cheers,
> Renaud
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: NXP Layerscape

[Ahmad Fatoum]

On 10.06.21 18:23, Barbier, Renaud wrote:
> Could the barebox image be started from memory with a "go" command?
> What would be the entry point?

Here's the barebox code that implements booting other barebox images:
https://git.pengutronix.de/cgit/barebox/tree/arch/arm/mach-layerscape/pblimage.c

Apparently entry point is at offset 128K. Keep in mind that
U-Boot go (at least on ARM32) does not do cache maintenance or turn
off the MMU, so funny effects may be expected.

Cheers,
Ahamd

> 
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de> 
> Sent: 10 June 2021 17:14
> To: Barbier, Renaud <renaud.barbier@abaco.com>
> Subject: Re: NXP Layerscape
> 
> 
> 
> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
> 
> Hi Renaud,
> 
> (please keep mailing list CC'd)
> 
> On 10.06.21 16:53, Barbier, Renaud wrote:
>>  I am not using a USB serial adapter. Currently I have a RJ-45 to RS232 to my laptop.
>>
>> Should not BOOTLOCPTR be set I the PBI. I see 0x40100000 for U-boot and 0x10000000 for barebox. Unless it does not apply for PPA boot flow.
> 
> I don't know about the specifics of the first stage boot on the Layerscape, I just wanted to point you at the docs and ask if the steps I had documented there work for you or not.
> 
> Cheers,
> Ahmad
> 
>>
>> -----Original Message-----
>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> Sent: 10 June 2021 15:09
>> To: Barbier, Renaud <renaud.barbier@abaco.com>; Barebox List 
>> <barebox@lists.infradead.org>
>> Subject: Re: NXP Layerscape
>>
>>
>>
>> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
>>
>> Hello Barbier,
>>
>> On 10.06.21 15:49, Barbier, Renaud wrote:
>>> I received a NXP  LS1046A-RDB
>>
>> It doesn't reboot cleanly with a USB serial adapter attached!
>> Jfyi, gave me a scare first time, when I thought I broke something ^^.
>>
>>>
>>> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
>>> I programmed the image in the alternative SPI bank as per NXP instructions:
>>> =>    tftp $load_addr
>>> =>    sf erase 0 +$filesize && sf write $load_addr 0 $filesize
>>>
>>> Barebox does not boot.
>>>
>>> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
>>> My understanding is that barebox is one image and shall be programmed 
>>> at offset 0 of the SPI (0x40000000)
>>
>> Can't comment on that. Sascha did the integration.
>>
>>> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
>>>
>>> Any return on experience is welcome.
>>
>> Can comment on that: Last time I did this, I wrote some documentation:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
>> barebox.org%2Fdoc%2Flatest%2Fboards%2Flayerscape.html&amp;data=04%7C01
>> %7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f
>> 27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7
>> CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV
>> CI6Mn0%3D%7C1000&amp;sdata=OUk8SFTmrlH0U%2F8aiXZonQHxLplyEjlMtc7Y5JHx%
>> 2BUk%3D&amp;reserved=0
>>
>> There I flashed barebox from another barebox booted from SD-Card.
>> I'd assume that should still work. I can't recall how the CPLD needed to be tickled, but it would be helpful to know whether doing it like described in the documentation doesn't work for you.
>>
>> Cheers,
>> Ahmad
>>
>>>
>>> Cheers,
>>> Renaud
>>>
>>>
>>> _______________________________________________
>>> barebox mailing list
>>> barebox@lists.infradead.org
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
>>> s 
>>> .infradead.org%2Fmailman%2Flistinfo%2Fbarebox&amp;data=04%7C01%7Crena
>>> u
>>> d.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f2745189
>>> 9 
>>> d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423989184%7CUnknown%7CTWFpbG
>>> Z
>>> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
>>> 3
>>> D%7C1000&amp;sdata=ORpVZlyPk2o7%2FyVYOkJPeAWNnq2%2FkxKauxep7gvDJ%2Bo%
>>> 3
>>> D&amp;reserved=0
>>>
>>
>> --
>> Pengutronix e.K.                           |                             |
>> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ru7cLRTSk3qfVNgAjscSXxOw4hj2j3dHbFSqsTL8sic%3D&amp;reserved=0  |
>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
>>
> 
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ru7cLRTSk3qfVNgAjscSXxOw4hj2j3dHbFSqsTL8sic%3D&amp;reserved=0  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
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Re: NXP Layerscape

[Ahmad Fatoum]

Hello Renaud,

On 10.06.21 18:44, Barbier, Renaud wrote:
> It partially starts:
> 
> => go 0xa0020000
> ## Starting application at 0xA0020000 ...
> 
> 
> barebox 2021.03.0-00096-gb6358ef010-dirty #14 Thu Jun 10 16:26:59 BST 2021
> 
> 
> Board: LS1046A RDB Board
> FIT: Opened FIT image: PPA Firmware
> FIT: No match found. Trying default.
> FIT: configuration 'config@1': PPA Secure firmware
> FIT: image 'firmware@1': 'PPA Firmware: Version LSDK-20170625'

Huh, apparently U-Boot is running at EL3 and loads barebox at EL3
as well. EL3 barebox tries to load PPA (secure monitor) and that fails.
This shouldn't happen with normal boots though, because:

 - if barebox runs at EL3, nothing besides BootROM has run before it,
   so it can load the PPA normally, which returns to barebox in EL2
 - if barebox runs at EL2, it will automatically skip installation
   of the PPA

Cheers,
Ahmad

> 
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de> 
> Sent: 10 June 2021 17:36
> To: Barbier, Renaud <renaud.barbier@abaco.com>
> Cc: barebox@lists.infradead.org
> Subject: Re: NXP Layerscape
> 
> 
> 
> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
> 
> On 10.06.21 18:23, Barbier, Renaud wrote:
>> Could the barebox image be started from memory with a "go" command?
>> What would be the entry point?
> 
> Here's the barebox code that implements booting other barebox images:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.pengutronix.de%2Fcgit%2Fbarebox%2Ftree%2Farch%2Farm%2Fmach-layerscape%2Fpblimage.c&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cffecae81cdee4a7b7eb608d92c2dce3d%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589397510510674%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=DLsQvcf5K4QVJtZ8UJSNE%2Fywd80%2FoT2ZUGS3T0NISps%3D&amp;reserved=0
> 
> Apparently entry point is at offset 128K. Keep in mind that U-Boot go (at least on ARM32) does not do cache maintenance or turn off the MMU, so funny effects may be expected.
> 
> Cheers,
> Ahamd
> 
>>
>> -----Original Message-----
>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> Sent: 10 June 2021 17:14
>> To: Barbier, Renaud <renaud.barbier@abaco.com>
>> Subject: Re: NXP Layerscape
>>
>>
>>
>> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
>>
>> Hi Renaud,
>>
>> (please keep mailing list CC'd)
>>
>> On 10.06.21 16:53, Barbier, Renaud wrote:
>>>  I am not using a USB serial adapter. Currently I have a RJ-45 to RS232 to my laptop.
>>>
>>> Should not BOOTLOCPTR be set I the PBI. I see 0x40100000 for U-boot and 0x10000000 for barebox. Unless it does not apply for PPA boot flow.
>>
>> I don't know about the specifics of the first stage boot on the Layerscape, I just wanted to point you at the docs and ask if the steps I had documented there work for you or not.
>>
>> Cheers,
>> Ahmad
>>
>>>
>>> -----Original Message-----
>>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>>> Sent: 10 June 2021 15:09
>>> To: Barbier, Renaud <renaud.barbier@abaco.com>; Barebox List 
>>> <barebox@lists.infradead.org>
>>> Subject: Re: NXP Layerscape
>>>
>>>
>>>
>>> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
>>>
>>> Hello Barbier,
>>>
>>> On 10.06.21 15:49, Barbier, Renaud wrote:
>>>> I received a NXP  LS1046A-RDB
>>>
>>> It doesn't reboot cleanly with a USB serial adapter attached!
>>> Jfyi, gave me a scare first time, when I thought I broke something ^^.
>>>
>>>>
>>>> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
>>>> I programmed the image in the alternative SPI bank as per NXP instructions:
>>>> =>    tftp $load_addr
>>>> =>    sf erase 0 +$filesize && sf write $load_addr 0 $filesize
>>>>
>>>> Barebox does not boot.
>>>>
>>>> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
>>>> My understanding is that barebox is one image and shall be 
>>>> programmed at offset 0 of the SPI (0x40000000)
>>>
>>> Can't comment on that. Sascha did the integration.
>>>
>>>> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
>>>>
>>>> Any return on experience is welcome.
>>>
>>> Can comment on that: Last time I did this, I wrote some documentation:
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
>>> barebox.org%2Fdoc%2Flatest%2Fboards%2Flayerscape.html&amp;data=04%7C0
>>> 1 
>>> %7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6
>>> f
>>> 27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%
>>> 7 
>>> CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
>>> V 
>>> CI6Mn0%3D%7C1000&amp;sdata=OUk8SFTmrlH0U%2F8aiXZonQHxLplyEjlMtc7Y5JHx
>>> %
>>> 2BUk%3D&amp;reserved=0
>>>
>>> There I flashed barebox from another barebox booted from SD-Card.
>>> I'd assume that should still work. I can't recall how the CPLD needed to be tickled, but it would be helpful to know whether doing it like described in the documentation doesn't work for you.
>>>
>>> Cheers,
>>> Ahmad
>>>
>>>>
>>>> Cheers,
>>>> Renaud
>>>>
>>>>
>>>> _______________________________________________
>>>> barebox mailing list
>>>> barebox@lists.infradead.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Flis
>>>> t
>>>> s
>>>> .infradead.org%2Fmailman%2Flistinfo%2Fbarebox&amp;data=04%7C01%7Cren
>>>> a
>>>> u
>>>> d.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f274518
>>>> 9
>>>> 9
>>>> d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423989184%7CUnknown%7CTWFpb
>>>> G
>>>> Z
>>>> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
>>>> %
>>>> 3
>>>> D%7C1000&amp;sdata=ORpVZlyPk2o7%2FyVYOkJPeAWNnq2%2FkxKauxep7gvDJ%2Bo
>>>> %
>>>> 3
>>>> D&amp;reserved=0
>>>>
>>>
>>> --
>>> Pengutronix e.K.                           |                             |
>>> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cffecae81cdee4a7b7eb608d92c2dce3d%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589397510510674%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=almI5k4Eunio%2FSXlzJvPEjdbojWK9u%2B7%2BQ9jMYAEJbA%3D&amp;reserved=0  |
>>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
>>>
>>
>> --
>> Pengutronix e.K.                           |                             |
>> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cffecae81cdee4a7b7eb608d92c2dce3d%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589397510510674%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=almI5k4Eunio%2FSXlzJvPEjdbojWK9u%2B7%2BQ9jMYAEJbA%3D&amp;reserved=0  |
>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
>>
> 
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cffecae81cdee4a7b7eb608d92c2dce3d%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589397510510674%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=almI5k4Eunio%2FSXlzJvPEjdbojWK9u%2B7%2BQ9jMYAEJbA%3D&amp;reserved=0  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

RE: NXP Layerscape

[Barbier, Renaud]

After reprograming the barebox image and change the DIP switch to boot from flash 1 instead of using the U-Boot  CPLD command, I got some garbage output on the serial. This is what you mention below.

Some hope.

-----Original Message-----
From: Ahmad Fatoum <a.fatoum@pengutronix.de> 
Sent: 10 June 2021 15:09
To: Barbier, Renaud <renaud.barbier@abaco.com>; Barebox List <barebox@lists.infradead.org>
Subject: Re: NXP Layerscape



[**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.

Hello Barbier,

On 10.06.21 15:49, Barbier, Renaud wrote:
> I received a NXP  LS1046A-RDB

It doesn't reboot cleanly with a USB serial adapter attached!
Jfyi, gave me a scare first time, when I thought I broke something ^^.

>
> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
> I programmed the image in the alternative SPI bank as per NXP instructions:
> =>    tftp $load_addr
> =>    sf erase 0 +$filesize && sf write $load_addr 0 $filesize
>
> Barebox does not boot.
>
> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
> My understanding is that barebox is one image and shall be programmed 
> at offset 0 of the SPI (0x40000000)

Can't comment on that. Sascha did the integration.

> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
>
> Any return on experience is welcome.

Can comment on that: Last time I did this, I wrote some documentation:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.barebox.org%2Fdoc%2Flatest%2Fboards%2Flayerscape.html&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423979193%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=SnXT0WYjQMJL%2FwK1LaOK1h7OMUcLiL37cojY2hzP89s%3D&amp;reserved=0

There I flashed barebox from another barebox booted from SD-Card.
I'd assume that should still work. I can't recall how the CPLD needed to be tickled, but it would be helpful to know whether doing it like described in the documentation doesn't work for you.

Cheers,
Ahmad

>
> Cheers,
> Renaud
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> .infradead.org%2Fmailman%2Flistinfo%2Fbarebox&amp;data=04%7C01%7Crenau
> d.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f27451899
> d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423989184%7CUnknown%7CTWFpbGZ
> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C1000&amp;sdata=ORpVZlyPk2o7%2FyVYOkJPeAWNnq2%2FkxKauxep7gvDJ%2Bo%3
> D&amp;reserved=0
>

--
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Re: NXP Layerscape

[Ahmad Fatoum]

Hello Barbier,

On 10.06.21 18:40, Barbier, Renaud wrote:
> I did find a barebox handler for the tqmls1046a but not the ls1046a.

Oh, I see.

> I guess they would work the same.
> It references /dev/qspiflash0.barebox
> 
> Then I just found arch/arm64/dts/fsl-ls1046a-rdb.dts. It does reference barebox in to esdhc not in qspi

This would explain why barebox_update -l doesn't list qspi, but you aren't getting
that far, apparently.

> I am programming barebox into the QSPI with barebox-ls1046ardb-qspi.image Could that be why it is not running, having  no QSPI node enabled?
> I guess I need to augment arch/arm64/dts/fsl-ls1046a-rdb.dts to have QSPI support.
> Not too familiar with the use of DTB in barebox at present.

That shouldn't matter. barebox header should contain the necessary bits for muxing/clocks.

Device-Tree only becomes relevant later, when barebox itself needs to read/write the flash. 

I'd postpone QSPI for now and check whether SD-Card boot works at all.

Cheers,
Ahmad

> 
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de> 
> Sent: 10 June 2021 17:14
> To: Barbier, Renaud <renaud.barbier@abaco.com>
> Subject: Re: NXP Layerscape
> 
> 
> 
> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
> 
> Hi Renaud,
> 
> (please keep mailing list CC'd)
> 
> On 10.06.21 16:53, Barbier, Renaud wrote:
>>  I am not using a USB serial adapter. Currently I have a RJ-45 to RS232 to my laptop.
>>
>> Should not BOOTLOCPTR be set I the PBI. I see 0x40100000 for U-boot and 0x10000000 for barebox. Unless it does not apply for PPA boot flow.
> 
> I don't know about the specifics of the first stage boot on the Layerscape, I just wanted to point you at the docs and ask if the steps I had documented there work for you or not.
> 
> Cheers,
> Ahmad
> 
>>
>> -----Original Message-----
>> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> Sent: 10 June 2021 15:09
>> To: Barbier, Renaud <renaud.barbier@abaco.com>; Barebox List 
>> <barebox@lists.infradead.org>
>> Subject: Re: NXP Layerscape
>>
>>
>>
>> [**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.
>>
>> Hello Barbier,
>>
>> On 10.06.21 15:49, Barbier, Renaud wrote:
>>> I received a NXP  LS1046A-RDB
>>
>> It doesn't reboot cleanly with a USB serial adapter attached!
>> Jfyi, gave me a scare first time, when I thought I broke something ^^.
>>
>>>
>>> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
>>> I programmed the image in the alternative SPI bank as per NXP instructions:
>>> =>    tftp $load_addr
>>> =>    sf erase 0 +$filesize && sf write $load_addr 0 $filesize
>>>
>>> Barebox does not boot.
>>>
>>> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
>>> My understanding is that barebox is one image and shall be programmed 
>>> at offset 0 of the SPI (0x40000000)
>>
>> Can't comment on that. Sascha did the integration.
>>
>>> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
>>>
>>> Any return on experience is welcome.
>>
>> Can comment on that: Last time I did this, I wrote some documentation:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
>> barebox.org%2Fdoc%2Flatest%2Fboards%2Flayerscape.html&amp;data=04%7C01
>> %7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f
>> 27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7
>> CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV
>> CI6Mn0%3D%7C1000&amp;sdata=OUk8SFTmrlH0U%2F8aiXZonQHxLplyEjlMtc7Y5JHx%
>> 2BUk%3D&amp;reserved=0
>>
>> There I flashed barebox from another barebox booted from SD-Card.
>> I'd assume that should still work. I can't recall how the CPLD needed to be tickled, but it would be helpful to know whether doing it like described in the documentation doesn't work for you.
>>
>> Cheers,
>> Ahmad
>>
>>>
>>> Cheers,
>>> Renaud
>>>
>>>
>>> _______________________________________________
>>> barebox mailing list
>>> barebox@lists.infradead.org
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
>>> s 
>>> .infradead.org%2Fmailman%2Flistinfo%2Fbarebox&amp;data=04%7C01%7Crena
>>> u
>>> d.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f2745189
>>> 9 
>>> d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423989184%7CUnknown%7CTWFpbG
>>> Z
>>> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
>>> 3
>>> D%7C1000&amp;sdata=ORpVZlyPk2o7%2FyVYOkJPeAWNnq2%2FkxKauxep7gvDJ%2Bo%
>>> 3
>>> D&amp;reserved=0
>>>
>>
>> --
>> Pengutronix e.K.                           |                             |
>> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ru7cLRTSk3qfVNgAjscSXxOw4hj2j3dHbFSqsTL8sic%3D&amp;reserved=0  |
>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
>>
> 
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7C0e00e06c3236419cae1108d92c2acefe%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589384654589155%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ru7cLRTSk3qfVNgAjscSXxOw4hj2j3dHbFSqsTL8sic%3D&amp;reserved=0  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
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RE: NXP Layerscape

[Barbier, Renaud]

I am a bit confused on how the QSPI image is built.
>From images/Makefile.layerscape
$(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
          $(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
         $(board)/ls1046ardb/ls1046ardb_pbi.cfg

It makes use of the file ls1046ardb/ls1046ardb_pbi.cfg not ls1046ardb/ls1046ardb_qspi_pbi.cfg. 
ls1046a_qspi_pbi.cfg contains an endian swap that I can see in the U-boot rcw+pbi data.

When I take an hex dump of the barebox-ls1046ardb-qspi.image, I see that the scratchpad register 2 (BOOTLOCPTR) in the PBI section points to 0x10000000 (as in the PBI file), not the PBL address start address.
How can this work?

Renaud





-----Original Message-----
From: Ahmad Fatoum <a.fatoum@pengutronix.de> 
Sent: 10 June 2021 15:09
To: Barbier, Renaud <renaud.barbier@abaco.com>; Barebox List <barebox@lists.infradead.org>
Subject: Re: NXP Layerscape



[**EXTERNAL SOURCE**]:Please verify the source before clicking link or opening attachment.

Hello Barbier,

On 10.06.21 15:49, Barbier, Renaud wrote:
> I received a NXP  LS1046A-RDB

It doesn't reboot cleanly with a USB serial adapter attached!
Jfyi, gave me a scare first time, when I thought I broke something ^^.

>
> I built barebox for the LS1046A and got the image barebox-ls1046ardb-qspi.image.
> I programmed the image in the alternative SPI bank as per NXP instructions:
> =>    tftp $load_addr
> =>    sf erase 0 +$filesize && sf write $load_addr 0 $filesize
>
> Barebox does not boot.
>
> I did notice that u-boot is at address 0x40100000 while the RCW is at 0x40000000.
> My understanding is that barebox is one image and shall be programmed 
> at offset 0 of the SPI (0x40000000)

Can't comment on that. Sascha did the integration.

> At present I cannot connect my I.C.E. due a pin stuck in my MIPI connector.
>
> Any return on experience is welcome.

Can comment on that: Last time I did this, I wrote some documentation:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.barebox.org%2Fdoc%2Flatest%2Fboards%2Flayerscape.html&amp;data=04%7C01%7Crenaud.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f27451899d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423979193%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=SnXT0WYjQMJL%2FwK1LaOK1h7OMUcLiL37cojY2hzP89s%3D&amp;reserved=0

There I flashed barebox from another barebox booted from SD-Card.
I'd assume that should still work. I can't recall how the CPLD needed to be tickled, but it would be helpful to know whether doing it like described in the documentation doesn't work for you.

Cheers,
Ahmad

>
> Cheers,
> Renaud
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> .infradead.org%2Fmailman%2Flistinfo%2Fbarebox&amp;data=04%7C01%7Crenau
> d.barbier%40abaco.com%7Cdf668f5e5f2d497d54cb08d92c194c3e%7Ce6f27451899
> d4d0db8fa88baafa551a7%7C0%7C0%7C637589309423989184%7CUnknown%7CTWFpbGZ
> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C1000&amp;sdata=ORpVZlyPk2o7%2FyVYOkJPeAWNnq2%2FkxKauxep7gvDJ%2Bo%3
> D&amp;reserved=0
>

--
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Re: NXP Layerscape

[Sascha Hauer]

On Mon, Jun 14, 2021 at 03:16:27PM +0000, Barbier, Renaud wrote:
> I am a bit confused on how the QSPI image is built.
> From images/Makefile.layerscape
> $(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
>           $(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
>          $(board)/ls1046ardb/ls1046ardb_pbi.cfg
> 
> It makes use of the file ls1046ardb/ls1046ardb_pbi.cfg not ls1046ardb/ls1046ardb_qspi_pbi.cfg. 
> ls1046a_qspi_pbi.cfg contains an endian swap that I can see in the U-boot rcw+pbi data.
> 
> When I take an hex dump of the barebox-ls1046ardb-qspi.image, I see that the scratchpad register 2 (BOOTLOCPTR) in the PBI section points to 0x10000000 (as in the PBI file), not the PBL address start address.
> How can this work?

Let's have a look at the differences between both files:

> --- arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg       2021-05-04 10:21:05.961665227 +0200
> +++ arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg  2021-05-04 10:21:05.961665227 +0200
> @@ -1,3 +1,5 @@
> +#QSPI clk
> +0957015c 40100000

Not sure about this one. It might be not necessary because the SPI clock
must have a sane value without it, in the end this data has just been
read from SPI flash.

>  #Configure Scratch register
>  09570600 00000000
>  09570604 10000000
> @@ -20,3 +22,5 @@
>  09570158 00001000
>  #flush PBI data
>  096100c0 000fffff
> +#Change endianness
> +09550000 000f400c

This is the weird one. The QSPI read data is memory mapped in some SRAM
where it is directly executed. Now the snippet above changes the
endianess of the read data, so that beginning after the line above the
rest of the data must be written to flash with a different endianess. In
barebox we do that differently. Instead of changing the endianess of the
controller we change the endianess of the data written to flash. This
type of image is generated with the -s option to the pblimage tool.
This means we don't need a special QSPI variant for the PBI file.
arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg could be removed,
it's there as a leftover from the files imported from U-Boot.

Sascha

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RE: NXP Layerscape

[Barbier, Renaud]

>  09570604 10000000

> This is the weird one. The QSPI read data is memory mapped in some SRAM where it is directly executed. 
So if  I understand you correctly both the PBI and barebox PBL got mapped to the SRAM (which I guess may be the OCRAM1 if i refer to the address above 0x10000000) and get executed sequentially.

Based on U-boot, RCW+PBI (at 0x40000000) which specifies 09570604 40100000 (address of U-boot), I would have thought that the address needed to be the exact start address of the barebox PBL in QSPI. Apparently not. 

So If I burn the image barebox-ls1046ardb-qspi.image at address 0x40000000 (start of QSPI flash) by using U-boot, it shall boot on power on.

Thanks.

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