[PATCH 0/4] Orion GBE fixes and Marvell PHY driver

[PATCH 0/4] Orion GBE fixes and Marvell PHY driver

[Sebastian Hesselbarth]

This patch set comprises some fixes and improvements related with ethernet
support on Marvell Orion SoC based boards.

Patch 1 adds a check for ePAPR standard "phy-connection-type" property to
of_get_phy_mode.

Patch 2 resolves a device name conflict on orion-gbe port names when using
more than one controller instance.

Patch 3 extends ethernet serial port setup to also check for delayed RGMII
interface modes.

Patch 4 finally adds a driver for Marvell PHYs with 88E1121R as a first
PHY driver.

The patches have been tested on Globalscale Guruplug. For ethernet, the
board needs a DT fix that has been picked up for Linux v3.16-rc yesterday
and should be available in barebox soon. For the second ethernet port,
barebox is still missing pinctrl for Kirkwood, but that is next on my
"polish private branches for submission"-TODO list.

Sebastian Hesselbarth (4):
  of: net: respect phy-connection-type property
  net: orion: generate unique port device names
  net: orion-gbe: extend RGMII detection to delayed modes
  net: phy: add support for Marvell PHY drivers

 drivers/net/orion-gbe.c   |   8 +-
 drivers/net/phy/Kconfig   |   5 ++
 drivers/net/phy/Makefile  |   1 +
 drivers/net/phy/marvell.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/of/of_net.c       |   2 +
 5 files changed, 213 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/phy/marvell.c

---
Cc: barebox@lists.infradead.org
-- 
2.0.0


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[PATCH 1/4] of: net: respect phy-connection-type property

[Sebastian Hesselbarth]

ePAPR defines phy-connection-type as standard property for PHY interface
between Ethernet device and PHY device. Add corresponding property check
to of_get_phy_mode.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
 drivers/of/of_net.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index 2bf05e2ba21d..0320c1d4f50e 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -44,6 +44,8 @@ int of_get_phy_mode(struct device_node *np)
 
 	err = of_property_read_string(np, "phy-mode", &pm);
 	if (err < 0)
+		err = of_property_read_string(np, "phy-connection-type", &pm);
+	if (err < 0)
 		return err;
 
 	for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
-- 
2.0.0


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[PATCH 2/4] net: orion: generate unique port device names

[Sebastian Hesselbarth]

Marvell Orion ethernet IP originally is multi-port capable, but SoCs
using the IP usually have multiple single-port controllers built in.
Currently, orion-gbe driver registers each port device with a constant
name, which causes a name conflict with multiple controller instances.

This patch uniquifies port device name generation by prepending
controller's base register address to resolve the name conflict.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
 drivers/net/orion-gbe.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/orion-gbe.c b/drivers/net/orion-gbe.c
index 9315127ac7ff..23c8346ec58f 100644
--- a/drivers/net/orion-gbe.c
+++ b/drivers/net/orion-gbe.c
@@ -399,6 +399,7 @@ static int port_open(struct eth_device *edev)
 
 static int port_probe(struct device_d *parent, struct port_priv *port)
 {
+	struct orion_gbe *gbe = parent->priv;
 	struct device_d *dev = &port->dev;
 	u32 reg;
 	int ret;
@@ -450,7 +451,7 @@ static int port_probe(struct device_d *parent, struct port_priv *port)
 		reg |= RGMII_ENABLE;
 	writel(reg, port->regs + PORT_SC1);
 
-	sprintf(dev->name, "orion-gbe-port");
+	snprintf(dev->name, MAX_DRIVER_NAME, "%08x.ethernet-port", (u32)gbe->regs);
 	dev->id = port->portno;
 	dev->parent = parent;
 	dev->device_node = port->np;
-- 
2.0.0


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[PATCH 3/4] net: orion-gbe: extend RGMII detection to delayed modes

[Sebastian Hesselbarth]

RGMII PHY modes include delayed interface modes RGMII_ID, RGMII_TXID,
and RGMII_RXID. Also check for those modes when setup RGMII mode in
port serial ctrl register.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
 drivers/net/orion-gbe.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/orion-gbe.c b/drivers/net/orion-gbe.c
index 23c8346ec58f..991c8a80de31 100644
--- a/drivers/net/orion-gbe.c
+++ b/drivers/net/orion-gbe.c
@@ -447,7 +447,10 @@ static int port_probe(struct device_d *parent, struct port_priv *port)
 
 	reg = SC1_RESERVED;
 	reg |= DEFAULT_COL_LIMIT | COL_ON_BACKPRESS | INBAND_ANEG_BYPASS;
-	if (port->intf == PHY_INTERFACE_MODE_RGMII)
+	if (port->intf == PHY_INTERFACE_MODE_RGMII ||
+	    port->intf == PHY_INTERFACE_MODE_RGMII_ID ||
+	    port->intf == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    port->intf == PHY_INTERFACE_MODE_RGMII_TXID)
 		reg |= RGMII_ENABLE;
 	writel(reg, port->regs + PORT_SC1);
 
-- 
2.0.0


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[PATCH 4/4] net: phy: add support for Marvell PHY drivers

[Sebastian Hesselbarth]

This adds initial support for Marvell PHY specific drivers. As a first
PHY, a driver for MV88E1121R is ported over from Linux.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
 drivers/net/phy/Kconfig   |   5 ++
 drivers/net/phy/Makefile  |   1 +
 drivers/net/phy/marvell.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 205 insertions(+)
 create mode 100644 drivers/net/phy/marvell.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 02e1e83c0b65..d0a02c1e402d 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -18,6 +18,11 @@ config LXT_PHY
 	---help---
 	  Currently supports the lxt971 PHY.
 
+config MARVELL_PHY
+	tristate "Drivers for Marvell PHYs"
+	---help---
+	  Add support for various Marvell PHYs (e.g. 88E1121R).
+
 config MICREL_PHY
 	bool "Driver for Micrel PHYs"
 	---help---
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7f8277f1d52a..94b9be83ea7a 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -1,6 +1,7 @@
 obj-y += phy.o mdio_bus.o
 obj-$(CONFIG_AT803X_PHY)	+= at803x.o
 obj-$(CONFIG_LXT_PHY)		+= lxt.o
+obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
 obj-$(CONFIG_MICREL_PHY)	+= micrel.o
 obj-$(CONFIG_NATIONAL_PHY)	+= national.o
 obj-$(CONFIG_SMSC_PHY)		+= smsc.o
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
new file mode 100644
index 000000000000..34f852e06550
--- /dev/null
+++ b/drivers/net/phy/marvell.c
@@ -0,0 +1,199 @@
+/*
+ * drivers/net/phy/marvell.c
+ *
+ * Driver for Marvell PHYs based on Linux driver
+ */
+
+#include <common.h>
+#include <init.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/smscphy.h>
+
+/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E1101		0x01410c60
+#define MARVELL_PHY_ID_88E1112		0x01410c90
+#define MARVELL_PHY_ID_88E1111		0x01410cc0
+#define MARVELL_PHY_ID_88E1118		0x01410e10
+#define MARVELL_PHY_ID_88E1121R		0x01410cb0
+#define MARVELL_PHY_ID_88E1145		0x01410cd0
+#define MARVELL_PHY_ID_88E1149R		0x01410e50
+#define MARVELL_PHY_ID_88E1240		0x01410e30
+#define MARVELL_PHY_ID_88E1318S		0x01410e90
+#define MARVELL_PHY_ID_88E1116R		0x01410e40
+#define MARVELL_PHY_ID_88E1510		0x01410dd0
+
+/* Mask used for ID comparisons */
+#define MARVELL_PHY_ID_MASK		0xfffffff0
+
+/* Marvell Register Page register */
+#define MII_MARVELL_PHY_PAGE		22
+#define MII_MARVELL_PHY_DEFAULT_PAGE	0
+
+#define MII_M1011_PHY_SCR		0x10
+#define MII_M1011_PHY_SCR_AUTO_CROSS	0x0060
+
+#define MII_M1011_PHY_STATUS		0x11
+#define MII_M1011_PHY_STATUS_1000	BIT(15)
+#define MII_M1011_PHY_STATUS_100	BIT(14)
+#define MII_M1011_PHY_STATUS_SPD_MASK	\
+	(MII_M1011_PHY_STATUS_1000 | MII_M1011_PHY_STATUS_100)
+#define MII_M1011_PHY_STATUS_FULLDUPLEX	BIT(13)
+#define MII_M1011_PHY_STATUS_RESOLVED	BIT(11)
+#define MII_M1011_PHY_STATUS_LINK	BIT(10)
+
+#define MII_88E1121_PHY_MSCR_PAGE	2
+#define MII_88E1121_PHY_MSCR		0x15
+#define MII_88E1121_PHY_MSCR_TX_DELAY	BIT(4)
+#define MII_88E1121_PHY_MSCR_RX_DELAY	BIT(5)
+#define MII_88E1121_PHY_MSCR_DELAY_MASK	\
+	(MII_88E1121_PHY_MSCR_RX_DELAY | MII_88E1121_PHY_MSCR_TX_DELAY)
+
+/*
+ * marvell_read_status
+ *
+ * Generic status code does not detect Fiber correctly!
+ * Description:
+ *   Check the link, then figure out the current state
+ *   by comparing what we advertise with what the link partner
+ *   advertises.  Start by checking the gigabit possibilities,
+ *   then move on to 10/100.
+ */
+static int marvell_read_status(struct phy_device *phydev)
+{
+	int adv;
+	int err;
+	int lpa;
+	int status = 0;
+
+	/* Update the link, but return if there
+	 * was an error */
+	err = genphy_update_link(phydev);
+	if (err)
+		return err;
+
+	if (AUTONEG_ENABLE == phydev->autoneg) {
+		status = phy_read(phydev, MII_M1011_PHY_STATUS);
+		if (status < 0)
+			return status;
+
+		lpa = phy_read(phydev, MII_LPA);
+		if (lpa < 0)
+			return lpa;
+
+		adv = phy_read(phydev, MII_ADVERTISE);
+		if (adv < 0)
+			return adv;
+
+		lpa &= adv;
+
+		if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
+			phydev->duplex = DUPLEX_FULL;
+		else
+			phydev->duplex = DUPLEX_HALF;
+
+		status = status & MII_M1011_PHY_STATUS_SPD_MASK;
+		phydev->pause = phydev->asym_pause = 0;
+
+		switch (status) {
+		case MII_M1011_PHY_STATUS_1000:
+			phydev->speed = SPEED_1000;
+			break;
+
+		case MII_M1011_PHY_STATUS_100:
+			phydev->speed = SPEED_100;
+			break;
+
+		default:
+			phydev->speed = SPEED_10;
+			break;
+		}
+
+		if (phydev->duplex == DUPLEX_FULL) {
+			phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
+			phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
+		}
+	} else {
+		int bmcr = phy_read(phydev, MII_BMCR);
+
+		if (bmcr < 0)
+			return bmcr;
+
+		if (bmcr & BMCR_FULLDPLX)
+			phydev->duplex = DUPLEX_FULL;
+		else
+			phydev->duplex = DUPLEX_HALF;
+
+		if (bmcr & BMCR_SPEED1000)
+			phydev->speed = SPEED_1000;
+		else if (bmcr & BMCR_SPEED100)
+			phydev->speed = SPEED_100;
+		else
+			phydev->speed = SPEED_10;
+
+		phydev->pause = phydev->asym_pause = 0;
+	}
+
+	return 0;
+}
+
+static int m88e1121_config_init(struct phy_device *phydev)
+{
+	u16 reg;
+	int ret;
+
+	ret = phy_write(phydev, MII_MARVELL_PHY_PAGE,
+			MII_88E1121_PHY_MSCR_PAGE);
+	if (ret < 0)
+		return ret;
+
+	/* Setup RGMII TX/RX delay */
+	reg = phy_read(phydev, MII_88E1121_PHY_MSCR) &
+		~MII_88E1121_PHY_MSCR_DELAY_MASK;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+		reg |= MII_88E1121_PHY_MSCR_RX_DELAY;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+		reg |= MII_88E1121_PHY_MSCR_TX_DELAY;
+	ret = phy_write(phydev, MII_88E1121_PHY_MSCR, reg);
+	if (ret < 0)
+		return ret;
+
+	phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_PHY_DEFAULT_PAGE);
+	if (ret < 0)
+		return ret;
+
+	/* Enable auto-crossover */
+	ret = phy_write(phydev, MII_M1011_PHY_SCR,
+			MII_M1011_PHY_SCR_AUTO_CROSS);
+	if (ret < 0)
+		return ret;
+
+	/* Reset PHY */
+	ret = phy_write(phydev, MII_BMCR,
+			phy_read(phydev, MII_BMCR) | BMCR_RESET);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static struct phy_driver marvell_phys[] = {
+{
+	.phy_id		= MARVELL_PHY_ID_88E1121R,
+	.phy_id_mask	= MARVELL_PHY_ID_MASK,
+	.drv.name	= "Marvell 88E1121R",
+	.features	= PHY_GBIT_FEATURES,
+	.config_init	= m88e1121_config_init,
+	.config_aneg	= genphy_config_aneg,
+	.read_status	= marvell_read_status,
+},
+};
+
+static int __init marvell_phy_init(void)
+{
+	return phy_drivers_register(marvell_phys, ARRAY_SIZE(marvell_phys));
+}
+fs_initcall(marvell_phy_init);
-- 
2.0.0


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Re: [PATCH 0/4] Orion GBE fixes and Marvell PHY driver

[Sascha Hauer]

On Tue, Jun 24, 2014 at 12:18:07PM +0200, Sebastian Hesselbarth wrote:
> This patch set comprises some fixes and improvements related with ethernet
> support on Marvell Orion SoC based boards.
> 
> Patch 1 adds a check for ePAPR standard "phy-connection-type" property to
> of_get_phy_mode.
> 
> Patch 2 resolves a device name conflict on orion-gbe port names when using
> more than one controller instance.
> 
> Patch 3 extends ethernet serial port setup to also check for delayed RGMII
> interface modes.
> 
> Patch 4 finally adds a driver for Marvell PHYs with 88E1121R as a first
> PHY driver.
> 
> The patches have been tested on Globalscale Guruplug. For ethernet, the
> board needs a DT fix that has been picked up for Linux v3.16-rc yesterday
> and should be available in barebox soon. For the second ethernet port,
> barebox is still missing pinctrl for Kirkwood, but that is next on my
> "polish private branches for submission"-TODO list.
> 
> Sebastian Hesselbarth (4):
>   of: net: respect phy-connection-type property
>   net: orion: generate unique port device names
>   net: orion-gbe: extend RGMII detection to delayed modes
>   net: phy: add support for Marvell PHY drivers

Applied, thanks

Sascha

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