* [PATCH 1/3] drivers: of: import PCI bus specific translator
2014-06-24 11:45 [PATCH 0/3] MVEBU SoC ID and revision detection Sebastian Hesselbarth
@ 2014-06-24 11:45 ` Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 2/3] ARM: mvebu: select PCI specific DT bus translator Sebastian Hesselbarth
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Sebastian Hesselbarth @ 2014-06-24 11:45 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
DT PCI address translation needs a special handling. This imports
the corresponding translator into of/address.c but makes it selectable
through Kconfig. Compared to the Linux version, we don't check for
struct device_node's type which does not exist on Barebox but directly
for device_type property set to "pci".
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
drivers/of/Kconfig | 3 ++
drivers/of/address.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index c4525cbffcc4..45f77a759fd4 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -15,6 +15,9 @@ config OFDEVICE
select DTC
bool "Enable probing of devices from the devicetree"
+config OF_ADDRESS_PCI
+ bool
+
config OF_NET
depends on NET
def_bool y
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 4cacdb1cf78e..b3cbb154539a 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -108,11 +108,94 @@ static unsigned int of_bus_default_get_flags(const __be32 *addr)
return IORESOURCE_MEM;
}
+#ifdef CONFIG_OF_ADDRESS_PCI
+/*
+ * PCI bus specific translator
+ */
+
+static int of_bus_pci_match(struct device_node *np)
+{
+ return !of_property_match_string(np, "device_type", "pci");
+}
+
+static void of_bus_pci_count_cells(struct device_node *np,
+ int *addrc, int *sizec)
+{
+ if (addrc)
+ *addrc = 3;
+ if (sizec)
+ *sizec = 2;
+}
+
+static unsigned int of_bus_pci_get_flags(const __be32 *addr)
+{
+ unsigned int flags = 0;
+ u32 w = be32_to_cpup(addr);
+
+ switch ((w >> 24) & 0x03) {
+ case 0x01:
+ flags |= IORESOURCE_IO;
+ break;
+ case 0x02: /* 32 bits */
+ case 0x03: /* 64 bits */
+ flags |= IORESOURCE_MEM;
+ break;
+ }
+ if (w & 0x40000000)
+ flags |= IORESOURCE_PREFETCH;
+ return flags;
+}
+
+static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
+ int pna)
+{
+ u64 cp, s, da;
+ unsigned int af, rf;
+
+ af = of_bus_pci_get_flags(addr);
+ rf = of_bus_pci_get_flags(range);
+
+ /* Check address type match */
+ if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO))
+ return OF_BAD_ADDR;
+
+ /* Read address values, skipping high cell */
+ cp = of_read_number(range + 1, na - 1);
+ s = of_read_number(range + na + pna, ns);
+ da = of_read_number(addr + 1, na - 1);
+
+ pr_debug("OF: PCI map, cp=%llx, s=%llx, da=%llx\n",
+ (unsigned long long)cp, (unsigned long long)s,
+ (unsigned long long)da);
+
+ if (da < cp || da >= (cp + s))
+ return OF_BAD_ADDR;
+ return da - cp;
+}
+
+static int of_bus_pci_translate(__be32 *addr, u64 offset, int na)
+{
+ return of_bus_default_translate(addr + 1, offset, na - 1);
+}
+#endif /* CONFIG_OF_ADDRESS_PCI */
+
/*
* Array of bus specific translators
*/
static struct of_bus of_busses[] = {
+#ifdef CONFIG_OF_ADDRESS_PCI
+ /* PCI */
+ {
+ .name = "pci",
+ .addresses = "assigned-addresses",
+ .match = of_bus_pci_match,
+ .count_cells = of_bus_pci_count_cells,
+ .map = of_bus_pci_map,
+ .translate = of_bus_pci_translate,
+ .get_flags = of_bus_pci_get_flags,
+ },
+#endif
/* Default */
{
.name = "default",
--
2.0.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/3] ARM: mvebu: select PCI specific DT bus translator
2014-06-24 11:45 [PATCH 0/3] MVEBU SoC ID and revision detection Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 1/3] drivers: of: import PCI bus specific translator Sebastian Hesselbarth
@ 2014-06-24 11:45 ` Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 3/3] ARM: mvebu: determine SoC id and revision from PCIe nodes Sebastian Hesselbarth
2014-06-25 6:45 ` [PATCH 0/3] MVEBU SoC ID and revision detection Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sebastian Hesselbarth @ 2014-06-24 11:45 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
Marvell MVEBU DT files contain some nodes mapped to PCI address space,
add the translator Kconfig to be able to iomap those node's addresses.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3b8a2a2207e4..8465d4a7f739 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -95,6 +95,7 @@ config ARCH_MVEBU
select HAVE_PBL_MULTI_IMAGES
select MVEBU_MBUS
select OFTREE
+ select OF_ADDRESS_PCI
config ARCH_MXS
bool "Freescale i.MX23/28 (mxs) based"
--
2.0.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] ARM: mvebu: determine SoC id and revision from PCIe nodes
2014-06-24 11:45 [PATCH 0/3] MVEBU SoC ID and revision detection Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 1/3] drivers: of: import PCI bus specific translator Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 2/3] ARM: mvebu: select PCI specific DT bus translator Sebastian Hesselbarth
@ 2014-06-24 11:45 ` Sebastian Hesselbarth
2014-06-25 6:45 ` [PATCH 0/3] MVEBU SoC ID and revision detection Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sebastian Hesselbarth @ 2014-06-24 11:45 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
Marvell MVEBU SoC id and revision can be read out from any PCIe port
registers. This adds corresponding code to read out id and revision
and provides a helper function for drivers to use it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: barebox@lists.infradead.org
---
arch/arm/mach-mvebu/common.c | 64 +++++++++++++++++++++++++++
arch/arm/mach-mvebu/include/mach/socid.h | 76 ++++++++++++++++++++++++++++++++
2 files changed, 140 insertions(+)
create mode 100644 arch/arm/mach-mvebu/include/mach/socid.h
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 4a78a0f37ec5..b054bf5aff48 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -15,3 +15,67 @@
*
*/
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <of.h>
+#include <of_address.h>
+#include <linux/clk.h>
+
+/*
+ * Marvell MVEBU SoC id and revision can be read from any PCIe
+ * controller port.
+ */
+u16 soc_devid;
+EXPORT_SYMBOL(soc_devid);
+u16 soc_revid;
+EXPORT_SYMBOL(soc_revid);
+
+static const struct of_device_id mvebu_pcie_of_ids[] = {
+ { .compatible = "marvell,armada-xp-pcie", },
+ { .compatible = "marvell,armada-370-pcie", },
+ { .compatible = "marvell,dove-pcie" },
+ { .compatible = "marvell,kirkwood-pcie" },
+ { },
+};
+
+#define PCIE_VEN_DEV_ID 0x000
+#define PCIE_REV_ID 0x008
+#define REV_ID_MASK 0xff
+
+static int mvebu_soc_id_init(void)
+{
+ struct device_node *np, *cnp;
+ struct clk *clk;
+ void __iomem *base;
+
+ np = of_find_matching_node(NULL, mvebu_pcie_of_ids);
+ if (!np)
+ return -ENODEV;
+
+ for_each_child_of_node(np, cnp) {
+ base = of_iomap(cnp, 0);
+ if (!base)
+ continue;
+
+ clk = of_clk_get(cnp, 0);
+ if (IS_ERR(clk))
+ continue;
+
+ clk_enable(clk);
+ soc_devid = readl(base + PCIE_VEN_DEV_ID) >> 16;
+ soc_revid = readl(base + PCIE_REV_ID) & REV_ID_MASK;
+ clk_disable(clk);
+ break;
+ }
+
+ if (!soc_devid) {
+ pr_err("Unable to read SoC id from PCIe ports\n");
+ return -EINVAL;
+ }
+
+ pr_info("SoC: Marvell %04x rev %d\n", soc_devid, soc_revid);
+
+ return 0;
+}
+postcore_initcall(mvebu_soc_id_init);
diff --git a/arch/arm/mach-mvebu/include/mach/socid.h b/arch/arm/mach-mvebu/include/mach/socid.h
new file mode 100644
index 000000000000..36d681a9dcc1
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/socid.h
@@ -0,0 +1,76 @@
+/*
+ * Marvell MVEBU SoC Ids
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_MVEBU_SOCID_H
+#define __MACH_MVEBU_SOCID_H
+
+extern u16 soc_devid;
+extern u16 soc_revid;
+
+static inline u16 mvebu_get_soc_devid(void)
+{
+ return soc_devid;
+}
+
+static inline u16 mvebu_get_soc_revid(void)
+{
+ return soc_revid;
+}
+
+/* Orion */
+#define DEVID_F5180 0x5180
+#define REVID_F5180N_B1 0x3
+#define DEVID_F5181 0x5181
+#define REVID_F5181_B1 0x3
+#define REVID_F5181L 0x8
+#define DEVID_F5182 0x5182
+#define REVID_F5182_A1 0x1
+#define DEVID_F6183 0x6183
+/* Kirkwood */
+#define DEVID_F6180 0x6180
+#define DEVID_F6190 0x6190
+#define DEVID_F6192 0x6192
+#define DEVID_F6280 0x6280
+#define DEVID_F6281 0x6281
+#define DEVID_F6282 0x1155
+/* Kirkwood Duo */
+#define DEVID_F6321 0x6321
+#define DEVID_F6322 0x6322
+#define DEVID_F6323 0x6323
+/* Avanta */
+#define DEVID_F6510 0x6510
+#define DEVID_F6530 0x6530
+#define DEVID_F6550 0x6550
+#define DEVID_F6560 0x6560
+/* Dove */
+#define DEVID_AP510 0x0510
+#define DEVID_F6781 0x6781
+/* Discovery Duo */
+#define DEVID_MV76100 0x7610
+#define DEVID_MV78100 0x7810
+#define DEVID_MV78200 0x7820
+/* Armada 370 */
+#define DEVID_F6707 0x6707
+#define DEVID_F6710 0x6710
+#define DEVID_F6711 0x6711
+/* Armada XP */
+#define DEVID_MV78130 0x7813
+#define DEVID_MV78160 0x7816
+#define DEVID_MV78230 0x7823
+#define DEVID_MV78260 0x7826
+#define DEVID_MV78460 0x7846
+#define DEVID_MV78880 0x7888
+
+#endif /* __MACH_MVEBU_SOCID_H */
--
2.0.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] MVEBU SoC ID and revision detection
2014-06-24 11:45 [PATCH 0/3] MVEBU SoC ID and revision detection Sebastian Hesselbarth
` (2 preceding siblings ...)
2014-06-24 11:45 ` [PATCH 3/3] ARM: mvebu: determine SoC id and revision from PCIe nodes Sebastian Hesselbarth
@ 2014-06-25 6:45 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2014-06-25 6:45 UTC (permalink / raw)
To: Sebastian Hesselbarth; +Cc: barebox
On Tue, Jun 24, 2014 at 01:45:33PM +0200, Sebastian Hesselbarth wrote:
> This patch set adds support for reading SoC ID and revision from
> PCIe controllers found on Marvell MVEBU SoCs.
>
> Patch 1 adds PCI bus specific OF address translation required for
> reg property parsing of PCIe controller nodes.
>
> Patch 2 selects above PCI OF address translation for MVEBU SoCs.
>
> Patch 3 adds common code to find and parse PCIe controller nodes
> from MVEBU SoC DT and read out SoC ID and revision registers.
>
> The patches are based on barebox next with latest MVEBU patches
> for cleanup and PBL images applied. They have been tested on
> Marvell Kirkwood, Dove, and Armada 370.
>
> Sebastian Hesselbarth (3):
> drivers: of: import PCI bus specific translator
> ARM: mvebu: select PCI specific DT bus translator
> ARM: mvebu: determine SoC id and revision from PCIe nodes
Applied, thanks
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 5+ messages in thread