From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-lb0-x229.google.com ([2a00:1450:4010:c04::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WzvkV-0006xy-TG for barebox@lists.infradead.org; Wed, 25 Jun 2014 22:33:06 +0000 Received: by mail-lb0-f169.google.com with SMTP id l4so2362085lbv.0 for ; Wed, 25 Jun 2014 15:32:41 -0700 (PDT) From: Antony Pavlov Date: Thu, 26 Jun 2014 02:32:14 +0400 Message-Id: <1403735538-25437-2-git-send-email-antonynpavlov@gmail.com> In-Reply-To: <1403735538-25437-1-git-send-email-antonynpavlov@gmail.com> References: <1403735538-25437-1-git-send-email-antonynpavlov@gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [RFC v3 1/5] PCI: initial commit To: barebox@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20Leger?= used shorten version of linux-2.6.39 pci_ids.h Signed-off-by: Antony Pavlov Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- drivers/Makefile | 1 + drivers/pci/Kconfig | 12 ++ drivers/pci/Makefile | 8 ++ drivers/pci/bus.c | 110 ++++++++++++++++ drivers/pci/pci.c | 282 ++++++++++++++++++++++++++++++++++++++++ include/linux/mod_devicetable.h | 20 +++ include/linux/pci.h | 241 ++++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 136 +++++++++++++++++++ include/linux/pci_regs.h | 118 +++++++++++++++++ 9 files changed, 928 insertions(+) create mode 100644 drivers/pci/Kconfig create mode 100644 drivers/pci/Makefile create mode 100644 drivers/pci/bus.c create mode 100644 drivers/pci/pci.c create mode 100644 include/linux/mod_devicetable.h create mode 100644 include/linux/pci.h create mode 100644 include/linux/pci_ids.h create mode 100644 include/linux/pci_regs.h diff --git a/drivers/Makefile b/drivers/Makefile index ef3604f..1990e86 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -26,3 +26,4 @@ obj-y += pinctrl/ obj-y += bus/ obj-$(CONFIG_REGULATOR) += regulator/ obj-$(CONFIG_RESET_CONTROLLER) += reset/ +obj-$(CONFIG_PCI) += pci/ diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig new file mode 100644 index 0000000..88b8dfb --- /dev/null +++ b/drivers/pci/Kconfig @@ -0,0 +1,12 @@ +# +# PCI configuration +# +config PCI_DEBUG + bool "PCI Debugging" + depends on PCI + help + Say Y here if you want the PCI core to produce a bunch of debug + messages to the system log. Select this if you are having a + problem with PCI support and want to see more of what is going on. + + When in doubt, say N. diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile new file mode 100644 index 0000000..c7d43c3 --- /dev/null +++ b/drivers/pci/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the PCI bus specific drivers. +# +obj-y += pci.o bus.o + +ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG + +CPPFLAGS += $(ccflags-y) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c new file mode 100644 index 0000000..8215ee5 --- /dev/null +++ b/drivers/pci/bus.c @@ -0,0 +1,110 @@ +#include +#include +#include +#include + +/** + * pci_match_one_device - Tell if a PCI device structure has a matching + * PCI device id structure + * @id: single PCI device id structure to match + * @dev: the PCI device structure to match against + * + * Returns the matching pci_device_id structure or %NULL if there is no match. + */ +static inline const struct pci_device_id * +pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && + (id->device == PCI_ANY_ID || id->device == dev->device) && + (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && + (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && + !((id->class ^ dev->class) & id->class_mask)) + return id; + return NULL; +} + +static int pci_match(struct device_d *dev, struct driver_d *drv) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_driver *pdrv = to_pci_driver(drv); + struct pci_device_id *id; + + for (id = (struct pci_device_id *)pdrv->id_table; id->vendor; id++) + if (pci_match_one_device(id, pdev)) { + dev->priv = id; + return 0; + } + + return -1; +} + +static int pci_probe(struct device_d *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_driver *pdrv = to_pci_driver(dev->driver); + + return pdrv->probe(pdev, dev->priv); +} + +static void pci_remove(struct device_d *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_driver *pdrv = to_pci_driver(dev->driver); + + pdrv->remove(pdev); +} + +struct bus_type pci_bus = { + .name = "pci", + .match = pci_match, + .probe = pci_probe, + .remove = pci_remove, +}; + +static int pci_bus_init(void) +{ + return bus_register(&pci_bus); +} +pure_initcall(pci_bus_init); + +int pci_register_driver(struct pci_driver *pdrv) +{ + struct driver_d *drv = &pdrv->driver; + + if (!pdrv->id_table) + return -EIO; + + drv->name = pdrv->name; + drv->bus = &pci_bus; + + return register_driver(drv); +} + +int pci_register_device(struct pci_dev *pdev) +{ + char str[6]; + struct device_d *dev = &pdev->dev; + int ret; + + strcpy(dev->name, "pci"); + dev->bus = &pci_bus; + dev->id = DEVICE_ID_DYNAMIC; + + ret = register_device(dev); + + if (ret) + return ret; + + sprintf(str, "%02x", pdev->devfn); + dev_add_param_fixed(dev, "devfn", str); + sprintf(str, "%04x", (pdev->class >> 8) & 0xffff); + dev_add_param_fixed(dev, "class", str); + sprintf(str, "%04x", pdev->vendor); + dev_add_param_fixed(dev, "vendor", str); + sprintf(str, "%04x", pdev->device); + dev_add_param_fixed(dev, "device", str); + sprintf(str, "%04x", pdev->revision); + dev_add_param_fixed(dev, "revision", str); + + return 0; +} diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c new file mode 100644 index 0000000..9bee73f --- /dev/null +++ b/drivers/pci/pci.c @@ -0,0 +1,282 @@ +#include +#include + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +static struct pci_controller *hose_head, **hose_tail = &hose_head; + +struct pci_bus *pci_root; + +static struct pci_bus *pci_alloc_bus(void) +{ + struct pci_bus *b; + + b = kzalloc(sizeof(*b), GFP_KERNEL); + if (b) { + INIT_LIST_HEAD(&b->node); + INIT_LIST_HEAD(&b->children); + INIT_LIST_HEAD(&b->devices); + INIT_LIST_HEAD(&b->slots); + INIT_LIST_HEAD(&b->resources); + } + return b; +} + +void register_pci_controller(struct pci_controller *hose) +{ + struct pci_bus *bus; + + *hose_tail = hose; + hose_tail = &hose->next; + + bus = pci_alloc_bus(); + hose->bus = bus; + bus->ops = hose->pci_ops; + bus->resource[0] = hose->mem_resource; + bus->resource[1] = hose->io_resource; + + pci_scan_bus(bus); + + pci_root = bus; + + return; +} + +int +pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, u8 where, u8 *val) +{ + u32 data; + int status; + + status = bus->ops->read(bus, devfn, where & 0xfc, 4, &data); + *val = (u8) (data >> ((where & 3) << 3)); + return status; +} + +int +pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, u8 where, u16 *val) +{ + u32 data; + int status; + + status = bus->ops->read(bus, devfn, where & 0xfc, 4, &data); + *val = (u16) (data >> ((where & 3) << 3)); + return status; +} + +int +pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, u8 where, u32 *val) +{ + return bus->ops->read(bus, devfn, where, 4, val); +} + +int +pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, u8 where, u8 val) +{ + u32 data; + int status; + + bus->ops->read(bus, devfn, where & 0xfc, 4, &data); + data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + status = bus->ops->write(bus, devfn, where & 0xfc, 4, data); + + return status; +} + +int +pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, u8 where, u16 val) +{ + u32 data; + int status; + + bus->ops->read(bus, devfn, where & 0xfc, 4, &data); + data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + status = bus->ops->write(bus, devfn, where & 0xfc, 4, data); + + return status; +} + +int +pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, u8 where, u32 val) +{ + return bus->ops->write(bus, devfn, where, 4, val); +} + +int +pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val) +{ + return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); +} + +int +pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val) +{ + return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); +} + +int +pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val) +{ + return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); +} + +int +pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val) +{ + return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); +} + +int +pci_write_config_word(struct pci_dev *dev, u8 where, u16 val) +{ + return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); +} + +int +pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val) +{ + return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); +} + +static struct pci_dev *alloc_pci_dev(void) +{ + struct pci_dev *dev; + + dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); + if (!dev) + return NULL; + + INIT_LIST_HEAD(&dev->bus_list); + + return dev; +} + +unsigned int pci_scan_bus(struct pci_bus *bus) +{ + unsigned int devfn, l, max, class; + unsigned char cmd, tmp, hdr_type, is_multi = 0; + struct pci_dev *dev; + resource_size_t last_mem; + resource_size_t last_io; + + /* FIXME: use res_start() */ + last_mem = bus->resource[0]->start; + last_io = bus->resource[1]->start; + + DBG("pci_scan_bus for bus %d\n", bus->number); + DBG(" last_io = 0x%08x, last_mem = 0x%08x\n", last_io, last_mem); + max = bus->secondary; + + for (devfn = 0; devfn < 0xff; ++devfn) { + int bar; + u32 old_bar, mask; + int size; + + if (PCI_FUNC(devfn) && !is_multi) { + /* not a multi-function device */ + continue; + } + if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) + continue; + if (!PCI_FUNC(devfn)) + is_multi = hdr_type & 0x80; + + if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l) || + /* some broken boards return 0 if a slot is empty: */ + l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000) + continue; + + dev = alloc_pci_dev(); + if (!dev) + return 0; + + dev->bus = bus; + dev->devfn = devfn; + dev->vendor = l & 0xffff; + dev->device = (l >> 16) & 0xffff; + + /* non-destructively determine if device can be a master: */ + pci_read_config_byte(dev, PCI_COMMAND, &cmd); + pci_write_config_byte(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); + pci_read_config_byte(dev, PCI_COMMAND, &tmp); + pci_write_config_byte(dev, PCI_COMMAND, cmd); + + pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); + dev->revision = class & 0xff; + class >>= 8; /* upper 3 bytes */ + dev->class = class; + class >>= 8; + dev->hdr_type = hdr_type; + + DBG("PCI: class = %08x, hdr_type = %08x\n", class, hdr_type); + + switch (hdr_type & 0x7f) { /* header type */ + case PCI_HEADER_TYPE_NORMAL: /* standard header */ + if (class == PCI_CLASS_BRIDGE_PCI) + goto bad; + + /* + * read base address registers, again pcibios_fixup() can + * tweak these + */ + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &l); + dev->rom_address = (l == 0xffffffff) ? 0 : l; + break; + default: /* unknown header */ + bad: + printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n", + bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type); + continue; + } + + DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device); + + list_add_tail(&dev->bus_list, &bus->devices); + pci_register_device(dev); + + if (class == PCI_CLASS_BRIDGE_HOST) { + DBG("PCI: skip pci host bridge\n"); + continue; + } + + for (bar = 0; bar < 6; bar++) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &old_bar); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, 0xfffffffe); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &mask); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, old_bar); + + if (mask == 0 || mask == 0xffffffff) { + DBG(" PCI: pbar%d set bad mask\n", bar); + continue; + } + + if (mask & 0x01) { /* IO */ + size = -(mask & 0xfffffffe); + DBG(" PCI: pbar%d: mask=%08x io %d bytes\n", bar, mask, size); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io); + last_io += size; + + } else { /* MEM */ + size = -(mask & 0xfffffff0); + DBG(" PCI: pbar%d: mask=%08x memory %d bytes\n", bar, mask, size); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem); + last_mem += size; + } + } + } + + /* + * We've scanned the bus and so we know all about what's on + * the other side of any bridges that may be on this bus plus + * any devices. + * + * Return how far we've got finding sub-buses. + */ + DBG("PCI: pci_scan_bus returning with max=%02x\n", max); + + return max; +} diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h new file mode 100644 index 0000000..c822075 --- /dev/null +++ b/include/linux/mod_devicetable.h @@ -0,0 +1,20 @@ +/* + * Device tables which are exported to userspace via + * scripts/mod/file2alias.c. You must keep that file in sync with this + * header. + */ + +#ifndef LINUX_MOD_DEVICETABLE_H +#define LINUX_MOD_DEVICETABLE_H + +#include + +#define PCI_ANY_ID (~0) + +struct pci_device_id { + __u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ + __u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + __u32 class, class_mask; /* (class,subclass,prog-if) triplet */ +}; + +#endif /* LINUX_MOD_DEVICETABLE_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h new file mode 100644 index 0000000..1411692 --- /dev/null +++ b/include/linux/pci.h @@ -0,0 +1,241 @@ +/* + * pci.h + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ +#ifndef LINUX_PCI_H +#define LINUX_PCI_H + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + + +/* + * The PCI interface treats multi-function devices as independent + * devices. The slot/function address of each device is encoded + * in a single byte as follows: + * + * 7:3 = slot + * 2:0 = function + */ +#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCI_FUNC(devfn) ((devfn) & 0x07) + + +/* + * Error values that may be returned by PCI functions. + */ +#define PCIBIOS_SUCCESSFUL 0x00 +#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 +#define PCIBIOS_BAD_VENDOR_ID 0x83 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 +#define PCIBIOS_SET_FAILED 0x88 +#define PCIBIOS_BUFFER_TOO_SMALL 0x89 + +#define DEVICE_COUNT_RESOURCE 12 +#define PCI_BRIDGE_RESOURCE_NUM 2 + +/* + * The pci_dev structure is used to describe PCI devices. + */ +struct pci_dev { + struct list_head bus_list; /* node in per-bus list */ + struct pci_bus *bus; /* bus this device is on */ + struct pci_bus *subordinate; /* bus this device bridges to */ + + void *sysdata; /* hook for sys-specific extension */ + struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ + struct pci_slot *slot; /* Physical slot this device is in */ + + struct device_d dev; + + unsigned int devfn; /* encoded device & function index */ + unsigned short vendor; + unsigned short device; + unsigned short subsystem_vendor; + unsigned short subsystem_device; + unsigned int class; /* 3 bytes: (base,sub,prog-if) */ + u8 revision; /* PCI revision, low byte of class word */ + u8 hdr_type; /* PCI header type (`multi' flag masked out) */ + + struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ + + /* Base registers for this device, can be adjusted by + * pcibios_fixup() as necessary. + */ + unsigned long base_address[6]; + unsigned long rom_address; +}; +#define to_pci_dev(dev) container_of(dev, struct pci_dev, dev) + +struct pci_bus { + struct list_head node; /* node in list of buses */ + struct pci_bus *parent; /* parent bus this bridge is on */ + struct list_head children; /* list of child buses */ + struct list_head devices; /* list of devices on this bus */ + struct pci_dev *self; /* bridge device as seen by parent */ + struct list_head slots; /* list of slots on this bus */ + struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; + struct list_head resources; /* address space routed to this bus */ + + struct pci_ops *ops; /* configuration access functions */ + void *sysdata; /* hook for sys-specific extension */ + struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ + + unsigned char number; /* bus number */ + unsigned char primary; /* number of primary bridge */ + unsigned char secondary; /* number of secondary bridge */ + unsigned char subordinate; /* max number of subordinate buses */ + + char name[48]; +}; + +/* Low-level architecture-dependent routines */ + +struct pci_ops { + int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); + int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + + /* return memory address for pci resource */ + int (*res_start)(struct pci_bus *bus, resource_size_t res_addr); +}; + +extern struct pci_ops *pci_ops; + +/* + * Each pci channel is a top-level PCI bus seem by CPU. A machine with + * multiple PCI channels may have multiple PCI host controllers or a + * single controller supporting multiple channels. + */ +struct pci_controller { + struct pci_controller *next; + struct pci_bus *bus; + + struct pci_ops *pci_ops; + struct resource *mem_resource; + unsigned long mem_offset; + struct resource *io_resource; + unsigned long io_offset; + unsigned long io_map_base; + + unsigned int index; + + /* Optional access methods for reading/writing the bus number + of the PCI controller */ + int (*get_busno)(void); + void (*set_busno)(int busno); +}; + +struct pci_driver { + struct list_head node; + const char *name; + const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ + int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ + void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ + struct driver_d driver; +}; + +#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) + +/** + * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table + * @_table: device table name + * + * This macro is used to create a struct pci_device_id array (a device table) + * in a generic manner. + */ +#define DEFINE_PCI_DEVICE_TABLE(_table) \ + const struct pci_device_id _table[] + +/** + * PCI_DEVICE - macro used to describe a specific pci device + * @vend: the 16 bit PCI Vendor ID + * @dev: the 16 bit PCI Device ID + * + * This macro is used to create a struct pci_device_id that matches a + * specific device. The subvendor and subdevice fields will be set to + * PCI_ANY_ID. + */ +#define PCI_DEVICE(vend, dev) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID + +/** + * PCI_DEVICE_CLASS - macro used to describe a specific pci device class + * @dev_class: the class, subclass, prog-if triple for this device + * @dev_class_mask: the class mask for this device + * + * This macro is used to create a struct pci_device_id that matches a + * specific PCI class. The vendor, device, subvendor, and subdevice + * fields will be set to PCI_ANY_ID. + */ +#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ + .class = (dev_class), .class_mask = (dev_class_mask), \ + .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID + +/** + * PCI_VDEVICE - macro used to describe a specific pci device in short form + * @vend: the vendor name + * @dev: the 16 bit PCI Device ID + * + * This macro is used to create a struct pci_device_id that matches a + * specific PCI device. The subvendor, and subdevice fields will be set + * to PCI_ANY_ID. The macro allows the next field to follow as the device + * private data. + */ + +#define PCI_VDEVICE(vend, dev) \ + .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 + +int pci_register_driver(struct pci_driver *pdrv); +int pci_register_device(struct pci_dev *pdev); + +extern struct pci_bus *pci_root; + +extern unsigned int pci_scan_bus(struct pci_bus *bus); +extern void register_pci_controller(struct pci_controller *hose); + +extern int pci_bus_read_config_byte(struct pci_bus *bus, + unsigned int devfn, u8 where, u8 *val); +extern int pci_bus_read_config_word(struct pci_bus *bus, + unsigned int devfn, u8 where, u16 *val); +extern int pci_bus_read_config_dword(struct pci_bus *bus, + unsigned int devfn, u8 where, u32 *val); +extern int pci_bus_write_config_byte(struct pci_bus *bus, + unsigned int devfn, u8 where, u8 val); +extern int pci_bus_write_config_word(struct pci_bus *bus, + unsigned int devfn, u8 where, u16 val); +extern int pci_bus_write_config_dword(struct pci_bus *bus, + unsigned int devfn, u8 where, u32 val); + +extern int pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val); +extern int pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val); +extern int pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val); +extern int pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val); +extern int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val); +extern int pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val); + +#endif /* LINUX_PCI_H */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h new file mode 100644 index 0000000..49e2954 --- /dev/null +++ b/include/linux/pci_ids.h @@ -0,0 +1,136 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + * + * Do not add new entries to this file unless the definitions + * are shared between multiple drivers. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 +#define PCI_CLASS_STORAGE_SAS 0x0107 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 +#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_SDHCI 0x0805 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 +#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 +#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 +#define PCI_CLASS_SERIAL_USB_XHCI 0x0c0330 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 + +#define PCI_BASE_CLASS_WIRELESS 0x0d +#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 +#define PCI_CLASS_WIRELESS_WHCI 0x0d1010 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h new file mode 100644 index 0000000..9e11a0d --- /dev/null +++ b/include/linux/pci_regs.h @@ -0,0 +1,118 @@ +/* + * pci_regs.h + * + * PCI standard defines + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + * + * For HyperTransport information, please consult the following manuals + * from http://www.hypertransport.org + * + * The HyperTransport I/O Link Specification + */ + +#ifndef LINUX_PCI_REGS_H +#define LINUX_PCI_REGS_H + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) +#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +#endif /* LINUX_PCI_REGS_H */ -- 1.9.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox