From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Sascha Hauer <s.hauer@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
barebox@lists.infradead.org
Subject: [PATCH v3 3/8] pci: pci_scan_bus: respect 64b BARs
Date: Wed, 30 Jul 2014 10:39:35 +0200 [thread overview]
Message-ID: <1406709580-5585-4-git-send-email-sebastian.hesselbarth@gmail.com> (raw)
In-Reply-To: <1406709580-5585-1-git-send-email-sebastian.hesselbarth@gmail.com>
In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type
indicates a 64-bit BAR we have to skip the next BAR register.
While at it, also set proper IORESOURCE flags for I/O and
32b MEM.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
---
Changelog:
v2->v3:
- IORESOURCE_MEM_64 is ORed with IORESOURCE_MEM
- write 0 to upper 64b BAR register
v1->v2:
- set resource flags for all resources found (Suggested by Lucas Stach)
- use MEM_64 resource flag for BAR64 detection (Suggested by Lucas Stach)
Cc: barebox@lists.infradead.org
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
drivers/pci/pci.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3d88b0ff5fd0..83d44fc103f7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -211,19 +211,29 @@ unsigned int pci_scan_bus(struct pci_bus *bus)
size = -(mask & 0xfffffffe);
DBG(" PCI: pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
+ dev->resource[bar].flags = IORESOURCE_IO;
last_addr = last_io;
last_io += size;
-
} else { /* MEM */
size = -(mask & 0xfffffff0);
DBG(" PCI: pbar%d: mask=%08x memory %d bytes\n", bar, mask, size);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
+ dev->resource[bar].flags = IORESOURCE_MEM;
last_addr = last_mem;
last_mem += size;
+
+ if ((mask & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dev->resource[bar].flags |= IORESOURCE_MEM_64;
+ pci_write_config_dword(dev,
+ PCI_BASE_ADDRESS_1 + bar * 4, 0);
+ }
}
dev->resource[bar].start = last_addr;
dev->resource[bar].end = last_addr + size - 1;
+ if (dev->resource[bar].flags & IORESOURCE_MEM_64)
+ bar++;
}
}
--
2.0.0
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next prev parent reply other threads:[~2014-07-30 8:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-30 8:39 [PATCH v3 0/8] Marvell EBU PCIe driver Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 1/8] bus: mvebu: fix resource size handling Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 2/8] ARM: mvebu: armada-370-xp: disable MBUS error propagation Sebastian Hesselbarth
2014-07-30 8:39 ` Sebastian Hesselbarth [this message]
2014-07-30 8:39 ` [PATCH v3 4/8] pci: register device after BAR setup Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 5/8] pci: ensure device does ignore BAR mangling Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 6/8] pci: set auto-incremented bus number Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 7/8] of: pci: import of_pci_get_devfn() Sebastian Hesselbarth
2014-07-30 8:39 ` [PATCH v3 8/8] pci: mvebu: Add PCIe driver Sebastian Hesselbarth
2014-07-30 9:16 ` [PATCH v3 0/8] Marvell EBU " Lucas Stach
2014-07-31 5:30 ` Sascha Hauer
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