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From: "Raphaël Poggi" <poggi.raph@gmail.com>
To: barebox@lists.infradead.org
Cc: "Raphaël Poggi" <poggi.raph@gmail.com>
Subject: [PATCH v3 1/3] arm: mach-at91: move gpio.h to include folder
Date: Tue,  2 Sep 2014 13:07:58 +0200	[thread overview]
Message-ID: <1409656080-19280-2-git-send-email-poggi.raph@gmail.com> (raw)
In-Reply-To: <1409656080-19280-1-git-send-email-poggi.raph@gmail.com>

This commit add functions from mach-at91/gpio.h in include/mach/gpio.h.
This allow to use these functions outside the mach-at91 folder.

Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
---
 arch/arm/mach-at91/gpio.c              |    2 +-
 arch/arm/mach-at91/gpio.h              |  148 -------------------------------
 arch/arm/mach-at91/include/mach/gpio.h |  149 ++++++++++++++++++++++++++++++++
 3 files changed, 150 insertions(+), 149 deletions(-)
 delete mode 100644 arch/arm/mach-at91/gpio.h

diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 4f2c76e..402634b 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -32,7 +32,7 @@
 #include <driver.h>
 #include <getopt.h>
 
-#include "gpio.h"
+#include <mach/gpio.h>
 
 #define MAX_GPIO_BANKS		5
 
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index d40628b..0000000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_GPIO_H__
-#define __AT91_GPIO_H__
-
-#ifndef __gpio_init
-#define __gpio_init
-#endif
-
-#define MAX_NB_GPIO_PER_BANK	32
-
-static inline unsigned pin_to_bank(unsigned pin)
-{
-	return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_bank_offset(unsigned pin)
-{
-	return pin % MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
-	return 1 << pin_to_bank_offset(pin);
-}
-
-static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_IDR);
-}
-
-static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
-{
-	__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
-}
-
-static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
-{
-	__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
-}
-
-static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_ASR);
-}
-
-static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_BSR);
-}
-
-static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
-{
-
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
-						pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-						pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
-						pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-						pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-}
-
-static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	if (is_on)
-		__raw_writel(mask, pio + PIO_IFSCDR);
-	at91_mux_set_deglitch(pio, mask, is_on);
-}
-
-static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
-				bool is_on, u32 div)
-{
-	if (is_on) {
-		__raw_writel(mask, pio + PIO_IFSCER);
-		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
-		__raw_writel(mask, pio + PIO_IFER);
-	} else {
-		__raw_writel(mask, pio + PIO_IFDR);
-	}
-}
-
-static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
-{
-	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-}
-
-static __gpio_init void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-}
-
-static __gpio_init void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_PDR);
-}
-
-static __gpio_init void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_PER);
-}
-
-static __gpio_init void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
-{
-	__raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
-}
-
-static __gpio_init void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
-int value)
-{
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-}
-
-static __gpio_init int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
-{
-       u32 pdsr;
-
-       pdsr = __raw_readl(pio + PIO_PDSR);
-       return (pdsr & mask) != 0;
-}
-
-#endif /* __AT91_GPIO_H__ */
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 306ab4c..6a6b9cd 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -1 +1,150 @@
+/*
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_GPIO_H__
+#define __AT91_GPIO_H__
+
 #include <asm-generic/gpio.h>
+
+#ifndef __gpio_init
+#define __gpio_init
+#endif
+
+#define MAX_NB_GPIO_PER_BANK	32
+
+static inline unsigned pin_to_bank(unsigned pin)
+{
+	return pin / MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_bank_offset(unsigned pin)
+{
+	return pin % MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+	return 1 << pin_to_bank_offset(pin);
+}
+
+static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_IDR);
+}
+
+static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
+{
+	__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
+}
+
+static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
+{
+	__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
+}
+
+static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_ASR);
+}
+
+static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_BSR);
+}
+
+static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
+{
+
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
+{
+	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+}
+
+static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
+{
+	if (is_on)
+		__raw_writel(mask, pio + PIO_IFSCDR);
+	at91_mux_set_deglitch(pio, mask, is_on);
+}
+
+static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
+				bool is_on, u32 div)
+{
+	if (is_on) {
+		__raw_writel(mask, pio + PIO_IFSCER);
+		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+		__raw_writel(mask, pio + PIO_IFER);
+	} else {
+		__raw_writel(mask, pio + PIO_IFDR);
+	}
+}
+
+static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
+{
+	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+}
+
+static __gpio_init void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+}
+
+static __gpio_init void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_PDR);
+}
+
+static __gpio_init void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_PER);
+}
+
+static __gpio_init void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
+{
+	__raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
+}
+
+static __gpio_init void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
+int value)
+{
+	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+}
+
+static __gpio_init int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
+{
+       u32 pdsr;
+
+       pdsr = __raw_readl(pio + PIO_PDSR);
+       return (pdsr & mask) != 0;
+}
+
+#endif /* __AT91_GPIO_H__ */
-- 
1.7.9.5


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  reply	other threads:[~2014-09-02 11:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-02 11:07 [PATCH v3 0/3] Add atmel pinctrl driver Raphaël Poggi
2014-09-02 11:07 ` Raphaël Poggi [this message]
2014-09-03  7:00   ` [PATCH v3 1/3] arm: mach-at91: move gpio.h to include folder Sascha Hauer
2014-09-02 11:07 ` [PATCH v3 2/3] pinctrl: at91: add pinctrl driver Raphaël Poggi
2014-09-03  6:56   ` Sascha Hauer
2014-09-03 11:23     ` Raphaël Poggi
2014-09-03 13:52       ` Sascha Hauer
2014-09-03 15:10         ` Raphaël Poggi
2014-09-04  9:26           ` Sascha Hauer
2014-09-04  9:41             ` Raphaël Poggi
2014-09-02 11:08 ` [PATCH v3 3/3] at91sam9g45: add device tree gpio clocks Raphaël Poggi
2014-09-03  6:46   ` Sascha Hauer

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