[PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[Teresa Gámez]

Updated the SPI NOR flash entries. NOR flash got
detected but did not work.

- Updated muxing
- Fixed frequency
- Fixed CS
- Removed first compatible entry (the flashes used is changing frequently)

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
 arch/arm/dts/am335x-phytec-phycore.dts |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts
index 5678138..16febd3 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -50,10 +50,10 @@
 
 	spi0_pins: pinmux_spi0_pins {
 		pinctrl-single,pins = <
-			0x150 (INPUT_EN | MUX_MODE0)
-			0x154 (PULL_UP | INPUT_EN | MUX_MODE0)
-			0x158 (INPUT_EN | MUX_MODE0)
-			0x15c (PULL_UP | INPUT_EN | MUX_MODE0)
+			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
+			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
+			0x158 (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
+			0x15c (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
 		>;
 	};
 
@@ -172,9 +172,9 @@
 	status = "okay";
 
 	flash: m25p80 {
-		compatible = "sst,sst25vf032b", "m25p80";
-		spi-max-frequency = <15000000>;
-		reg = <1>;
+		compatible = "m25p80";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-- 
1.7.0.4


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[PATCH 2/5] ARM: phyCORE-AM335x: Update RAM Timings

[Teresa Gámez]

Increased the RAM frequency to 400MHz.
Recalculation of the RAM timing values was needed.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   70 +++++++++++-----------
 1 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index ff1f04e..ff0b021 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -16,15 +16,15 @@
 #include <debug_ll.h>
 
 static const struct am33xx_cmd_control pcm051_cmd = {
-	.slave_ratio0 = 0x40,
+	.slave_ratio0 = 0x80,
 	.dll_lock_diff0 = 0x0,
-	.invert_clkout0 = 0x1,
-	.slave_ratio1 = 0x40,
+	.invert_clkout0 = 0x0,
+	.slave_ratio1 = 0x80,
 	.dll_lock_diff1 = 0x0,
-	.invert_clkout1 = 0x1,
-	.slave_ratio2 = 0x40,
+	.invert_clkout1 = 0x0,
+	.slave_ratio2 = 0x80,
 	.dll_lock_diff2 = 0x0,
-	.invert_clkout2 = 0x1,
+	.invert_clkout2 = 0x0,
 };
 
 struct pcm051_sdram_timings {
@@ -42,57 +42,57 @@ struct pcm051_sdram_timings timings[] = {
 	/* 1x256M16 */
 	[MT41J128M16125IT_1x256M16] = {
 		.regs = {
-			.emif_read_latency	= 0x6,
-			.emif_tim1		= 0x0888A39B,
-			.emif_tim2		= 0x26337FDA,
-			.emif_tim3		= 0x501F830F,
-			.sdram_config		= 0x61C04AB2,
+			.emif_read_latency	= 0x7,
+			.emif_tim1		= 0x0AAAD4DB,
+			.emif_tim2		= 0x26437FDA,
+			.emif_tim3		= 0x501F83FF,
+			.sdram_config		= 0x61C052B2,
 			.zq_config		= 0x50074BE4,
-			.sdram_ref_ctrl		= 0x0000093B,
+			.sdram_ref_ctrl		= 0x00000C30,
 		},
 		.data = {
 			.rd_slave_ratio0	= 0x3B,
-			.wr_dqs_slave_ratio0	= 0x3B,
-			.fifo_we_slave_ratio0	= 0x97,
-			.wr_slave_ratio0	= 0x76,
+			.wr_dqs_slave_ratio0	= 0x33,
+			.fifo_we_slave_ratio0	= 0x9c,
+			.wr_slave_ratio0	= 0x6f,
 		},
 	},
 
 	/* 1x128M16 */
 	[MT41J64M1615IT_1x128M16] = {
 		.regs =  {
-			.emif_read_latency	= 0x6,
-			.emif_tim1		= 0x0888A39B,
-			.emif_tim2		= 0x26247FDA,
-			.emif_tim3		= 0x501F821F,
-			.sdram_config		= 0x61C04A32,
+			.emif_read_latency	= 0x7,
+			.emif_tim1		= 0x0AAAE4DB,
+			.emif_tim2		= 0x262F7FDA,
+			.emif_tim3		= 0x501F82BF,
+			.sdram_config		= 0x61C05232,
 			.zq_config		= 0x50074BE4,
-			.sdram_ref_ctrl		= 0x0000093B,
+			.sdram_ref_ctrl		= 0x00000C30,
 		},
 		.data = {
-			.rd_slave_ratio0	= 0x3A,
-			.wr_dqs_slave_ratio0	= 0x36,
+			.rd_slave_ratio0	= 0x38,
+			.wr_dqs_slave_ratio0	= 0x34,
 			.fifo_we_slave_ratio0	= 0xA2,
-			.wr_slave_ratio0	= 0x74,
+			.wr_slave_ratio0	= 0x72,
 		},
 	},
 
 	/* 1x512MB */
 	[MT41J256M16HA15EIT_1x512M16] = {
 		.regs = {
-			.emif_read_latency	= 0x6,
-			.emif_tim1		= 0x0888A39B,
-			.emif_tim2		= 0x26517FDA,
-			.emif_tim3		= 0x501F84EF,
-			.sdram_config		= 0x61C04B32,
+			.emif_read_latency	= 0x7,
+			.emif_tim1		= 0x0AAAE4DB,
+			.emif_tim2		= 0x266B7FDA,
+			.emif_tim3		= 0x501F867F,
+			.sdram_config		= 0x61C05332,
 			.zq_config		= 0x50074BE4,
-			.sdram_ref_ctrl		= 0x0000093B,
+			.sdram_ref_ctrl		= 0x00000C30
 		},
 		.data = {
-			.rd_slave_ratio0	= 0x3B,
-			.wr_dqs_slave_ratio0	= 0x3B,
-			.fifo_we_slave_ratio0	= 0x96,
-			.wr_slave_ratio0	= 0x76,
+			.rd_slave_ratio0	= 0x35,
+			.wr_dqs_slave_ratio0	= 0x43,
+			.fifo_we_slave_ratio0	= 0x97,
+			.wr_slave_ratio0	= 0x7b,
 		},
 	},
 };
@@ -122,7 +122,7 @@ static noinline void pcm051_board_init(int sdram)
 	writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
 	while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
 
-	am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
+	am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_400);
 
 	am335x_sdram_init(0x18B, &pcm051_cmd,
 			&timing->regs,
-- 
1.7.0.4


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[PATCH 3/5] ARM: phyCORE-AM335x: Fixup RAM setting naming

[Teresa Gámez]

Naming is confusing and wrong. Fixed it up.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   30 +++++++++++-----------
 images/Makefile.am33xx                           |   18 ++++++------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index ff0b021..a15e151 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -33,14 +33,14 @@ struct pcm051_sdram_timings {
 };
 
 enum {
-	MT41J128M16125IT_1x256M16,
-	MT41J64M1615IT_1x128M16,
-	MT41J256M16HA15EIT_1x512M16,
+	MT41J128M16125IT_256MB,
+	MT41J64M1615IT_128MB,
+	MT41J256M16HA15EIT_512MB,
 };
 
 struct pcm051_sdram_timings timings[] = {
-	/* 1x256M16 */
-	[MT41J128M16125IT_1x256M16] = {
+	/* 256MB */
+	[MT41J128M16125IT_256MB] = {
 		.regs = {
 			.emif_read_latency	= 0x7,
 			.emif_tim1		= 0x0AAAD4DB,
@@ -58,8 +58,8 @@ struct pcm051_sdram_timings timings[] = {
 		},
 	},
 
-	/* 1x128M16 */
-	[MT41J64M1615IT_1x128M16] = {
+	/* 128MB */
+	[MT41J64M1615IT_128MB] = {
 		.regs =  {
 			.emif_read_latency	= 0x7,
 			.emif_tim1		= 0x0AAAE4DB,
@@ -77,8 +77,8 @@ struct pcm051_sdram_timings timings[] = {
 		},
 	},
 
-	/* 1x512MB */
-	[MT41J256M16HA15EIT_1x512M16] = {
+	/* 512MB */
+	[MT41J256M16HA15EIT_512MB] = {
 		.regs = {
 			.emif_read_latency	= 0x7,
 			.emif_tim1		= 0x0AAAE4DB,
@@ -154,19 +154,19 @@ static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram)
 	pcm051_board_init(sdram);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x256m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2)
 {
-	pcm051_board_entry(bootinfo, MT41J128M16125IT_1x256M16);
+	pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x128m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2)
 {
-	pcm051_board_entry(bootinfo, MT41J64M1615IT_1x128M16);
+	pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x512m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2)
 {
-	pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_1x512M16);
+	pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
 }
 
 ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index fa1f848..c1f19c1 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -11,17 +11,17 @@ pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sdram
 FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_sdram.pblx
 am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x256m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x256m16.img = start_am33xx_phytec_phycore_sram_1x256m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x256m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_256mb
+FILE_barebox-am33xx-phytec-phycore-mlo-256mb.img = start_am33xx_phytec_phycore_sram_256mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-256mb.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x128m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x128m16.img = start_am33xx_phytec_phycore_sram_1x128m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x128m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_128mb
+FILE_barebox-am33xx-phytec-phycore-mlo-128mb.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-128mb.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x512m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x512m16.img = start_am33xx_phytec_phycore_sram_1x512m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-1x512m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_512mb
+FILE_barebox-am33xx-phytec-phycore-mlo-512mb.img = start_am33xx_phytec_phycore_sram_512mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-512mb.img
 
 pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
 FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
-- 
1.7.0.4


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[PATCH 4/5] ARM: phyCORE-AM335x: Add support for 2x512MB RAM

[Teresa Gámez]

Added settings for 1GB RAM option.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   25 ++++++++++++++++++++++
 images/Makefile.am33xx                           |    4 +++
 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index a15e151..66bae80 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -36,6 +36,7 @@ enum {
 	MT41J128M16125IT_256MB,
 	MT41J64M1615IT_128MB,
 	MT41J256M16HA15EIT_512MB,
+	MT41J512M8125IT_2x512MB,
 };
 
 struct pcm051_sdram_timings timings[] = {
@@ -95,6 +96,25 @@ struct pcm051_sdram_timings timings[] = {
 			.wr_slave_ratio0	= 0x7b,
 		},
 	},
+
+	/* 1024MB */
+	[MT41J512M8125IT_2x512MB] = {
+		.regs = {
+			.emif_read_latency	= 0x7,
+			.emif_tim1		= 0x0AAAE4DB,
+			.emif_tim2		= 0x266B7FDA,
+			.emif_tim3		= 0x501F867F,
+			.sdram_config		= 0x61C053B2,
+			.zq_config		= 0x50074BE4,
+			.sdram_ref_ctrl		= 0x00000C30
+		},
+		.data = {
+			.rd_slave_ratio0	= 0x32,
+			.wr_dqs_slave_ratio0	= 0x48,
+			.fifo_we_slave_ratio0	= 0x99,
+			.wr_slave_ratio0	= 0x80,
+		},
+	},
 };
 
 extern char __dtb_am335x_phytec_phycore_start[];
@@ -169,6 +189,11 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2)
 	pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
 }
 
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2)
+{
+	pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB);
+}
+
 ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
 {
 	void *fdt;
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index c1f19c1..d24338e 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -23,6 +23,10 @@ pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_512mb
 FILE_barebox-am33xx-phytec-phycore-mlo-512mb.img = start_am33xx_phytec_phycore_sram_512mb.pblx.mlo
 am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-512mb.img
 
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_2x512mb
+FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-2x512mb.img
+
 pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
 FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
 am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img
-- 
1.7.0.4


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[PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

[Teresa Gámez]

Added device tree partition and made rootfs partition
variable size depending on nand flash size.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
---
 arch/arm/dts/am335x-phytec-phycore.dts |   22 ++++++++++++++++++----
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts
index 16febd3..047dc15 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -194,8 +194,13 @@
 		};
 
 		partition@3 {
+			label = "oftree";
+			reg = <0xc0000 0x20000>;
+		};
+
+		partition@4 {
 			label = "kernel";
-			reg = <0xc0000 0x400000>;
+			reg = <0xe0000 0x400000>;
 		};
 	};
 };
@@ -305,13 +310,22 @@
 		};
 
 		partition@6 {
-			label = "kernel";
-			reg = <0x120000 0x800000>;
+			label = "oftree";
+			reg = <0x120000 0x20000>;
 		};
 
 		partition@7 {
+			label = "kernel";
+			reg = <0x140000 0x800000>;
+		};
+
+		partition@8 {
 			label = "root";
-			reg = <0x920000 0x1f6e0000>;
+			/*
+			 * Size 0x0 extends partition to
+			 * end of nand flash.
+			 */
+			reg = <0x920000 0x0>;
 		};
 	};
 };
-- 
1.7.0.4


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Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

[Alexander Aring]

Hi Teresa,

On Thu, Sep 04, 2014 at 08:50:40AM +0200, Teresa Gámez wrote:
> Added device tree partition and made rootfs partition
> variable size depending on nand flash size.
> 
> Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> ---
>  arch/arm/dts/am335x-phytec-phycore.dts |   22 ++++++++++++++++++----
>  1 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts
> index 16febd3..047dc15 100644
> --- a/arch/arm/dts/am335x-phytec-phycore.dts
> +++ b/arch/arm/dts/am335x-phytec-phycore.dts
> @@ -194,8 +194,13 @@
>  		};
>  
>  		partition@3 {
> +			label = "oftree";
> +			reg = <0xc0000 0x20000>;
> +		};
> +
> +		partition@4 {
>  			label = "kernel";
> -			reg = <0xc0000 0x400000>;
> +			reg = <0xe0000 0x400000>;
>  		};
>  	};
>  };
> @@ -305,13 +310,22 @@
>  		};
>  
>  		partition@6 {
> -			label = "kernel";
> -			reg = <0x120000 0x800000>;
> +			label = "oftree";
> +			reg = <0x120000 0x20000>;
>  		};
>  
>  		partition@7 {
> +			label = "kernel";
> +			reg = <0x140000 0x800000>;
> +		};
> +
> +		partition@8 {
>  			label = "root";
> -			reg = <0x920000 0x1f6e0000>;
> +			/*
> +			 * Size 0x0 extends partition to
> +			 * end of nand flash.
> +			 */
> +			reg = <0x920000 0x0>;

I think this should be 0x940000 insead 0x920000.

From partition7 7 "kernel" you have 0x140000 + 0x800000 = 0x940000.

I simple use the gnome-calculator in hex mode to check it.

- Alex

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Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

[Alexander Aring]

On Thu, Sep 04, 2014 at 09:12:58AM +0200, Alexander Aring wrote:
> Hi Teresa,
> 
> On Thu, Sep 04, 2014 at 08:50:40AM +0200, Teresa Gámez wrote:
> > Added device tree partition and made rootfs partition
> > variable size depending on nand flash size.
> > 
> > Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> > ---
> >  arch/arm/dts/am335x-phytec-phycore.dts |   22 ++++++++++++++++++----
> >  1 files changed, 18 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts
> > index 16febd3..047dc15 100644
> > --- a/arch/arm/dts/am335x-phytec-phycore.dts
> > +++ b/arch/arm/dts/am335x-phytec-phycore.dts
> > @@ -194,8 +194,13 @@
> >  		};
> >  
> >  		partition@3 {
> > +			label = "oftree";
> > +			reg = <0xc0000 0x20000>;
> > +		};
> > +
> > +		partition@4 {
> >  			label = "kernel";
> > -			reg = <0xc0000 0x400000>;
> > +			reg = <0xe0000 0x400000>;
> >  		};
> >  	};
> >  };
> > @@ -305,13 +310,22 @@
> >  		};
> >  
> >  		partition@6 {
> > -			label = "kernel";
> > -			reg = <0x120000 0x800000>;
> > +			label = "oftree";
> > +			reg = <0x120000 0x20000>;
> >  		};
> >  
> >  		partition@7 {
> > +			label = "kernel";
> > +			reg = <0x140000 0x800000>;
> > +		};
> > +
> > +		partition@8 {
> >  			label = "root";
> > -			reg = <0x920000 0x1f6e0000>;
> > +			/*
> > +			 * Size 0x0 extends partition to
> > +			 * end of nand flash.
> > +			 */
> > +			reg = <0x920000 0x0>;
> 
> I think this should be 0x940000 insead 0x920000.
> 
> From partition7 7 "kernel" you have 0x140000 + 0x800000 = 0x940000.
> 
> I simple use the gnome-calculator in hex mode to check it.
> 

But in this case it was very obviously. Can't have a two in this
position. :-)

- Alex

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Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[Sascha Hauer]

Hi Teresa,

On Thu, Sep 04, 2014 at 08:50:36AM +0200, Teresa Gámez wrote:
> Updated the SPI NOR flash entries. NOR flash got
> detected but did not work.
> 
> - Updated muxing
> - Fixed frequency
> - Fixed CS
> - Removed first compatible entry (the flashes used is changing frequently)
> 
> Signed-off-by: Teresa Gámez <t.gamez@phytec.de>

Applied up to 4/5. The Root partition start seems indeed wrong.

Sascha

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Pengutronix e.K.                           |                             |
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Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[Alexander Aring]

Hi Sascha,

On Fri, Sep 05, 2014 at 07:37:33AM +0200, Sascha Hauer wrote:
> Hi Teresa,
> 
> On Thu, Sep 04, 2014 at 08:50:36AM +0200, Teresa Gámez wrote:
> > Updated the SPI NOR flash entries. NOR flash got
> > detected but did not work.
> > 
> > - Updated muxing
> > - Fixed frequency
> > - Fixed CS
> > - Removed first compatible entry (the flashes used is changing frequently)
> > 
> > Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> 
> Applied up to 4/5. The Root partition start seems indeed wrong.
> 

yea. But sometimes you also do a "fixed while applying". Why not now?
Okay, maybe on the "good" days.


Nevertheless, isn't there any mechanism to check on conflicts while
creating partitions like request memory mapped regions?

- Alex

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Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[Sascha Hauer]

On Fri, Sep 05, 2014 at 08:32:00AM +0200, Alexander Aring wrote:
> Hi Sascha,
> 
> On Fri, Sep 05, 2014 at 07:37:33AM +0200, Sascha Hauer wrote:
> > Hi Teresa,
> > 
> > On Thu, Sep 04, 2014 at 08:50:36AM +0200, Teresa Gámez wrote:
> > > Updated the SPI NOR flash entries. NOR flash got
> > > detected but did not work.
> > > 
> > > - Updated muxing
> > > - Fixed frequency
> > > - Fixed CS
> > > - Removed first compatible entry (the flashes used is changing frequently)
> > > 
> > > Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> > 
> > Applied up to 4/5. The Root partition start seems indeed wrong.
> > 
> 
> yea. But sometimes you also do a "fixed while applying". Why not now?
> Okay, maybe on the "good" days.

Maybe because you didn't write the correct start offset and I didn't
feel like doing maths before the first coffee ;)

> 
> Nevertheless, isn't there any mechanism to check on conflicts while
> creating partitions like request memory mapped regions?

No. Right now creating multiple conflicting partitions is a feature, see
for example /dev/env0 and /dev/nor0.bareboxenv. Those are two
partitions which both conflict but must both exist.

I must admit it's a misfeature though and I wish we could do without it
as it really can hide problems.

Sascha

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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

[Alexander Aring]

On Fri, Sep 05, 2014 at 08:51:22AM +0200, Sascha Hauer wrote:
> On Fri, Sep 05, 2014 at 08:32:00AM +0200, Alexander Aring wrote:
> > Hi Sascha,
> > 
> > On Fri, Sep 05, 2014 at 07:37:33AM +0200, Sascha Hauer wrote:
> > > Hi Teresa,
> > > 
> > > On Thu, Sep 04, 2014 at 08:50:36AM +0200, Teresa Gámez wrote:
> > > > Updated the SPI NOR flash entries. NOR flash got
> > > > detected but did not work.
> > > > 
> > > > - Updated muxing
> > > > - Fixed frequency
> > > > - Fixed CS
> > > > - Removed first compatible entry (the flashes used is changing frequently)
> > > > 
> > > > Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> > > 
> > > Applied up to 4/5. The Root partition start seems indeed wrong.
> > > 
> > 
> > yea. But sometimes you also do a "fixed while applying". Why not now?
> > Okay, maybe on the "good" days.
> 
> Maybe because you didn't write the correct start offset and I didn't
> feel like doing maths before the first coffee ;)
> 

hey, I wrote a correct start offset with a calculation example. In
my last mail to Teresa. I can also give you the advice, to use a calculator
when it's too early in the morning.

My problem is to write some english, but I can't use google translator
or something like that to check it. (Sometimes the author of lilo "Werner
Almesberger" review my bad english and helps me there). :-)

> > 
> > Nevertheless, isn't there any mechanism to check on conflicts while
> > creating partitions like request memory mapped regions?
> 
> No. Right now creating multiple conflicting partitions is a feature, see
> for example /dev/env0 and /dev/nor0.bareboxenv. Those are two
> partitions which both conflict but must both exist.
> 

Sounds for me like doing symlink magic. But I don't feel like to doing
magic in the morning. I don't drink coffee since I stopped working at
phytec. Does devfs support symlinks? -> First look: "no".

> I must admit it's a misfeature though and I wish we could do without it
> as it really can hide problems.
> 

If symlink magic doesn't work, maybe add a flag/type which allow to have a
conflict partition? This sounds more like a feature which doesn't help
to check on misconfigured partitions, you can simple switch it off.

I would prefer the symlink magic idea.

- Alex

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