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From: Lucas Stach <dev@lynxeye.de>
To: barebox@lists.infradead.org
Subject: [PATCH 06/13] clk: tegra: slow down MSELECT to 102MHz
Date: Sun,  2 Nov 2014 21:13:48 +0100	[thread overview]
Message-ID: <1414959235-18095-7-git-send-email-dev@lynxeye.de> (raw)
In-Reply-To: <1414959235-18095-1-git-send-email-dev@lynxeye.de>

Don't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
Overclocking MSELECT by 100% seems to lead to
PCIe failures. Much more on T124 than on T30.
---
 drivers/clk/tegra/clk-tegra124.c | 2 +-
 drivers/clk/tegra/clk-tegra30.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 514b22a..3530127 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -286,7 +286,7 @@ static struct tegra_clk_init_table init_table[] = {
 	{TEGRA124_CLK_PLL_P_OUT2,	TEGRA124_CLK_CLK_MAX,	48000000,	1},
 	{TEGRA124_CLK_PLL_P_OUT3,	TEGRA124_CLK_CLK_MAX,	102000000,	1},
 	{TEGRA124_CLK_PLL_P_OUT4,	TEGRA124_CLK_CLK_MAX,	204000000,	1},
-	{TEGRA124_CLK_MSELECT,		TEGRA124_CLK_PLL_P,	204000000,	1},
+	{TEGRA124_CLK_MSELECT,		TEGRA124_CLK_PLL_P,	102000000,	1},
 	{TEGRA124_CLK_UARTA,		TEGRA124_CLK_PLL_P,	0,		1},
 	{TEGRA124_CLK_UARTB,		TEGRA124_CLK_PLL_P,	0,		1},
 	{TEGRA124_CLK_UARTC,		TEGRA124_CLK_PLL_P,	0,		1},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 9997ab9..7210053 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -351,7 +351,7 @@ static struct tegra_clk_init_table init_table[] = {
 	{TEGRA30_CLK_PLL_P_OUT2,	TEGRA30_CLK_CLK_MAX,	48000000,	1},
 	{TEGRA30_CLK_PLL_P_OUT3,	TEGRA30_CLK_CLK_MAX,	102000000,	1},
 	{TEGRA30_CLK_PLL_P_OUT4,	TEGRA30_CLK_CLK_MAX,	204000000,	1},
-	{TEGRA30_CLK_MSELECT,		TEGRA30_CLK_PLL_P,	204000000,	1},
+	{TEGRA30_CLK_MSELECT,		TEGRA30_CLK_PLL_P,	102000000,	1},
 	{TEGRA30_CLK_UARTA,		TEGRA30_CLK_PLL_P,	0,		1},
 	{TEGRA30_CLK_UARTB,		TEGRA30_CLK_PLL_P,	0,		1},
 	{TEGRA30_CLK_UARTC,		TEGRA30_CLK_PLL_P,	0,		1},
-- 
1.9.3


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  parent reply	other threads:[~2014-11-02 20:08 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-02 20:13 [PATCH 00/13] Tegra124 PCIe Lucas Stach
2014-11-02 20:13 ` [PATCH 01/13] net: rtl8169: add support for RTL-8168/8111g Lucas Stach
2014-11-02 20:13 ` [PATCH 02/13] net: rtl8169: clean receive buffer after net handler Lucas Stach
2014-11-02 20:13 ` [PATCH 03/13] tegra: defconfig: enable barebox OF drivers Lucas Stach
2014-11-02 20:13 ` [PATCH 04/13] pinctrl: tegra: try to select "boot" state Lucas Stach
2014-11-02 20:13 ` [PATCH 05/13] arm: dts: jetson-tk1: switch to upstream DT Lucas Stach
2014-11-02 20:13 ` Lucas Stach [this message]
2014-11-02 20:13 ` [PATCH 07/13] tegra: pmc: work around power domain failure Lucas Stach
2014-11-02 20:13 ` [PATCH 08/13] tegra: jetson-tk1: enable 1.05V_RUN Lucas Stach
2014-11-02 20:13 ` [PATCH 09/13] clk: tegra124: add PLLE setup functions Lucas Stach
2014-11-02 20:13 ` [PATCH 10/13] clk: tegra124: add PCIe clocks Lucas Stach
2014-11-02 20:13 ` [PATCH 11/13] add generic PHY framework Lucas Stach
2014-11-02 20:13 ` [PATCH 12/13] pinctrl: tegra: add XUSB pad controller Lucas Stach
2014-11-02 20:13 ` [PATCH 13/13] pci: tegra: add tegra124 support Lucas Stach
2014-11-03  8:40 ` [PATCH 00/13] Tegra124 PCIe Sascha Hauer

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