From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 1/4] arm/cpu/lowlevel: add and fix comments for CPSR and SCTLR accesses
Date: Thu, 11 Dec 2014 10:15:24 +0100 [thread overview]
Message-ID: <1418289327-28310-2-git-send-email-u.kleine-koenig@pengutronix.de> (raw)
In-Reply-To: <1418289327-28310-1-git-send-email-u.kleine-koenig@pengutronix.de>
A part of the existing comments was incomplete or missleading.
Adding the register name to mcr/mrc instructions helps finding the
corresponding documentation in the manuals.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/cpu/lowlevel.S | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index c615d5b58160..7cc14b954f1f 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -5,7 +5,7 @@
.section ".text_bare_init_","ax"
ENTRY(arm_cpu_lowlevel_init)
mov r2, lr
- /* set the cpu to SVC32 mode */
+ /* set the cpu to SVC32 mode, mask irq and fiq */
mrs r12, cpsr
bic r12, r12, #0x1f
orr r12, r12, #0xd3
@@ -17,10 +17,12 @@ ENTRY(arm_cpu_lowlevel_init)
mcr p15, 0, r12, c7, c5, 4
#endif
- /* disable MMU stuff and caches */
- mrc p15, 0, r12, c1, c0, 0
- bic r12, r12 , #(CR_M | CR_C | CR_B)
+ /* disable MMU stuff and data/unified caches */
+ mrc p15, 0, r12, c1, c0, 0 /* SCTLR */
+ bic r12, r12, #(CR_M | CR_C | CR_B)
bic r12, r12, #(CR_S | CR_R | CR_V)
+
+ /* enable instruction cache */
orr r12, r12, #CR_I
#if __LINUX_ARM_ARCH__ >= 6
@@ -34,7 +36,7 @@ ENTRY(arm_cpu_lowlevel_init)
orr r12, r12, #CR_B
#endif
- mcr p15, 0, r12, c1, c0, 0
+ mcr p15, 0, r12, c1, c0, 0 /* SCTLR */
mov pc, r2
ENDPROC(arm_cpu_lowlevel_init)
--
2.1.3
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next prev parent reply other threads:[~2014-12-11 9:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 9:15 [PATCH 0/4] arm/cpu/lowlevel cleanups Uwe Kleine-König
2014-12-11 9:15 ` Uwe Kleine-König [this message]
2014-12-11 9:15 ` [PATCH 2/4] arm/cpu/lowlevel: Use coprocessor instruction for ARMv7, too Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 3/4] arm/cpu/lowlevel: Don't save the return address in another register Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 4/4] arm/cpu/lowlevel: invalidate i-cache before enabling Uwe Kleine-König
2014-12-11 11:14 ` Lucas Stach
2014-12-11 12:05 ` Sascha Hauer
2014-12-11 13:08 ` Uwe Kleine-König
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