From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 3/4] arm/cpu/lowlevel: Don't save the return address in another register
Date: Thu, 11 Dec 2014 10:15:26 +0100 [thread overview]
Message-ID: <1418289327-28310-4-git-send-email-u.kleine-koenig@pengutronix.de> (raw)
In-Reply-To: <1418289327-28310-1-git-send-email-u.kleine-koenig@pengutronix.de>
The corresponding code doesn't use the lr register (neither explicitly
nor implicitly by the bl instruction), so there is no gain in using r2
here.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/cpu/lowlevel.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 7c99ecaad9dd..dd0f75a8802a 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -4,7 +4,6 @@
.section ".text_bare_init_","ax"
ENTRY(arm_cpu_lowlevel_init)
- mov r2, lr
/* set the cpu to SVC32 mode, mask irq and fiq */
mrs r12, cpsr
bic r12, r12, #0x1f
@@ -44,5 +43,5 @@ ENTRY(arm_cpu_lowlevel_init)
mcr p15, 0, r12, c1, c0, 0 /* SCTLR */
- mov pc, r2
+ mov pc, lr
ENDPROC(arm_cpu_lowlevel_init)
--
2.1.3
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next prev parent reply other threads:[~2014-12-11 9:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 9:15 [PATCH 0/4] arm/cpu/lowlevel cleanups Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 1/4] arm/cpu/lowlevel: add and fix comments for CPSR and SCTLR accesses Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 2/4] arm/cpu/lowlevel: Use coprocessor instruction for ARMv7, too Uwe Kleine-König
2014-12-11 9:15 ` Uwe Kleine-König [this message]
2014-12-11 9:15 ` [PATCH 4/4] arm/cpu/lowlevel: invalidate i-cache before enabling Uwe Kleine-König
2014-12-11 11:14 ` Lucas Stach
2014-12-11 12:05 ` Sascha Hauer
2014-12-11 13:08 ` Uwe Kleine-König
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