From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 4/4] arm/cpu/lowlevel: invalidate i-cache before enabling
Date: Thu, 11 Dec 2014 10:15:27 +0100 [thread overview]
Message-ID: <1418289327-28310-5-git-send-email-u.kleine-koenig@pengutronix.de> (raw)
In-Reply-To: <1418289327-28310-1-git-send-email-u.kleine-koenig@pengutronix.de>
Architecturally the cache contents are undefined so it might well
contain stale data at reset. So better be save than sorry.
I verifyed that the added instructions are defined for both, ARMv6 and
ARMv7, using the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
edition (ARM DDI 0406C.c).
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/cpu/lowlevel.S | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index dd0f75a8802a..af2b0a8ac93a 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -11,7 +11,19 @@ ENTRY(arm_cpu_lowlevel_init)
msr cpsr, r12
#if __LINUX_ARM_ARCH__ >= 6
+/*
+ * Invalidate instruction cache and branch predictor. Even if the
+ * i-cache is off it might contain stale entries that are better
+ * discarded before enabling the cache.
+ */
+ /* ICIALLU: Invalidate all instruction caches to PoU */
+ mcr p15, 0, r12, c7, c5, 0
+ /* BPIALL: Invalidate all branch predictors */
+ mcr p15, 0, r12, c7, c5, 6
+ /* DSB, ensure completion of the invalidation */
+ mcr p15, 0, r12, c7, c10, 4
/*
+ * ISB, ensure instruction fetch path is in sync.
* Note that the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
* edition (ARM DDI 0406C.c) doesn't define this instruction in the
* ARMv6 part (D12.7.10). It only has: "Support of additional
@@ -19,7 +31,7 @@ ENTRY(arm_cpu_lowlevel_init)
* But an earlier version of the ARMARM (ARM DDI 0100I) does define it
* as "Flush prefetch buffer (PrefetchFlush)".
*/
- mcr p15, 0, r12, c7, c5, 4 /* ISB */
+ mcr p15, 0, r12, c7, c5, 4
#endif
/* disable MMU stuff and data/unified caches */
--
2.1.3
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next prev parent reply other threads:[~2014-12-11 9:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-11 9:15 [PATCH 0/4] arm/cpu/lowlevel cleanups Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 1/4] arm/cpu/lowlevel: add and fix comments for CPSR and SCTLR accesses Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 2/4] arm/cpu/lowlevel: Use coprocessor instruction for ARMv7, too Uwe Kleine-König
2014-12-11 9:15 ` [PATCH 3/4] arm/cpu/lowlevel: Don't save the return address in another register Uwe Kleine-König
2014-12-11 9:15 ` Uwe Kleine-König [this message]
2014-12-11 11:14 ` [PATCH 4/4] arm/cpu/lowlevel: invalidate i-cache before enabling Lucas Stach
2014-12-11 12:05 ` Sascha Hauer
2014-12-11 13:08 ` Uwe Kleine-König
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