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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache
Date: Fri,  7 Aug 2015 15:35:41 +0200	[thread overview]
Message-ID: <1438954545-24917-2-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1438954545-24917-1-git-send-email-s.hauer@pengutronix.de>

When flushing the cache L1 has to be flushed before L2, not the
other way round.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 37bfa05..1bd6080 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -159,9 +159,9 @@ static u32 *find_pte(unsigned long adr)
 
 static void dma_flush_range(unsigned long start, unsigned long end)
 {
+	__dma_flush_range(start, end);
 	if (outer_cache.flush_range)
 		outer_cache.flush_range(start, end);
-	__dma_flush_range(start, end);
 }
 
 static void dma_inv_range(unsigned long start, unsigned long end)
-- 
2.4.6


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  reply	other threads:[~2015-08-07 13:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
2015-08-07 13:35 ` Sascha Hauer [this message]
2015-08-07 13:35 ` [PATCH 2/5] ARM: l2x0: Flush cache before disabling it Sascha Hauer
2015-08-07 13:35 ` [PATCH 3/5] ARM: l2x0: Implement L310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 4/5] ARM: l2x0: Add some informational debug messages Sascha Hauer
2015-08-07 13:35 ` [PATCH 5/5] ARM: i.MX6: Enable l2 cache Sascha Hauer

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