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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 2/5] ARM: l2x0: Flush cache before disabling it
Date: Fri,  7 Aug 2015 15:35:42 +0200	[thread overview]
Message-ID: <1438954545-24917-3-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1438954545-24917-1-git-send-email-s.hauer@pengutronix.de>

Otherwise entries may still be in the cache and never reach memory.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/cache-l2x0.c  | 13 ++++++++++++-
 arch/arm/cpu/cache.c       |  2 ++
 arch/arm/cpu/cpu.c         |  3 +--
 arch/arm/include/asm/mmu.h |  1 +
 4 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 2be562d..43f296f 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -112,6 +112,13 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 }
 
+static void l2x0_flush_all(void)
+{
+	writel(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+	cache_wait(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
+	cache_sync();
+}
+
 static void l2x0_disable(void)
 {
 	writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
@@ -149,5 +156,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
 	outer_cache.disable = l2x0_disable;
-}
+	outer_cache.flush_all = l2x0_flush_all;
 
+	pr_debug("%s cache controller enabled\n", type);
+	pr_debug("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
+			ways, cache_id, aux);
+}
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 7b161d5..27ead1c 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -71,6 +71,8 @@ void __mmu_cache_flush(void)
 {
 	if (cache_fns)
 		cache_fns->mmu_cache_flush();
+	if (outer_cache.flush_all)
+		outer_cache.flush_all();
 }
 
 int arm_set_cache_functions(void)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 5e70802..ff8f43d 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -79,10 +79,9 @@ struct outer_cache_fns outer_cache;
  */
 void mmu_disable(void)
 {
+	__mmu_cache_flush();
 	if (outer_cache.disable)
 		outer_cache.disable();
-
-	__mmu_cache_flush();
 	__mmu_cache_off();
 }
 
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 97bb0db..3b19e9e 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -67,6 +67,7 @@ struct outer_cache_fns {
 	void (*inv_range)(unsigned long, unsigned long);
 	void (*clean_range)(unsigned long, unsigned long);
 	void (*flush_range)(unsigned long, unsigned long);
+	void (*flush_all)(void);
 	void (*disable)(void);
 };
 
-- 
2.4.6


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  parent reply	other threads:[~2015-08-07 13:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache Sascha Hauer
2015-08-07 13:35 ` Sascha Hauer [this message]
2015-08-07 13:35 ` [PATCH 3/5] ARM: l2x0: Implement L310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 4/5] ARM: l2x0: Add some informational debug messages Sascha Hauer
2015-08-07 13:35 ` [PATCH 5/5] ARM: i.MX6: Enable l2 cache Sascha Hauer

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