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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 3/5] ARM: l2x0: Implement L310 support
Date: Fri,  7 Aug 2015 15:35:43 +0200	[thread overview]
Message-ID: <1438954545-24917-4-git-send-email-s.hauer@pengutronix.de> (raw)
In-Reply-To: <1438954545-24917-1-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/cpu/cache-l2x0.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 43f296f..665f862 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -7,6 +7,7 @@
 #define CACHE_LINE_SIZE		32
 
 static void __iomem *l2x0_base;
+static uint32_t l2x0_way_mask; /* Bitmask of active ways */
 
 static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
@@ -50,8 +51,8 @@ static inline void l2x0_flush_line(unsigned long addr)
 static inline void l2x0_inv_all(void)
 {
 	/* invalidate all ways */
-	writel(0xff, l2x0_base + L2X0_INV_WAY);
-	cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
+	writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+	cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 	cache_sync();
 }
 
@@ -129,9 +130,37 @@ static void l2x0_disable(void)
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
 	__u32 aux;
+	__u32 cache_id;
+	int ways;
+	const char *type;
 
 	l2x0_base = base;
 
+	cache_id = readl(l2x0_base + L2X0_CACHE_ID);
+	aux = readl(l2x0_base + L2X0_AUX_CTRL);
+
+	/* Determine the number of ways */
+	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	case L2X0_CACHE_ID_PART_L310:
+		if (aux & (1 << 16))
+			ways = 16;
+		else
+			ways = 8;
+		type = "L310";
+		break;
+	case L2X0_CACHE_ID_PART_L210:
+		ways = (aux >> 13) & 0xf;
+		type = "L210";
+		break;
+	default:
+		/* Assume unknown chips have 8 ways */
+		ways = 8;
+		type = "L2x0 series";
+		break;
+	}
+
+       l2x0_way_mask = (1 << ways) - 1;
+
 	/*
 	 * Check if l2x0 controller is already enabled.
 	 * If you are booting from non-secure mode
-- 
2.4.6


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  parent reply	other threads:[~2015-08-07 13:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache Sascha Hauer
2015-08-07 13:35 ` [PATCH 2/5] ARM: l2x0: Flush cache before disabling it Sascha Hauer
2015-08-07 13:35 ` Sascha Hauer [this message]
2015-08-07 13:35 ` [PATCH 4/5] ARM: l2x0: Add some informational debug messages Sascha Hauer
2015-08-07 13:35 ` [PATCH 5/5] ARM: i.MX6: Enable l2 cache Sascha Hauer

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