* [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
@ 2015-08-07 13:35 ` Sascha Hauer
2015-08-07 13:35 ` [PATCH 2/5] ARM: l2x0: Flush cache before disabling it Sascha Hauer
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-08-07 13:35 UTC (permalink / raw)
To: Barebox List
When flushing the cache L1 has to be flushed before L2, not the
other way round.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 37bfa05..1bd6080 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -159,9 +159,9 @@ static u32 *find_pte(unsigned long adr)
static void dma_flush_range(unsigned long start, unsigned long end)
{
+ __dma_flush_range(start, end);
if (outer_cache.flush_range)
outer_cache.flush_range(start, end);
- __dma_flush_range(start, end);
}
static void dma_inv_range(unsigned long start, unsigned long end)
--
2.4.6
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/5] ARM: l2x0: Flush cache before disabling it
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache Sascha Hauer
@ 2015-08-07 13:35 ` Sascha Hauer
2015-08-07 13:35 ` [PATCH 3/5] ARM: l2x0: Implement L310 support Sascha Hauer
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-08-07 13:35 UTC (permalink / raw)
To: Barebox List
Otherwise entries may still be in the cache and never reach memory.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-l2x0.c | 13 ++++++++++++-
arch/arm/cpu/cache.c | 2 ++
arch/arm/cpu/cpu.c | 3 +--
arch/arm/include/asm/mmu.h | 1 +
4 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 2be562d..43f296f 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -112,6 +112,13 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
cache_sync();
}
+static void l2x0_flush_all(void)
+{
+ writel(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+ cache_wait(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
+ cache_sync();
+}
+
static void l2x0_disable(void)
{
writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
@@ -149,5 +156,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
outer_cache.clean_range = l2x0_clean_range;
outer_cache.flush_range = l2x0_flush_range;
outer_cache.disable = l2x0_disable;
-}
+ outer_cache.flush_all = l2x0_flush_all;
+ pr_debug("%s cache controller enabled\n", type);
+ pr_debug("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
+ ways, cache_id, aux);
+}
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 7b161d5..27ead1c 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -71,6 +71,8 @@ void __mmu_cache_flush(void)
{
if (cache_fns)
cache_fns->mmu_cache_flush();
+ if (outer_cache.flush_all)
+ outer_cache.flush_all();
}
int arm_set_cache_functions(void)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 5e70802..ff8f43d 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -79,10 +79,9 @@ struct outer_cache_fns outer_cache;
*/
void mmu_disable(void)
{
+ __mmu_cache_flush();
if (outer_cache.disable)
outer_cache.disable();
-
- __mmu_cache_flush();
__mmu_cache_off();
}
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 97bb0db..3b19e9e 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -67,6 +67,7 @@ struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
void (*flush_range)(unsigned long, unsigned long);
+ void (*flush_all)(void);
void (*disable)(void);
};
--
2.4.6
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 3/5] ARM: l2x0: Implement L310 support
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
2015-08-07 13:35 ` [PATCH 1/5] ARM: MMU: Fix order when flushing inner/outer cache Sascha Hauer
2015-08-07 13:35 ` [PATCH 2/5] ARM: l2x0: Flush cache before disabling it Sascha Hauer
@ 2015-08-07 13:35 ` Sascha Hauer
2015-08-07 13:35 ` [PATCH 4/5] ARM: l2x0: Add some informational debug messages Sascha Hauer
2015-08-07 13:35 ` [PATCH 5/5] ARM: i.MX6: Enable l2 cache Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-08-07 13:35 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-l2x0.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 43f296f..665f862 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -7,6 +7,7 @@
#define CACHE_LINE_SIZE 32
static void __iomem *l2x0_base;
+static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
@@ -50,8 +51,8 @@ static inline void l2x0_flush_line(unsigned long addr)
static inline void l2x0_inv_all(void)
{
/* invalidate all ways */
- writel(0xff, l2x0_base + L2X0_INV_WAY);
- cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
+ writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
}
@@ -129,9 +130,37 @@ static void l2x0_disable(void)
void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
__u32 aux;
+ __u32 cache_id;
+ int ways;
+ const char *type;
l2x0_base = base;
+ cache_id = readl(l2x0_base + L2X0_CACHE_ID);
+ aux = readl(l2x0_base + L2X0_AUX_CTRL);
+
+ /* Determine the number of ways */
+ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+ case L2X0_CACHE_ID_PART_L310:
+ if (aux & (1 << 16))
+ ways = 16;
+ else
+ ways = 8;
+ type = "L310";
+ break;
+ case L2X0_CACHE_ID_PART_L210:
+ ways = (aux >> 13) & 0xf;
+ type = "L210";
+ break;
+ default:
+ /* Assume unknown chips have 8 ways */
+ ways = 8;
+ type = "L2x0 series";
+ break;
+ }
+
+ l2x0_way_mask = (1 << ways) - 1;
+
/*
* Check if l2x0 controller is already enabled.
* If you are booting from non-secure mode
--
2.4.6
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 4/5] ARM: l2x0: Add some informational debug messages
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
` (2 preceding siblings ...)
2015-08-07 13:35 ` [PATCH 3/5] ARM: l2x0: Implement L310 support Sascha Hauer
@ 2015-08-07 13:35 ` Sascha Hauer
2015-08-07 13:35 ` [PATCH 5/5] ARM: i.MX6: Enable l2 cache Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-08-07 13:35 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-l2x0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 665f862..428dd93 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) "l2x0: " fmt
+
#include <common.h>
#include <init.h>
#include <io.h>
--
2.4.6
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 5/5] ARM: i.MX6: Enable l2 cache
2015-08-07 13:35 [PATCH] PL310 support Sascha Hauer
` (3 preceding siblings ...)
2015-08-07 13:35 ` [PATCH 4/5] ARM: l2x0: Add some informational debug messages Sascha Hauer
@ 2015-08-07 13:35 ` Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-08-07 13:35 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/imx6.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0de2d3e..92b5652 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -175,6 +175,7 @@ config ARCH_IMX53
config ARCH_IMX6
bool
+ select ARCH_HAS_L2X0
select ARCH_HAS_FEC_IMX
select CPU_V7
select PINCTRL_IMX_IOMUX_V3
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 7508964..ceabe19 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -22,6 +22,7 @@
#include <mach/imx6-anadig.h>
#include <mach/imx6-regs.h>
#include <mach/generic.h>
+#include <asm/mmu.h>
#define SI_REV 0x260
@@ -193,3 +194,37 @@ int imx6_devices_init(void)
return 0;
}
+
+#define L310_PREFETCH_CTRL 0xF60
+
+static int imx6_mmu_init(void)
+{
+ void __iomem *l2x0_base = IOMEM(0x00a02000);
+ u32 val;
+
+ if (!cpu_is_mx6())
+ return 0;
+
+ /* Configure the L2 PREFETCH and POWER registers */
+ val = readl(l2x0_base + L310_PREFETCH_CTRL);
+ val |= 0x70800000;
+
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+ if (cpu_is_mx6q())
+ val &= ~(1 << 30 | 1 << 23);
+
+ writel(val, l2x0_base + L310_PREFETCH_CTRL);
+
+ l2x0_init(l2x0_base, 0x0, ~0UL);
+
+ return 0;
+}
+postmmu_initcall(imx6_mmu_init);
--
2.4.6
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^ permalink raw reply [flat|nested] 6+ messages in thread