* [PATCH 0/3] misc MIPS patches @ 2015-09-20 22:50 Antony Pavlov 2015-09-20 22:50 ` [PATCH 1/3] MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant Antony Pavlov ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Antony Pavlov @ 2015-09-20 22:50 UTC (permalink / raw) To: barebox Antony Pavlov (3): MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant MIPS: PBL: Add missing pieces for xz compressed PBL image MIPS: refactor SPL start.S code arch/mips/boot/start.S | 108 ++---------------------- arch/mips/lib/Makefile | 2 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 + arch/mips/mach-ath79/include/mach/debug_ll.h | 5 +- arch/mips/pbl/.gitignore | 2 + arch/mips/pbl/Makefile | 1 + arch/mips/pbl/piggy.xzkern.S | 6 ++ 7 files changed, 23 insertions(+), 105 deletions(-) create mode 100644 arch/mips/pbl/piggy.xzkern.S -- 2.5.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant 2015-09-20 22:50 [PATCH 0/3] misc MIPS patches Antony Pavlov @ 2015-09-20 22:50 ` Antony Pavlov 2015-09-20 22:50 ` [PATCH 2/3] MIPS: PBL: Add missing pieces for xz compressed PBL image Antony Pavlov ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Antony Pavlov @ 2015-09-20 22:50 UTC (permalink / raw) To: barebox Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++++ arch/mips/mach-ath79/include/mach/debug_ll.h | 5 +---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 0c6ddd6..77138ab 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -15,7 +15,11 @@ #ifndef __ASM_MACH_AR71XX_REGS_H #define __ASM_MACH_AR71XX_REGS_H +#ifndef __ASSEMBLER__ #include <linux/bitops.h> +#else +#define BIT(nr) (1 << (nr)) +#endif #define AR71XX_APB_BASE 0x18000000 diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h index 64db674..d3813af 100644 --- a/arch/mips/mach-ath79/include/mach/debug_ll.h +++ b/arch/mips/mach-ath79/include/mach/debug_ll.h @@ -19,10 +19,7 @@ #define __AR933X_DEBUG_LL__ #include <asm/addrspace.h> - -/* Alas! <mach/ar71xx_regs.h> isn't assembly-tolerant */ -#define AR71XX_APB_BASE 0x18000000 -#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#include <mach/ar71xx_regs.h> #define DEBUG_LL_UART_ADDR KSEG1ADDR(AR933X_UART_BASE) -- 2.5.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] MIPS: PBL: Add missing pieces for xz compressed PBL image 2015-09-20 22:50 [PATCH 0/3] misc MIPS patches Antony Pavlov 2015-09-20 22:50 ` [PATCH 1/3] MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant Antony Pavlov @ 2015-09-20 22:50 ` Antony Pavlov 2015-09-20 22:50 ` [PATCH 3/3] MIPS: refactor SPL start.S code Antony Pavlov 2015-09-21 6:22 ` [PATCH 0/3] misc MIPS patches Sascha Hauer 3 siblings, 0 replies; 6+ messages in thread From: Antony Pavlov @ 2015-09-20 22:50 UTC (permalink / raw) To: barebox Also ignore piggy.shipped binary (CONFIG_IMAGE_COMPRESSION_NONE=y). Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> --- arch/mips/lib/Makefile | 2 ++ arch/mips/pbl/.gitignore | 2 ++ arch/mips/pbl/Makefile | 1 + arch/mips/pbl/piggy.xzkern.S | 6 ++++++ 4 files changed, 11 insertions(+) diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 71c4f6b..0145f35 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_CPU_MIPS64) += c-r4k.o obj-$(CONFIG_CMD_MIPS_CPUINFO) += cpuinfo.o obj-$(CONFIG_CMD_BOOTM) += bootm.o + +pbl-y += ashldi3.o diff --git a/arch/mips/pbl/.gitignore b/arch/mips/pbl/.gitignore index 1b7f618..be604a8 100644 --- a/arch/mips/pbl/.gitignore +++ b/arch/mips/pbl/.gitignore @@ -1,6 +1,8 @@ piggy.gzip piggy.lzo piggy.lz4 +piggy.xzkern +piggy.shipped zbarebox zbarebox.bin zbarebox.lds diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile index b03bca1..44ce3d1 100644 --- a/arch/mips/pbl/Makefile +++ b/arch/mips/pbl/Makefile @@ -2,6 +2,7 @@ suffix_$(CONFIG_IMAGE_COMPRESSION_GZIP) = gzip suffix_$(CONFIG_IMAGE_COMPRESSION_LZO) = lzo suffix_$(CONFIG_IMAGE_COMPRESSION_LZ4) = lz4 +suffix_$(CONFIG_IMAGE_COMPRESSION_XZKERN) = xzkern suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = shipped OBJCOPYFLAGS_zbarebox.bin = -O binary diff --git a/arch/mips/pbl/piggy.xzkern.S b/arch/mips/pbl/piggy.xzkern.S new file mode 100644 index 0000000..edfa53b --- /dev/null +++ b/arch/mips/pbl/piggy.xzkern.S @@ -0,0 +1,6 @@ +#include <asm/asm.h> + + .section .data +EXPORT(input_data) + .incbin "arch/mips/pbl/piggy.xzkern" +EXPORT(input_data_end) -- 2.5.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] MIPS: refactor SPL start.S code 2015-09-20 22:50 [PATCH 0/3] misc MIPS patches Antony Pavlov 2015-09-20 22:50 ` [PATCH 1/3] MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant Antony Pavlov 2015-09-20 22:50 ` [PATCH 2/3] MIPS: PBL: Add missing pieces for xz compressed PBL image Antony Pavlov @ 2015-09-20 22:50 ` Antony Pavlov 2015-09-21 6:22 ` [PATCH 0/3] misc MIPS patches Sascha Hauer 3 siblings, 0 replies; 6+ messages in thread From: Antony Pavlov @ 2015-09-20 22:50 UTC (permalink / raw) To: barebox This commit removes code duplication by using MIPS PBL macros in the SPL start.S file. One of the side effects of this patch is that the only <asm/pbl_macros.h> header file is depends on the <generated/utsrelease.h> header file. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> --- arch/mips/boot/start.S | 108 ++++--------------------------------------------- 1 file changed, 7 insertions(+), 101 deletions(-) diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S index 7e2ae5e..1ddce95 100644 --- a/arch/mips/boot/start.S +++ b/arch/mips/boot/start.S @@ -1,8 +1,7 @@ /* * Startup Code for MIPS CPU * - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com> - * Used code copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com> + * Copyright (C) 2011, 2015 Antony Pavlov <antonynpavlov@gmail.com> * * This file is part of barebox. * See file CREDITS for list of people who contributed to this project. @@ -18,32 +17,7 @@ * */ -#include <asm/regdef.h> -#include <asm/mipsregs.h> -#include <asm/asm.h> -#include <asm-generic/memory_layout.h> -#include <generated/compile.h> -#include <generated/utsrelease.h> - - /* - * ADR macro instruction (inspired by ARM) - * - * ARM architecture doesn't have PC-relative jump instruction - * like MIPS' B/BAL insns. When ARM makes PC-relative jumps, - * it uses ADR insn. ADR is used to get a destination address - * of 'label' against current PC. With this, ARM can safely - * make PC-relative jumps. - */ - .macro ADR rd label temp - .set push - .set noreorder - move \temp, ra # preserve ra beforehand - bal _pc - nop -_pc: addiu \rd, ra, \label - _pc # label is assumed to be - move ra, \temp # within pc +/- 32KB - .set pop - .endm +#include <asm/pbl_macros.h> .set noreorder .text @@ -52,91 +26,23 @@ _pc: addiu \rd, ra, \label - _pc # label is assumed to be EXPORT(_start) - b __start - nop + mips_barebox_10h - .org 0x10 - .ascii "barebox " UTS_RELEASE " " UTS_VERSION - .byte 0 - - .align 4 -__start: /* disable watchpoints */ mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* disable interrupts */ - mfc0 k0, CP0_STATUS - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS + mips_disable_interrupts - /* copy barebox to link location */ - ADR a0, _start, t1 /* a0 <- pc-relative position of _start */ + copy_to_link_location _start - la a1, _start /* link (RAM) _start address */ - - beq a0, a1, stack_setup - nop - - la t0, _start - la t1, __bss_start - subu t2, t1, t0 /* t2 <- size of barebox */ - addu a2, a0, t2 /* a2 <- source end address */ - -#define LONGSIZE 4 - -copy_loop: - /* copy from source address [a0] */ - lw t4, LONGSIZE * 0(a0) - lw t5, LONGSIZE * 1(a0) - lw t6, LONGSIZE * 2(a0) - lw t7, LONGSIZE * 3(a0) - /* copy fo target address [a1] */ - sw t4, LONGSIZE * 0(a1) - sw t5, LONGSIZE * 1(a1) - sw t6, LONGSIZE * 2(a1) - sw t7, LONGSIZE * 3(a1) - addi a0, LONGSIZE * 4 - subu t3, a0, a2 - blez t3, copy_loop - addi a1, LONGSIZE * 4 - - /* - * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006 - * - * 11.2.2 Stack Argument Structure in o32 - * ... - * At the point where a function is called, sp must be - * eight-byte-aligned, matching the alignment of the largest - * basic types -- a long long integer or a floating-point double. - * The eight-byte alignment is not required by 32-bit MIPS integer - * hardware, but it's essential for compatibility with CPUs with - * 64-bit registers, and thus part of the rules. Subroutines fit - * in with this by always adjusting the stack pointer by a multiple - * of eight. - * ... - * SGI's n32 and n64 standards call for the stack to be maintained - * with 16-byte alignment. - * - */ - -#if (STACK_BASE + STACK_SIZE) % 16 != 0 -#error stack pointer must be 16-byte-aligned -#endif - -stack_setup: - la sp, STACK_BASE + STACK_SIZE - - /* reserve four 32-bit argument slots */ - addiu sp, -16 + stack_setup la v0, main_entry - jal v0 + jal v0 nop /* No return */ - __error: b __error nop -- 2.5.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] misc MIPS patches 2015-09-20 22:50 [PATCH 0/3] misc MIPS patches Antony Pavlov ` (2 preceding siblings ...) 2015-09-20 22:50 ` [PATCH 3/3] MIPS: refactor SPL start.S code Antony Pavlov @ 2015-09-21 6:22 ` Sascha Hauer 2015-09-21 6:56 ` Antony Pavlov 3 siblings, 1 reply; 6+ messages in thread From: Sascha Hauer @ 2015-09-21 6:22 UTC (permalink / raw) To: Antony Pavlov; +Cc: barebox On Mon, Sep 21, 2015 at 01:50:42AM +0300, Antony Pavlov wrote: > Antony Pavlov (3): > MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant > MIPS: PBL: Add missing pieces for xz compressed PBL image > MIPS: refactor SPL start.S code Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] misc MIPS patches 2015-09-21 6:22 ` [PATCH 0/3] misc MIPS patches Sascha Hauer @ 2015-09-21 6:56 ` Antony Pavlov 0 siblings, 0 replies; 6+ messages in thread From: Antony Pavlov @ 2015-09-21 6:56 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On Mon, 21 Sep 2015 08:22:08 +0200 Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Mon, Sep 21, 2015 at 01:50:42AM +0300, Antony Pavlov wrote: > > Antony Pavlov (3): > > MIPS: mach-ath79: make ar71xx_regs.h assembler-tolerant > > MIPS: PBL: Add missing pieces for xz compressed PBL image Sorry, I have mistyped here: > > MIPS: refactor SPL start.S code ^^^ SPL -> SBL (Secondary Bootloader). > > Applied, thanks > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- -- Best regards, Antony Pavlov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
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