* [PATCH 0/4] New denali nand driver (ported from kernel)
@ 2015-09-21 14:04 Enrico Jorns
2015-09-21 14:04 ` [PATCH 1/4] mtd nand: added 'bits_per_cell' property Enrico Jorns
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Enrico Jorns @ 2015-09-21 14:04 UTC (permalink / raw)
To: barebox; +Cc: Enrico Jorns
This series adds the denali NAND driver that is used, for example,
on socfpga platforms.
The driver is adapted from the mainline kernel driver with some bugfix patches
from Altera.
Enrico Jorns (4):
mtd nand: added 'bits_per_cell' property
mtd nand_denali: Add denali nand driver
mtd denali: pass col argument to READID operation
socfpga dts: set have-hw-ecc-fixup for nand
arch/arm/dts/socfpga.dtsi | 1 +
drivers/mtd/nand/Kconfig | 26 +
drivers/mtd/nand/Makefile | 3 +
drivers/mtd/nand/denali.h | 499 ++++++++++++
drivers/mtd/nand/nand_base.c | 2 +
drivers/mtd/nand/nand_denali.c | 1559 +++++++++++++++++++++++++++++++++++++
drivers/mtd/nand/nand_denali_dt.c | 101 +++
include/linux/mtd/nand.h | 12 +
8 files changed, 2203 insertions(+)
create mode 100644 drivers/mtd/nand/denali.h
create mode 100644 drivers/mtd/nand/nand_denali.c
create mode 100644 drivers/mtd/nand/nand_denali_dt.c
--
2.5.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] mtd nand: added 'bits_per_cell' property
2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
@ 2015-09-21 14:04 ` Enrico Jorns
2015-09-21 14:04 ` [PATCH 2/4] mtd nand_denali: Add denali nand driver Enrico Jorns
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Enrico Jorns @ 2015-09-21 14:04 UTC (permalink / raw)
To: barebox; +Cc: Enrico Jorns
This one is available in the kernel and used by the denali driver
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
---
drivers/mtd/nand/nand_base.c | 2 ++
include/linux/mtd/nand.h | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index bf4110a..ca48f59 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2819,6 +2819,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
chip->chipsize = le32_to_cpu(p->blocks_per_lun);
chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
+ chip->bits_per_cell = p->bits_per_cell;
+
*busw = 0;
if (le16_to_cpu(p->features) & 1)
*busw = NAND_BUSWIDTH_16;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 3c7509f..f126cd9 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -430,6 +430,7 @@ struct nand_buffers {
* @badblockbits: [INTERN] minimum number of set bits in a good block's
* bad block marker position; i.e., BBM == 11110111b is
* not bad when badblockbits == 7
+ * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
* @cellinfo: [INTERN] MLC/multichip data from chip ident
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
@@ -506,6 +507,7 @@ struct nand_chip {
int pagebuf;
unsigned int pagebuf_bitflips;
int subpagesize;
+ uint8_t bits_per_cell;
uint8_t cellinfo;
int badblockpos;
int badblockbits;
@@ -722,4 +724,14 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
}
+/*
+ * Check if it is a SLC nand.
+ * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
+ * We do not distinguish the MLC and TLC now.
+ */
+static inline bool nand_is_slc(struct nand_chip *chip)
+{
+ return chip->bits_per_cell == 1;
+}
+
#endif /* __LINUX_MTD_NAND_H */
--
2.5.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/4] mtd nand_denali: Add denali nand driver
2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
2015-09-21 14:04 ` [PATCH 1/4] mtd nand: added 'bits_per_cell' property Enrico Jorns
@ 2015-09-21 14:04 ` Enrico Jorns
2015-09-21 14:04 ` [PATCH 3/4] mtd denali: pass col argument to READID operation Enrico Jorns
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Enrico Jorns @ 2015-09-21 14:04 UTC (permalink / raw)
To: barebox; +Cc: Enrico Jorns
The driver is based on the denali driver from the linux kernel
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
---
drivers/mtd/nand/Kconfig | 26 +
drivers/mtd/nand/Makefile | 3 +
drivers/mtd/nand/denali.h | 499 ++++++++++++
drivers/mtd/nand/nand_denali.c | 1559 +++++++++++++++++++++++++++++++++++++
drivers/mtd/nand/nand_denali_dt.c | 101 +++
5 files changed, 2188 insertions(+)
create mode 100644 drivers/mtd/nand/denali.h
create mode 100644 drivers/mtd/nand/nand_denali.c
create mode 100644 drivers/mtd/nand/nand_denali_dt.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a75540b..ff26584 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -140,4 +140,30 @@ config MTD_NAND_NOMADIK
help
Driver for the NAND flash controller on the Nomadik, with ECC.
+config MTD_NAND_DENALI
+ tristate "Support Denali NAND controller"
+ depends on HAS_DMA
+ help
+ Enable support for the Denali NAND controller. This should be
+ combined with either the PCI or platform drivers to provide device
+ registration.
+
+config MTD_NAND_DENALI_DT
+ tristate "Support Denali NAND controller as a DT device"
+ depends on HAVE_CLK && MTD_NAND_DENALI
+ help
+ Enable the driver for NAND flash on platforms using a Denali NAND
+ controller as a DT device.
+
+if MTD_NAND_DENALI
+
+config MTD_NAND_DENALI_TIMING_MODE
+ int "Overrides default ONFI timing mode."
+ default -1
+ range -1 5
+ help
+ -1 indicates use default timings
+
+endif
+
endif
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index a0b3198..8809238 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -16,3 +16,6 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
pbl-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
obj-$(CONFIG_NAND_MXS) += nand_mxs.o
+obj-$(CONFIG_MTD_NAND_DENALI) += nand_denali.o
+obj-$(CONFIG_MTD_NAND_DENALI_DT) += nand_denali_dt.o
+
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
new file mode 100644
index 0000000..f5511c9
--- /dev/null
+++ b/drivers/mtd/nand/denali.h
@@ -0,0 +1,499 @@
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DENALI_H__
+#define __DENALI_H__
+
+#include <linux/mtd/nand.h>
+
+#define DEVICE_RESET 0x0
+#define DEVICE_RESET__BANK0 0x0001
+#define DEVICE_RESET__BANK1 0x0002
+#define DEVICE_RESET__BANK2 0x0004
+#define DEVICE_RESET__BANK3 0x0008
+
+#define TRANSFER_SPARE_REG 0x10
+#define TRANSFER_SPARE_REG__FLAG 0x0001
+
+#define LOAD_WAIT_CNT 0x20
+#define LOAD_WAIT_CNT__VALUE 0xffff
+
+#define PROGRAM_WAIT_CNT 0x30
+#define PROGRAM_WAIT_CNT__VALUE 0xffff
+
+#define ERASE_WAIT_CNT 0x40
+#define ERASE_WAIT_CNT__VALUE 0xffff
+
+#define INT_MON_CYCCNT 0x50
+#define INT_MON_CYCCNT__VALUE 0xffff
+
+#define RB_PIN_ENABLED 0x60
+#define RB_PIN_ENABLED__BANK0 0x0001
+#define RB_PIN_ENABLED__BANK1 0x0002
+#define RB_PIN_ENABLED__BANK2 0x0004
+#define RB_PIN_ENABLED__BANK3 0x0008
+
+#define MULTIPLANE_OPERATION 0x70
+#define MULTIPLANE_OPERATION__FLAG 0x0001
+
+#define MULTIPLANE_READ_ENABLE 0x80
+#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
+
+#define COPYBACK_DISABLE 0x90
+#define COPYBACK_DISABLE__FLAG 0x0001
+
+#define CACHE_WRITE_ENABLE 0xa0
+#define CACHE_WRITE_ENABLE__FLAG 0x0001
+
+#define CACHE_READ_ENABLE 0xb0
+#define CACHE_READ_ENABLE__FLAG 0x0001
+
+#define PREFETCH_MODE 0xc0
+#define PREFETCH_MODE__PREFETCH_EN 0x0001
+#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
+
+#define CHIP_ENABLE_DONT_CARE 0xd0
+#define CHIP_EN_DONT_CARE__FLAG 0x01
+
+#define ECC_ENABLE 0xe0
+#define ECC_ENABLE__FLAG 0x0001
+
+#define GLOBAL_INT_ENABLE 0xf0
+#define GLOBAL_INT_EN_FLAG 0x01
+
+#define WE_2_RE 0x100
+#define WE_2_RE__VALUE 0x003f
+
+#define ADDR_2_DATA 0x110
+#define ADDR_2_DATA__VALUE 0x003f
+
+#define RE_2_WE 0x120
+#define RE_2_WE__VALUE 0x003f
+
+#define ACC_CLKS 0x130
+#define ACC_CLKS__VALUE 0x000f
+
+#define NUMBER_OF_PLANES 0x140
+#define NUMBER_OF_PLANES__VALUE 0x0007
+
+#define PAGES_PER_BLOCK 0x150
+#define PAGES_PER_BLOCK__VALUE 0xffff
+
+#define DEVICE_WIDTH 0x160
+#define DEVICE_WIDTH__VALUE 0x0003
+
+#define DEVICE_MAIN_AREA_SIZE 0x170
+#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
+
+#define DEVICE_SPARE_AREA_SIZE 0x180
+#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
+
+#define TWO_ROW_ADDR_CYCLES 0x190
+#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
+
+#define MULTIPLANE_ADDR_RESTRICT 0x1a0
+#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
+
+#define ECC_CORRECTION 0x1b0
+#define ECC_CORRECTION__VALUE 0x001f
+
+#define READ_MODE 0x1c0
+#define READ_MODE__VALUE 0x000f
+
+#define WRITE_MODE 0x1d0
+#define WRITE_MODE__VALUE 0x000f
+
+#define COPYBACK_MODE 0x1e0
+#define COPYBACK_MODE__VALUE 0x000f
+
+#define RDWR_EN_LO_CNT 0x1f0
+#define RDWR_EN_LO_CNT__VALUE 0x001f
+
+#define RDWR_EN_HI_CNT 0x200
+#define RDWR_EN_HI_CNT__VALUE 0x001f
+
+#define MAX_RD_DELAY 0x210
+#define MAX_RD_DELAY__VALUE 0x000f
+
+#define CS_SETUP_CNT 0x220
+#define CS_SETUP_CNT__VALUE 0x001f
+
+#define SPARE_AREA_SKIP_BYTES 0x230
+#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
+
+#define SPARE_AREA_MARKER 0x240
+#define SPARE_AREA_MARKER__VALUE 0xffff
+
+#define DEVICES_CONNECTED 0x250
+#define DEVICES_CONNECTED__VALUE 0x0007
+
+#define DIE_MASK 0x260
+#define DIE_MASK__VALUE 0x00ff
+
+#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
+#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
+
+#define WRITE_PROTECT 0x280
+#define WRITE_PROTECT__FLAG 0x0001
+
+#define RE_2_RE 0x290
+#define RE_2_RE__VALUE 0x003f
+
+#define MANUFACTURER_ID 0x300
+#define MANUFACTURER_ID__VALUE 0x00ff
+
+#define DEVICE_ID 0x310
+#define DEVICE_ID__VALUE 0x00ff
+
+#define DEVICE_PARAM_0 0x320
+#define DEVICE_PARAM_0__VALUE 0x00ff
+
+#define DEVICE_PARAM_1 0x330
+#define DEVICE_PARAM_1__VALUE 0x00ff
+
+#define DEVICE_PARAM_2 0x340
+#define DEVICE_PARAM_2__VALUE 0x00ff
+
+#define LOGICAL_PAGE_DATA_SIZE 0x350
+#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
+
+#define LOGICAL_PAGE_SPARE_SIZE 0x360
+#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
+
+#define REVISION 0x370
+#define REVISION__VALUE 0xffff
+
+#define ONFI_DEVICE_FEATURES 0x380
+#define ONFI_DEVICE_FEATURES__VALUE 0x003f
+
+#define ONFI_OPTIONAL_COMMANDS 0x390
+#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
+
+#define ONFI_TIMING_MODE 0x3a0
+#define ONFI_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
+#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
+
+#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
+#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
+#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
+
+#define FEATURES 0x3f0
+#define FEATURES__N_BANKS 0x0003
+#define FEATURES__ECC_MAX_ERR 0x003c
+#define FEATURES__DMA 0x0040
+#define FEATURES__CMD_DMA 0x0080
+#define FEATURES__PARTITION 0x0100
+#define FEATURES__XDMA_SIDEBAND 0x0200
+#define FEATURES__GPREG 0x0400
+#define FEATURES__INDEX_ADDR 0x0800
+
+#define TRANSFER_MODE 0x400
+#define TRANSFER_MODE__VALUE 0x0003
+
+#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
+#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
+
+/*
+ * Some versions of the IP have the ECC fixup handled in hardware. In this
+ * configuration we only get interrupted when the error is uncorrectable.
+ * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
+ * old IP.
+ * taken from patch by Jamie Iles <jamie at jamieiles.com>
+ * support hardware with internal ECC fixup
+ */
+#define INTR_STATUS__ECC_UNCOR_ERR 0x0001
+
+#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
+#define INTR_STATUS__ECC_ERR 0x0002
+#define INTR_STATUS__DMA_CMD_COMP 0x0004
+#define INTR_STATUS__TIME_OUT 0x0008
+#define INTR_STATUS__PROGRAM_FAIL 0x0010
+#define INTR_STATUS__ERASE_FAIL 0x0020
+#define INTR_STATUS__LOAD_COMP 0x0040
+#define INTR_STATUS__PROGRAM_COMP 0x0080
+#define INTR_STATUS__ERASE_COMP 0x0100
+#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_STATUS__LOCKED_BLK 0x0400
+#define INTR_STATUS__UNSUP_CMD 0x0800
+#define INTR_STATUS__INT_ACT 0x1000
+#define INTR_STATUS__RST_COMP 0x2000
+#define INTR_STATUS__PIPE_CMD_ERR 0x4000
+#define INTR_STATUS__PAGE_XFER_INC 0x8000
+
+#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
+#define INTR_EN__ECC_ERR 0x0002
+#define INTR_EN__DMA_CMD_COMP 0x0004
+#define INTR_EN__TIME_OUT 0x0008
+#define INTR_EN__PROGRAM_FAIL 0x0010
+#define INTR_EN__ERASE_FAIL 0x0020
+#define INTR_EN__LOAD_COMP 0x0040
+#define INTR_EN__PROGRAM_COMP 0x0080
+#define INTR_EN__ERASE_COMP 0x0100
+#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
+#define INTR_EN__LOCKED_BLK 0x0400
+#define INTR_EN__UNSUP_CMD 0x0800
+#define INTR_EN__INT_ACT 0x1000
+#define INTR_EN__RST_COMP 0x2000
+#define INTR_EN__PIPE_CMD_ERR 0x4000
+#define INTR_EN__PAGE_XFER_INC 0x8000
+
+#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
+#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
+#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
+
+#define DATA_INTR 0x550
+#define DATA_INTR__WRITE_SPACE_AV 0x0001
+#define DATA_INTR__READ_DATA_AV 0x0002
+
+#define DATA_INTR_EN 0x560
+#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
+#define DATA_INTR_EN__READ_DATA_AV 0x0002
+
+#define GPREG_0 0x570
+#define GPREG_0__VALUE 0xffff
+
+#define GPREG_1 0x580
+#define GPREG_1__VALUE 0xffff
+
+#define GPREG_2 0x590
+#define GPREG_2__VALUE 0xffff
+
+#define GPREG_3 0x5a0
+#define GPREG_3__VALUE 0xffff
+
+#define ECC_THRESHOLD 0x600
+#define ECC_THRESHOLD__VALUE 0x03ff
+
+#define ECC_ERROR_BLOCK_ADDRESS 0x610
+#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
+
+#define ECC_ERROR_PAGE_ADDRESS 0x620
+#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
+#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
+
+#define ECC_ERROR_ADDRESS 0x630
+#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
+#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
+
+#define ERR_CORRECTION_INFO 0x640
+#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
+#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
+#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
+#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
+
+#define DMA_ENABLE 0x700
+#define DMA_ENABLE__FLAG 0x0001
+
+#define IGNORE_ECC_DONE 0x710
+#define IGNORE_ECC_DONE__FLAG 0x0001
+
+#define DMA_INTR 0x720
+#define DMA_INTR__TARGET_ERROR 0x0001
+#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
+
+#define DMA_INTR_EN 0x730
+#define DMA_INTR_EN__TARGET_ERROR 0x0001
+#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
+#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
+#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
+#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
+#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
+
+#define TARGET_ERR_ADDR_LO 0x740
+#define TARGET_ERR_ADDR_LO__VALUE 0xffff
+
+#define TARGET_ERR_ADDR_HI 0x750
+#define TARGET_ERR_ADDR_HI__VALUE 0xffff
+
+#define CHNL_ACTIVE 0x760
+#define CHNL_ACTIVE__CHANNEL0 0x0001
+#define CHNL_ACTIVE__CHANNEL1 0x0002
+#define CHNL_ACTIVE__CHANNEL2 0x0004
+#define CHNL_ACTIVE__CHANNEL3 0x0008
+
+#define FLASH_BURST_LENGTH 0x770
+#define CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS 0X780
+#define NO_OF_BLOCKS_PER_LUN 0X790
+#define LUN_STATUS_CMD 0X7A0
+
+#define ACTIVE_SRC_ID 0x800
+#define ACTIVE_SRC_ID__VALUE 0x00ff
+
+#define PTN_INTR 0x810
+#define PTN_INTR__CONFIG_ERROR 0x0001
+#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR__REG_ACCESS_ERROR 0x0020
+
+#define PTN_INTR_EN 0x820
+#define PTN_INTR_EN__CONFIG_ERROR 0x0001
+#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
+#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
+#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
+#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
+#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
+
+#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
+#define PERM_SRC_ID__SRCID 0x00ff
+#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
+#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
+#define PERM_SRC_ID__READ_ACTIVE 0x4000
+#define PERM_SRC_ID__PARTITION_VALID 0x8000
+
+#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
+#define MIN_BLK_ADDR__VALUE 0xffff
+
+#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
+#define MAX_BLK_ADDR__VALUE 0xffff
+
+#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
+#define MIN_MAX_BANK__MIN_VALUE 0x0003
+#define MIN_MAX_BANK__MAX_VALUE 0x000c
+
+
+/* ffsdefs.h */
+#define CLEAR 0 /*use this to clear a field instead of "fail"*/
+#define SET 1 /*use this to set a field instead of "pass"*/
+#define FAIL 1 /*failed flag*/
+#define PASS 0 /*success flag*/
+#define ERR -1 /*error flag*/
+
+/* lld.h */
+#define GOOD_BLOCK 0
+#define DEFECTIVE_BLOCK 1
+#define READ_ERROR 2
+
+#define CLK_X 5
+#define CLK_MULTI 4
+
+/* spectraswconfig.h */
+#define CMD_DMA 0
+
+#define SPECTRA_PARTITION_ID 0
+/**** Block Table and Reserved Block Parameters *****/
+#define SPECTRA_START_BLOCK 3
+#define NUM_FREE_BLOCKS_GATE 30
+
+/* KBV - Updated to LNW scratch register address */
+#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
+#define SCRATCH_REG_SIZE 64
+
+#define GLOB_HWCTL_DEFAULT_BLKS 2048
+
+#define SUPPORT_15BITECC 1
+#define SUPPORT_8BITECC 1
+
+#define CUSTOM_CONF_PARAMS 0
+
+#define ONFI_BLOOM_TIME 1
+#define MODE5_WORKAROUND 0
+
+
+#define MODE_00 0x00000000
+#define MODE_01 0x04000000
+#define MODE_10 0x08000000
+#define MODE_11 0x0C000000
+
+
+#define DATA_TRANSFER_MODE 0
+#define PROTECTION_PER_BLOCK 1
+#define LOAD_WAIT_COUNT 2
+#define PROGRAM_WAIT_COUNT 3
+#define ERASE_WAIT_COUNT 4
+#define INT_MONITOR_CYCLE_COUNT 5
+#define READ_BUSY_PIN_ENABLED 6
+#define MULTIPLANE_OPERATION_SUPPORT 7
+#define PRE_FETCH_MODE 8
+#define CE_DONT_CARE_SUPPORT 9
+#define COPYBACK_SUPPORT 10
+#define CACHE_WRITE_SUPPORT 11
+#define CACHE_READ_SUPPORT 12
+#define NUM_PAGES_IN_BLOCK 13
+#define ECC_ENABLE_SELECT 14
+#define WRITE_ENABLE_2_READ_ENABLE 15
+#define ADDRESS_2_DATA 16
+#define READ_ENABLE_2_WRITE_ENABLE 17
+#define TWO_ROW_ADDRESS_CYCLES 18
+#define MULTIPLANE_ADDRESS_RESTRICT 19
+#define ACC_CLOCKS 20
+#define READ_WRITE_ENABLE_LOW_COUNT 21
+#define READ_WRITE_ENABLE_HIGH_COUNT 22
+
+#define ECC_SECTOR_SIZE 512
+
+struct nand_buf {
+ int head;
+ int tail;
+ uint8_t *buf;
+ dma_addr_t dma_buf;
+};
+
+#define INTEL_CE4100 1
+#define INTEL_MRST 2
+#define DT 3
+
+struct denali_nand_info {
+ struct mtd_info mtd;
+ struct nand_chip nand;
+ int flash_bank; /* currently selected chip */
+ int status;
+ int platform;
+ struct nand_buf buf;
+ struct device_d *dev;
+ int total_used_banks;
+ uint32_t block; /* stored for future use */
+ uint32_t page;
+ void __iomem *flash_reg; /* Mapped io reg base address */
+ void __iomem *flash_mem; /* Mapped io reg base address */
+
+ /* elements used by ISR */
+ //struct completion complete;
+ spinlock_t irq_lock;
+ uint32_t irq_status;
+ int irq_debug_array[32];
+ int idx;
+ int irq;
+
+ uint32_t devnum; /* represent how many nands connected */
+ uint32_t fwblks; /* represent how many blocks FW used */
+ uint32_t totalblks;
+ uint32_t blksperchip;
+ uint32_t bbtskipbytes;
+ uint32_t max_banks;
+ bool have_hw_ecc_fixup;
+};
+
+extern int denali_init(struct denali_nand_info *denali);
+extern void denali_remove(struct denali_nand_info *denali);
+
+#endif /* __DENALI_H__ */
diff --git a/drivers/mtd/nand/nand_denali.c b/drivers/mtd/nand/nand_denali.c
new file mode 100644
index 0000000..f2d9cb7
--- /dev/null
+++ b/drivers/mtd/nand/nand_denali.c
@@ -0,0 +1,1559 @@
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright © 2009-2010, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <common.h>
+#include <dma.h>
+#include <driver.h>
+#include <malloc.h>
+#include <init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <mach/generic.h>
+#include <io.h>
+#include <of_mtd.h>
+#include <errno.h>
+#include <asm/io.h>
+#include "denali.h"
+
+#define NAND_DEFAULT_TIMINGS -1
+
+static int onfi_timing_mode = CONFIG_MTD_NAND_DENALI_TIMING_MODE;
+
+#define DENALI_NAND_NAME "denali-nand"
+
+/*
+ * We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience.
+ */
+#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
+ INTR_STATUS__ECC_TRANSACTION_DONE | \
+ INTR_STATUS__ECC_ERR | \
+ INTR_STATUS__PROGRAM_FAIL | \
+ INTR_STATUS__LOAD_COMP | \
+ INTR_STATUS__PROGRAM_COMP | \
+ INTR_STATUS__TIME_OUT | \
+ INTR_STATUS__ERASE_FAIL | \
+ INTR_STATUS__RST_COMP | \
+ INTR_STATUS__ERASE_COMP | \
+ INTR_STATUS__ECC_UNCOR_ERR)
+/* And here we use a variable for interrupt mask, bcs we want to
+ * change the irq mask during init. That is, we want to enable R/B
+ * interrupt during init, but not at other times */
+static uint32_t denali_irq_mask = DENALI_IRQ_ALL;
+
+
+/*
+ * indicates whether or not the internal value for the flash bank is
+ * valid or not
+ */
+#define CHIP_SELECT_INVALID -1
+
+#define SUPPORT_8BITECC 1
+
+/*
+ * This macro divides two integers and rounds fractional values up
+ * to the nearest integer value.
+ */
+#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
+
+/*
+ * this macro allows us to convert from an MTD structure to our own
+ * device context (denali) structure.
+ */
+#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
+
+/*
+ * These constants are defined by the driver to enable common driver
+ * configuration options.
+ */
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS 0x42
+#define MAIN_SPARE_ACCESS 0x43
+#define PIPELINE_ACCESS 0x2000
+
+#define DENALI_READ 0
+#define DENALI_WRITE 0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE 0
+#define ADDR_CYCLE 1
+#define STATUS_CYCLE 2
+
+/*
+ * this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller
+ */
+#define BANK(x) ((x) << 24)
+
+/* forward declarations */
+static void clear_interrupts(struct denali_nand_info *denali);
+static uint32_t wait_for_irq(struct denali_nand_info *denali,
+ uint32_t irq_mask);
+static void denali_irq_enable(struct denali_nand_info *denali,
+ uint32_t int_mask);
+static uint32_t read_interrupt_status(struct denali_nand_info *denali);
+
+/*
+ * Certain operations for the denali NAND controller use an indexed mode to
+ * read/write data. The operation is performed by writing the address value
+ * of the command to the device memory followed by the data. This function
+ * abstracts this common operation.
+ */
+static void index_addr(struct denali_nand_info *denali,
+ uint32_t address, uint32_t data)
+{
+ iowrite32(address, denali->flash_mem);
+ iowrite32(data, denali->flash_mem + 0x10);
+}
+
+/* Perform an indexed read of the device */
+static void index_addr_read_data(struct denali_nand_info *denali,
+ uint32_t address, uint32_t *pdata)
+{
+ iowrite32(address, denali->flash_mem);
+ *pdata = ioread32(denali->flash_mem + 0x10);
+}
+
+/*
+ * We need to buffer some data for some of the NAND core routines.
+ * The operations manage buffering that data.
+ */
+static void reset_buf(struct denali_nand_info *denali)
+{
+ denali->buf.head = denali->buf.tail = 0;
+}
+
+static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
+{
+ denali->buf.buf[denali->buf.tail++] = byte;
+}
+
+/* reads the status of the device */
+static void read_status(struct denali_nand_info *denali)
+{
+ uint32_t cmd;
+
+ /* initialize the data buffer to store status */
+ reset_buf(denali);
+
+ cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
+ if (cmd)
+ write_byte_to_buf(denali, NAND_STATUS_WP);
+ else
+ write_byte_to_buf(denali, 0);
+}
+
+/* resets a specific device connected to the core */
+static void reset_bank(struct denali_nand_info *denali)
+{
+ iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
+
+ /* wait for completion */
+ while (ioread32(denali->flash_reg + DEVICE_RESET) & (1 << denali->flash_bank))
+ barrier();
+}
+
+/* Reset the flash controller */
+static uint16_t denali_nand_reset(struct denali_nand_info *denali)
+{
+ int i;
+
+ dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
+ __FILE__, __LINE__, __func__);
+
+ for (i = 0; i < denali->max_banks; i++)
+ iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+ denali->flash_reg + INTR_STATUS(i));
+
+ for (i = 0; i < denali->max_banks; i++) {
+ iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
+ while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
+ (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
+ /* cpu_relax(); */
+ barrier();
+ if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
+ INTR_STATUS__TIME_OUT)
+ dev_dbg(denali->dev,
+ "NAND Reset operation timed out on bank %d\n", i);
+ }
+
+ for (i = 0; i < denali->max_banks; i++)
+ iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+ denali->flash_reg + INTR_STATUS(i));
+
+ return PASS;
+}
+
+/*
+ * this routine calculates the ONFI timing values for a given mode and
+ * programs the clocking register accordingly. The mode is determined by
+ * the get_onfi_nand_para routine.
+ */
+static void nand_onfi_timing_set(struct denali_nand_info *denali,
+ uint16_t mode)
+{
+ uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
+ uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
+ uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
+ uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
+ uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
+ uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
+ uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
+ uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
+ uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
+ uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
+ uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
+ uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
+
+ uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
+ uint16_t dv_window = 0;
+ uint16_t en_lo, en_hi;
+ uint16_t acc_clks;
+ uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
+
+ dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
+ __FILE__, __LINE__, __func__);
+
+ en_lo = CEIL_DIV(Trp[mode], CLK_X);
+ en_hi = CEIL_DIV(Treh[mode], CLK_X);
+#if ONFI_BLOOM_TIME
+ if ((en_hi * CLK_X) < (Treh[mode] + 2))
+ en_hi++;
+#endif
+
+ if ((en_lo + en_hi) * CLK_X < Trc[mode])
+ en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
+
+ if ((en_lo + en_hi) < CLK_MULTI)
+ en_lo += CLK_MULTI - en_lo - en_hi;
+
+ while (dv_window < 8) {
+ data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
+
+ data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
+
+ data_invalid = data_invalid_rhoh < data_invalid_rloh ?
+ data_invalid_rhoh : data_invalid_rloh;
+
+ dv_window = data_invalid - Trea[mode];
+
+ if (dv_window < 8)
+ en_lo++;
+ }
+
+ acc_clks = CEIL_DIV(Trea[mode], CLK_X);
+
+ while (acc_clks * CLK_X - Trea[mode] < 3)
+ acc_clks++;
+
+ if (data_invalid - acc_clks * CLK_X < 2)
+ dev_warn(denali->dev, "%s, Line %d: Warning!\n",
+ __FILE__, __LINE__);
+
+ addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
+ re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
+ re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
+ we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
+ cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
+ if (cs_cnt == 0)
+ cs_cnt = 1;
+
+ if (Tcea[mode]) {
+ while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
+ cs_cnt++;
+ }
+
+#if MODE5_WORKAROUND
+ if (mode == 5)
+ acc_clks = 5;
+#endif
+
+ /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
+ if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
+ ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
+ acc_clks = 6;
+
+ iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
+ iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
+ iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
+ iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
+ iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
+ iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
+ iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
+ iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
+}
+
+/* queries the NAND device to see what ONFI modes it supports. */
+static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
+{
+ int i;
+
+ /*
+ * we needn't to do a reset here because driver has already
+ * reset all the banks before
+ */
+ if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
+ ONFI_TIMING_MODE__VALUE))
+ return FAIL;
+
+ for (i = 5; i > 0; i--) {
+ if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
+ (0x01 << i))
+ break;
+ }
+
+ nand_onfi_timing_set(denali, i);
+
+ /*
+ * By now, all the ONFI devices we know support the page cache
+ * rw feature. So here we enable the pipeline_rw_ahead feature
+ */
+ /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
+ /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
+
+ return PASS;
+}
+
+static void get_samsung_nand_para(struct denali_nand_info *denali,
+ uint8_t device_id)
+{
+ if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
+ /* Set timing register values according to datasheet */
+ iowrite32(5, denali->flash_reg + ACC_CLKS);
+ iowrite32(20, denali->flash_reg + RE_2_WE);
+ iowrite32(12, denali->flash_reg + WE_2_RE);
+ iowrite32(14, denali->flash_reg + ADDR_2_DATA);
+ iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
+ iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
+ iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
+ }
+}
+
+static void get_toshiba_nand_para(struct denali_nand_info *denali)
+{
+ uint32_t tmp;
+
+ /*
+ * Workaround to fix a controller bug which reports a wrong
+ * spare area size for some kind of Toshiba NAND device
+ */
+ if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
+ (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
+ iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
+ ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ iowrite32(tmp,
+ denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+#if SUPPORT_15BITECC
+ iowrite32(15, denali->flash_reg + ECC_CORRECTION);
+#elif SUPPORT_8BITECC
+ iowrite32(8, denali->flash_reg + ECC_CORRECTION);
+#endif
+ }
+}
+
+static void get_hynix_nand_para(struct denali_nand_info *denali,
+ uint8_t device_id)
+{
+ uint32_t main_size, spare_size;
+
+ switch (device_id) {
+ case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
+ case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
+ iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
+ iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
+ iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+ main_size = 4096 *
+ ioread32(denali->flash_reg + DEVICES_CONNECTED);
+ spare_size = 224 *
+ ioread32(denali->flash_reg + DEVICES_CONNECTED);
+ iowrite32(main_size,
+ denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
+ iowrite32(spare_size,
+ denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+ iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
+#if SUPPORT_15BITECC
+ iowrite32(15, denali->flash_reg + ECC_CORRECTION);
+#elif SUPPORT_8BITECC
+ iowrite32(8, denali->flash_reg + ECC_CORRECTION);
+#endif
+ break;
+ default:
+ dev_warn(denali->dev,
+ "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
+ "Will use default parameter values instead.\n",
+ device_id);
+ }
+}
+
+/*
+ * determines how many NAND chips are connected to the controller. Note for
+ * Intel CE4100 devices we don't support more than one device.
+ */
+static void find_valid_banks(struct denali_nand_info *denali)
+{
+ uint32_t id[denali->max_banks];
+ int i;
+
+ denali->total_used_banks = 1;
+ for (i = 0; i < denali->max_banks; i++) {
+ index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
+ index_addr(denali, MODE_11 | (i << 24) | 1, 0);
+ index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
+
+ dev_dbg(denali->dev,
+ "Return 1st ID for bank[%d]: %x\n", i, id[i]);
+
+ if (i == 0) {
+ if (!(id[i] & 0x0ff))
+ break; /* WTF? */
+ } else {
+ if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
+ denali->total_used_banks++;
+ else
+ break;
+ }
+ }
+
+ if (denali->platform == INTEL_CE4100) {
+ /*
+ * Platform limitations of the CE4100 device limit
+ * users to a single chip solution for NAND.
+ * Multichip support is not enabled.
+ */
+ if (denali->total_used_banks != 1) {
+ dev_err(denali->dev,
+ "Sorry, Intel CE4100 only supports a single NAND device.\n");
+ BUG();
+ }
+ }
+ dev_dbg(denali->dev,
+ "denali->total_used_banks: %d\n", denali->total_used_banks);
+}
+
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void detect_max_banks(struct denali_nand_info *denali)
+{
+ uint32_t features = ioread32(denali->flash_reg + FEATURES);
+
+ denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+}
+
+static void detect_partition_feature(struct denali_nand_info *denali)
+{
+ /*
+ * For MRST platform, denali->fwblks represent the
+ * number of blocks firmware is taken,
+ * FW is in protect partition and MTD driver has no
+ * permission to access it. So let driver know how many
+ * blocks it can't touch.
+ */
+ if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
+ if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
+ PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
+ denali->fwblks =
+ ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
+ MIN_MAX_BANK__MIN_VALUE) *
+ denali->blksperchip)
+ +
+ (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
+ MIN_BLK_ADDR__VALUE);
+ } else {
+ denali->fwblks = SPECTRA_START_BLOCK;
+ }
+ } else {
+ denali->fwblks = SPECTRA_START_BLOCK;
+ }
+}
+
+static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
+{
+ uint16_t status = PASS;
+ uint32_t id_bytes[8], addr;
+ uint8_t maf_id, device_id;
+ int i;
+
+ dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
+ __FILE__, __LINE__, __func__);
+
+ /*
+ * Use read id method to get device ID and other params.
+ * For some NAND chips, controller can't report the correct
+ * device ID by reading from DEVICE_ID register
+ */
+ addr = MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, 0x90);
+ index_addr(denali, addr | 1, 0);
+ for (i = 0; i < 8; i++)
+ index_addr_read_data(denali, addr | 2, &id_bytes[i]);
+ maf_id = id_bytes[0];
+ device_id = id_bytes[1];
+
+ if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
+ ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
+ if (FAIL == get_onfi_nand_para(denali))
+ return FAIL;
+ } else if (maf_id == 0xEC) { /* Samsung NAND */
+ get_samsung_nand_para(denali, device_id);
+ } else if (maf_id == 0x98) { /* Toshiba NAND */
+ get_toshiba_nand_para(denali);
+ } else if (maf_id == 0xAD) { /* Hynix NAND */
+ get_hynix_nand_para(denali, device_id);
+ }
+
+ dev_info(denali->dev,
+ "Dump timing register values:\n"
+ "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
+ "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
+ "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
+ ioread32(denali->flash_reg + ACC_CLKS),
+ ioread32(denali->flash_reg + RE_2_WE),
+ ioread32(denali->flash_reg + RE_2_RE),
+ ioread32(denali->flash_reg + WE_2_RE),
+ ioread32(denali->flash_reg + ADDR_2_DATA),
+ ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
+ ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
+ ioread32(denali->flash_reg + CS_SETUP_CNT));
+
+ find_valid_banks(denali);
+
+ detect_partition_feature(denali);
+
+ /*
+ * If the user specified to override the default timings
+ * with a specific ONFI mode, we apply those changes here.
+ */
+ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
+ nand_onfi_timing_set(denali, onfi_timing_mode);
+
+ return status;
+}
+
+static void denali_set_intr_modes(struct denali_nand_info *denali,
+ uint16_t INT_ENABLE)
+{
+ dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
+ __FILE__, __LINE__, __func__);
+
+ if (INT_ENABLE)
+ iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
+ else
+ iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
+}
+
+/*
+ * validation function to verify that the controlling software is making
+ * a valid request
+ */
+static inline bool is_flash_bank_valid(int flash_bank)
+{
+ return flash_bank >= 0 && flash_bank < 4;
+}
+
+
+static void denali_irq_init(struct denali_nand_info *denali)
+{
+ uint32_t int_mask;
+ int i;
+
+ /* Disable global interrupts */
+ denali_set_intr_modes(denali, false);
+
+ int_mask = DENALI_IRQ_ALL;
+
+ /* Clear all status bits */
+ for (i = 0; i < denali->max_banks; ++i)
+ iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
+
+ denali_irq_enable(denali, int_mask);
+}
+
+
+static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
+{
+ denali_set_intr_modes(denali, false);
+}
+
+static void denali_irq_enable(struct denali_nand_info *denali,
+ uint32_t int_mask)
+{
+ int i;
+
+ for (i = 0; i < denali->max_banks; ++i)
+ iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
+}
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(struct denali_nand_info *denali,
+ uint32_t irq_mask)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+ iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(struct denali_nand_info *denali)
+{
+ uint32_t status;
+
+ status = read_interrupt_status(denali);
+ clear_interrupt(denali, status);
+
+ denali->irq_status = 0x0;
+}
+
+static uint32_t read_interrupt_status(struct denali_nand_info *denali)
+{
+ uint32_t intr_status_reg;
+
+ intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+ return ioread32(denali->flash_reg + intr_status_reg);
+}
+
+static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
+{
+ unsigned long comp_res = 1000;
+ uint32_t intr_status = 0;
+
+ do {
+ intr_status = read_interrupt_status(denali);
+ if (intr_status & irq_mask) {
+ /* our interrupt was detected */
+ break;
+ }
+ udelay(1);
+ comp_res--;
+ } while (comp_res != 0);
+
+ if (comp_res == 0) {
+ /* timeout */
+ intr_status = 0;
+ dev_dbg(denali->dev, "timeout occurred, status = 0x%x, mask = 0x%x\n",
+ intr_status, irq_mask);
+ }
+ return intr_status;
+}
+
+/*
+ * This helper function setups the registers for ECC and whether or not
+ * the spare area will be transferred.
+ */
+static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
+ bool transfer_spare)
+{
+ int ecc_en_flag, transfer_spare_flag;
+
+ /* set ECC, transfer spare bits if needed */
+ ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
+ transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
+
+ /* Enable spare area/ECC per user's request. */
+ iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
+ iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
+}
+
+/*
+ * sends a pipeline command operation to the controller. See the Denali NAND
+ * controller's user guide for more information (section 4.2.3.6).
+ */
+static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
+ bool ecc_en, bool transfer_spare,
+ int access_type, int op)
+{
+ int status = PASS;
+ uint32_t page_count = 1;
+ uint32_t addr, cmd, irq_status, irq_mask;
+
+ if (op == DENALI_READ)
+ irq_mask = INTR_STATUS__LOAD_COMP;
+ else if (op == DENALI_WRITE)
+ irq_mask = 0;
+ else
+ BUG();
+
+ setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
+
+ clear_interrupts(denali);
+
+ addr = BANK(denali->flash_bank) | denali->page;
+
+ if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
+ cmd = MODE_01 | addr;
+ iowrite32(cmd, denali->flash_mem);
+ } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
+ /* read spare area */
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, access_type);
+
+ cmd = MODE_01 | addr;
+ iowrite32(cmd, denali->flash_mem);
+ } else if (op == DENALI_READ) {
+ /* setup page read request for access type */
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, access_type);
+
+ /*
+ * page 33 of the NAND controller spec indicates we should not
+ * use the pipeline commands in Spare area only mode.
+ * So we don't.
+ */
+ if (access_type == SPARE_ACCESS) {
+ cmd = MODE_01 | addr;
+ iowrite32(cmd, denali->flash_mem);
+ } else {
+ index_addr(denali, cmd,
+ PIPELINE_ACCESS | op | page_count);
+
+ /*
+ * wait for command to be accepted
+ * can always use status0 bit as the
+ * mask is identical for each bank.
+ */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0) {
+ dev_err(denali->dev,
+ "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
+ cmd, denali->page, addr);
+ status = FAIL;
+ } else {
+ cmd = MODE_01 | addr;
+ iowrite32(cmd, denali->flash_mem);
+ }
+ }
+ }
+ return status;
+}
+
+/* helper function that simply writes a buffer to the flash */
+static int write_data_to_flash_mem(struct denali_nand_info *denali,
+ const uint8_t *buf, int len)
+{
+ uint32_t *buf32;
+ int i;
+
+ /*
+ * verify that the len is a multiple of 4.
+ * see comment in read_data_from_flash_mem()
+ */
+ BUG_ON((len % 4) != 0);
+
+ /* write the data to the flash memory */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i < len / 4; i++)
+ iowrite32(*buf32++, denali->flash_mem + 0x10);
+ return i * 4; /* intent is to return the number of bytes read */
+}
+
+/* helper function that simply reads a buffer from the flash */
+static int read_data_from_flash_mem(struct denali_nand_info *denali,
+ uint8_t *buf, int len)
+{
+ uint32_t *buf32;
+ int i;
+
+ /*
+ * we assume that len will be a multiple of 4, if not it would be nice
+ * to know about it ASAP rather than have random failures...
+ * This assumption is based on the fact that this function is designed
+ * to be used to read flash pages, which are typically multiples of 4.
+ */
+ BUG_ON((len % 4) != 0);
+
+ /* transfer the data from the flash */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i < len / 4; i++)
+ *buf32++ = ioread32(denali->flash_mem + 0x10);
+ return i * 4; /* intent is to return the number of bytes read */
+}
+
+/* writes OOB data to the device */
+static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_status;
+ uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
+ INTR_STATUS__PROGRAM_FAIL;
+ int status = 0;
+
+ denali->page = page;
+
+ if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
+ DENALI_WRITE) == PASS) {
+ write_data_to_flash_mem(denali, buf, mtd->oobsize);
+
+ /* wait for operation to complete */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0) {
+ dev_err(denali->dev, "OOB write failed\n");
+ status = -EIO;
+ }
+
+ /* set the device back to MAIN_ACCESS */
+ {
+ uint32_t addr;
+ uint32_t cmd;
+ addr = BANK(denali->flash_bank) | denali->page;
+ cmd = MODE_10 | addr;
+ index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
+ }
+
+ } else {
+ dev_err(denali->dev, "unable to send pipeline command\n");
+ status = -EIO;
+ }
+ return status;
+}
+
+/* reads OOB data from the device */
+static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
+ uint32_t irq_status, addr, cmd;
+
+ denali->page = page;
+
+ if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
+ DENALI_READ) == PASS) {
+ read_data_from_flash_mem(denali, buf, mtd->oobsize);
+
+ /*
+ * wait for command to be accepted
+ * can always use status0 bit as the
+ * mask is identical for each bank.
+ */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0)
+ dev_err(denali->dev, "page on OOB timeout %d\n",
+ denali->page);
+
+ /*
+ * We set the device back to MAIN_ACCESS here as I observed
+ * instability with the controller if you do a block erase
+ * and the last transaction was a SPARE_ACCESS. Block erase
+ * is reliable (according to the MTD test infrastructure)
+ * if you are in MAIN_ACCESS.
+ */
+ addr = BANK(denali->flash_bank) | denali->page;
+ cmd = MODE_10 | addr;
+ index_addr(denali, cmd, MAIN_ACCESS);
+ }
+}
+
+/*
+ * this function examines buffers to see if they contain data that
+ * indicate that the buffer is part of an erased region of flash.
+ */
+static bool is_erased(uint8_t *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ if (buf[i] != 0xFF)
+ return false;
+ return true;
+}
+#define ECC_SECTOR_SIZE 512
+
+#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
+#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
+#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
+#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
+#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
+#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
+
+static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
+ uint32_t irq_status, unsigned int *max_bitflips)
+{
+ bool check_erased_page = false;
+ unsigned int bitflips = 0;
+
+ if (denali->have_hw_ecc_fixup &&
+ (irq_status & INTR_STATUS__ECC_UNCOR_ERR)) {
+ clear_interrupts(denali);
+ denali_set_intr_modes(denali, true);
+ check_erased_page = true;
+ } else if (irq_status & INTR_STATUS__ECC_ERR) {
+ /* read the ECC errors. we'll ignore them for now */
+ uint32_t err_address, err_correction_info, err_byte,
+ err_sector, err_device, err_correction_value;
+ denali_set_intr_modes(denali, false);
+
+ do {
+ err_address = ioread32(denali->flash_reg +
+ ECC_ERROR_ADDRESS);
+ err_sector = ECC_SECTOR(err_address);
+ err_byte = ECC_BYTE(err_address);
+
+ err_correction_info = ioread32(denali->flash_reg +
+ ERR_CORRECTION_INFO);
+ err_correction_value =
+ ECC_CORRECTION_VALUE(err_correction_info);
+ err_device = ECC_ERR_DEVICE(err_correction_info);
+
+ if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
+ /*
+ * If err_byte is larger than ECC_SECTOR_SIZE,
+ * means error happened in OOB, so we ignore
+ * it. It's no need for us to correct it
+ * err_device is represented the NAND error
+ * bits are happened in if there are more
+ * than one NAND connected.
+ */
+ if (err_byte < ECC_SECTOR_SIZE) {
+ int offset;
+
+ offset = (err_sector *
+ ECC_SECTOR_SIZE +
+ err_byte) *
+ denali->devnum +
+ err_device;
+ /* correct the ECC error */
+ buf[offset] ^= err_correction_value;
+ denali->mtd.ecc_stats.corrected++;
+ bitflips++;
+ }
+ } else {
+ /*
+ * if the error is not correctable, need to
+ * look at the page to see if it is an erased
+ * page. if so, then it's not a real ECC error
+ */
+ check_erased_page = true;
+ }
+ } while (!ECC_LAST_ERR(err_correction_info));
+ /*
+ * Once handle all ecc errors, controller will trigger
+ * a ECC_TRANSACTION_DONE interrupt, so here just wait
+ * for a while for this interrupt
+ */
+ while (!(read_interrupt_status(denali) &
+ INTR_STATUS__ECC_TRANSACTION_DONE))
+ /* cpu_relax(); */
+ barrier();
+ clear_interrupts(denali);
+ denali_set_intr_modes(denali, true);
+ }
+ *max_bitflips = bitflips;
+ return check_erased_page;
+}
+
+/* programs the controller to either enable/disable DMA transfers */
+static void denali_enable_dma(struct denali_nand_info *denali, bool en)
+{
+ iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
+ ioread32(denali->flash_reg + DMA_ENABLE);
+}
+
+/* setups the HW to perform the data DMA */
+static void denali_setup_dma(struct denali_nand_info *denali, int op)
+{
+ uint32_t mode;
+ const int page_count = 1;
+ uint32_t addr = (unsigned long)denali->buf.buf;
+
+ mode = MODE_10 | BANK(denali->flash_bank);
+
+ /* DMA is a four step process */
+
+ /* 1. setup transfer type and # of pages */
+ index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
+
+ /* 2. set memory high address bits 23:8 */
+ index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
+
+ /* 3. set memory low address bits 23:8 */
+ index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
+
+ /* 4. interrupt when complete, burst len = 64 bytes */
+ index_addr(denali, mode | 0x14000, 0x2400);
+}
+
+/*
+ * writes a page. user specifies type, and this function handles the
+ * configuration details.
+ */
+static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, bool raw_xfer)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ dma_addr_t addr = (unsigned long)denali->buf.buf;
+ size_t size = denali->mtd.writesize + denali->mtd.oobsize;
+ uint32_t irq_status;
+ uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
+ INTR_STATUS__PROGRAM_FAIL;
+
+ /*
+ * if it is a raw xfer, we want to disable ecc and send the spare area.
+ * !raw_xfer - enable ecc
+ * raw_xfer - transfer spare
+ */
+ setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
+
+ /* copy buffer into DMA buffer */
+ memcpy(denali->buf.buf, buf, mtd->writesize);
+
+ if (raw_xfer) {
+ /* transfer the data to the spare area */
+ memcpy(denali->buf.buf + mtd->writesize,
+ chip->oob_poi,
+ mtd->oobsize);
+ }
+
+ dma_sync_single_for_device(addr, size, DMA_TO_DEVICE);
+
+ clear_interrupts(denali);
+ denali_enable_dma(denali, true);
+
+ denali_setup_dma(denali, DENALI_WRITE);
+
+ /* wait for operation to complete */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ if (irq_status == 0) {
+ dev_err(denali->dev, "timeout on write_page (type = %d)\n",
+ raw_xfer);
+ denali->status = NAND_STATUS_FAIL;
+ }
+
+ denali_enable_dma(denali, false);
+ dma_sync_single_for_cpu(addr, size, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+/* NAND core entry points */
+
+/*
+ * this is the callback that the NAND core calls to write a page. Since
+ * writing a page with ECC or without is similar, all the work is done
+ * by write_page above.
+ */
+static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ /*
+ * for regular page writes, we let HW handle all the ECC
+ * data written to the device.
+ */
+ return write_page(mtd, chip, buf, false);
+}
+
+/*
+ * This is the callback that the NAND core calls to write a page without ECC.
+ * raw access is similar to ECC page writes, so all the work is done in the
+ * write_page() function above.
+ */
+static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+{
+ /*
+ * for raw page writes, we want to disable ECC and simply write
+ * whatever data is in the buffer.
+ */
+ return write_page(mtd, chip, buf, true);
+}
+
+static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return write_oob_data(mtd, chip->oob_poi, page);
+}
+
+static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ read_oob_data(mtd, chip->oob_poi, page);
+
+ return 0;
+}
+
+static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ unsigned int max_bitflips = 0;
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ dma_addr_t addr = (unsigned long)denali->buf.buf;
+ size_t size = denali->mtd.writesize + denali->mtd.oobsize;
+
+ uint32_t irq_status;
+ uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
+ INTR_STATUS__ECC_ERR;
+ bool check_erased_page = false;
+
+ if (page != denali->page) {
+ dev_err(denali->dev,
+ "IN %s: page %d is not equal to denali->page %d",
+ __func__, page, denali->page);
+ BUG();
+ }
+
+ setup_ecc_for_xfer(denali, true, false);
+
+ denali_enable_dma(denali, true);
+ dma_sync_single_for_device(addr, size, DMA_FROM_DEVICE);
+
+ clear_interrupts(denali);
+ denali_setup_dma(denali, DENALI_READ);
+
+ /* wait for operation to complete */
+ irq_status = wait_for_irq(denali, irq_mask);
+
+ dma_sync_single_for_cpu(addr, size, DMA_FROM_DEVICE);
+
+ memcpy(buf, denali->buf.buf, mtd->writesize);
+
+ check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
+ denali_enable_dma(denali, false);
+
+ if (check_erased_page) {
+ if (denali->have_hw_ecc_fixup) {
+ /* When we have hw ecc fixup, don't check oob.
+ * That code below looks jacked up anyway. I mean,
+ * look at it, wtf? */
+ if (!is_erased(buf, denali->mtd.writesize))
+ denali->mtd.ecc_stats.failed++;
+ } else {
+ read_oob_data(&denali->mtd, chip->oob_poi,
+ denali->page);
+
+ /* check ECC failures that may have occurred on
+ * erased pages */
+ if (check_erased_page) {
+ if (!is_erased(buf, denali->mtd.writesize))
+ denali->mtd.ecc_stats.failed++;
+ if (!is_erased(buf, denali->mtd.oobsize))
+ denali->mtd.ecc_stats.failed++;
+ }
+ }
+ }
+ return max_bitflips;
+}
+
+static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ dma_addr_t addr = (unsigned long)denali->buf.buf;
+ size_t size = denali->mtd.writesize + denali->mtd.oobsize;
+ uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+ if (page != denali->page) {
+ dev_err(denali->dev,
+ "IN %s: page %d is not equal to denali->page %d",
+ __func__, page, denali->page);
+ BUG();
+ }
+
+ setup_ecc_for_xfer(denali, false, true);
+ denali_enable_dma(denali, true);
+
+ dma_sync_single_for_device(addr, size, DMA_FROM_DEVICE);
+
+ clear_interrupts(denali);
+ denali_setup_dma(denali, DENALI_READ);
+
+ /* wait for operation to complete */
+ wait_for_irq(denali, irq_mask);
+
+ dma_sync_single_for_cpu(addr, size, DMA_FROM_DEVICE);
+
+ denali_enable_dma(denali, false);
+
+ memcpy(buf, denali->buf.buf, mtd->writesize);
+ memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
+
+ return 0;
+}
+
+static uint8_t denali_read_byte(struct mtd_info *mtd)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint8_t result = 0xff;
+
+ if (denali->buf.head < denali->buf.tail)
+ result = denali->buf.buf[denali->buf.head++];
+
+ return result;
+}
+
+static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i;
+ for (i = 0; i < len; i++)
+ buf[i] = denali_read_byte(mtd);
+}
+
+static void denali_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+ denali->flash_bank = chip;
+}
+
+static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int status = denali->status;
+
+ denali->status = 0;
+
+ return status;
+}
+
+static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
+ int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t addr, id;
+ uint32_t pages_per_block;
+ uint32_t block;
+ int i;
+
+ switch (cmd) {
+ case NAND_CMD_PAGEPROG:
+ break;
+ case NAND_CMD_STATUS:
+ read_status(denali);
+ break;
+ case NAND_CMD_READID:
+ reset_buf(denali);
+ /*
+ * sometimes ManufactureId read from register is not right
+ * e.g. some of Micron MT29F32G08QAA MLC NAND chips
+ * So here we send READID cmd to NAND insteand
+ */
+ addr = MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, addr | 0, 0x90);
+ index_addr(denali, addr | 1, 0);
+ for (i = 0; i < 8; i++) {
+ index_addr_read_data(denali, addr | 2, &id);
+ write_byte_to_buf(denali, id);
+ }
+ break;
+ case NAND_CMD_PARAM:
+ reset_buf(denali);
+
+ /* turn on R/B interrupt */
+ denali_set_intr_modes(denali, false);
+ denali_irq_mask = DENALI_IRQ_ALL | INTR_STATUS__INT_ACT;
+ clear_interrupts(denali);
+ denali_irq_enable(denali, denali_irq_mask);
+ denali_set_intr_modes(denali, true);
+
+ addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+ index_addr(denali, (uint32_t)addr | 0, cmd);
+ index_addr(denali, (uint32_t)addr | 1, col & 0xFF);
+ /* Wait tR time... */
+ udelay(25);
+ /* And then wait for R/B interrupt */
+ wait_for_irq(denali, INTR_STATUS__INT_ACT);
+
+ /* turn off R/B interrupt now */
+ denali_irq_mask = DENALI_IRQ_ALL;
+ denali_set_intr_modes(denali, false);
+ denali_irq_enable(denali, denali_irq_mask);
+ denali_set_intr_modes(denali, true);
+
+ for (i = 0; i < 256; i++) {
+ index_addr_read_data(denali,
+ (uint32_t)addr | 2,
+ &id);
+ write_byte_to_buf(denali, id);
+ }
+ break;
+ case NAND_CMD_READ0:
+ case NAND_CMD_SEQIN:
+ denali->page = page;
+ break;
+ case NAND_CMD_RESET:
+ reset_bank(denali);
+ break;
+ case NAND_CMD_READOOB:
+ /* TODO: Read OOB data */
+ break;
+ case NAND_CMD_UNLOCK1:
+ pages_per_block = mtd->erasesize / mtd->writesize;
+ block = page / pages_per_block;
+ addr = (uint32_t)MODE_10 | (block * pages_per_block);
+ index_addr(denali, addr, 0x10);
+ break;
+ case NAND_CMD_UNLOCK2:
+ pages_per_block = mtd->erasesize / mtd->writesize;
+ block = (page+pages_per_block-1) / pages_per_block;
+ addr = (uint32_t)MODE_10 | (block * pages_per_block);
+ index_addr(denali, addr, 0x11);
+ break;
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ addr = MODE_10 | BANK(denali->flash_bank) | page;
+ index_addr(denali, addr, 0x1);
+ break;
+ default:
+ pr_err(": unsupported command received 0x%x\n", cmd);
+ break;
+ }
+}
+/* end NAND core entry points */
+
+/* Initialization code to bring the device up to a known good state */
+static void denali_hw_init(struct denali_nand_info *denali)
+{
+ /*
+ * tell driver how many bit controller will skip before
+ * writing ECC code in OOB, this register may be already
+ * set by firmware. So we read this value out.
+ * if this value is 0, just let it be.
+ */
+ denali->bbtskipbytes = ioread32(denali->flash_reg +
+ SPARE_AREA_SKIP_BYTES);
+ detect_max_banks(denali);
+ denali_nand_reset(denali);
+ iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
+ iowrite32(CHIP_EN_DONT_CARE__FLAG,
+ denali->flash_reg + CHIP_ENABLE_DONT_CARE);
+
+ iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
+
+ /* Should set value for these registers when init */
+ iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
+ iowrite32(1, denali->flash_reg + ECC_ENABLE);
+ denali_nand_timing_set(denali);
+ denali_irq_init(denali);
+}
+
+/*
+ * Althogh controller spec said SLC ECC is forceb to be 4bit,
+ * but denali controller in MRST only support 15bit and 8bit ECC
+ * correction
+ */
+#define ECC_8BITS 14
+static struct nand_ecclayout nand_8bit_oob = {
+ .eccbytes = 14,
+};
+
+#define ECC_15BITS 26
+static struct nand_ecclayout nand_15bit_oob = {
+ .eccbytes = 26,
+};
+
+/* initialize driver data structures */
+static void denali_drv_init(struct denali_nand_info *denali)
+{
+ denali->idx = 0;
+
+ /* indicate that MTD has not selected a valid bank yet */
+ denali->flash_bank = CHIP_SELECT_INVALID;
+
+ /* initialize our irq_status variable to indicate no interrupts */
+ denali->irq_status = 0;
+}
+
+int denali_init(struct denali_nand_info *denali)
+{
+ int ret = 0;
+ uint32_t val;
+
+ if (denali->platform == INTEL_CE4100) {
+ /*
+ * Due to a silicon limitation, we can only support
+ * ONFI timing mode 1 and below.
+ */
+ if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
+ pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
+ return -EINVAL;
+ }
+ }
+
+ /* allocate a temporary buffer for nand_scan_ident() */
+ denali->buf.buf = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL);
+ if (!denali->buf.buf)
+ return -ENOMEM;
+
+ denali->mtd.parent = denali->dev;
+ denali_hw_init(denali);
+ denali_drv_init(denali);
+
+ denali_set_intr_modes(denali, true);
+ denali->mtd.name = "denali-nand";
+ denali->mtd.priv = &denali->nand;
+
+ /* register the driver with the NAND core subsystem */
+ denali->nand.read_buf = denali_read_buf;
+ denali->nand.select_chip = denali_select_chip;
+ denali->nand.cmdfunc = denali_cmdfunc;
+ denali->nand.read_byte = denali_read_byte;
+ denali->nand.waitfunc = denali_waitfunc;
+
+ /*
+ * scan for NAND devices attached to the controller
+ * this is the first stage in a two step process to register
+ * with the nand subsystem
+ */
+ if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
+ ret = -ENXIO;
+ goto failed_req_irq;
+ }
+
+ /* allocate the right size buffer now */
+ kfree(denali->buf.buf);
+ denali->buf.buf = kzalloc(denali->mtd.writesize + denali->mtd.oobsize,
+ GFP_KERNEL);
+ if (!denali->buf.buf) {
+ ret = -ENOMEM;
+ goto failed_req_irq;
+ }
+
+ /*
+ * support for multi nand
+ * MTD known nothing about multi nand, so we should tell it
+ * the real pagesize and anything necessery
+ */
+ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
+ denali->nand.chipsize <<= (denali->devnum - 1);
+ denali->nand.page_shift += (denali->devnum - 1);
+ denali->nand.pagemask = (denali->nand.chipsize >>
+ denali->nand.page_shift) - 1;
+ denali->nand.bbt_erase_shift += (denali->devnum - 1);
+ denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
+ denali->nand.chip_shift += (denali->devnum - 1);
+ denali->mtd.writesize <<= (denali->devnum - 1);
+ denali->mtd.oobsize <<= (denali->devnum - 1);
+ denali->mtd.erasesize <<= (denali->devnum - 1);
+ denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
+ denali->bbtskipbytes *= denali->devnum;
+
+ /*
+ * second stage of the NAND scan
+ * this stage requires information regarding ECC and
+ * bad block management.
+ */
+
+ /* Bad block table description is set by nand framework,
+ see nand_bbt.c */
+
+ denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
+ denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
+ if (denali->have_hw_ecc_fixup) {
+ /* We have OOB support, so allow scan of BBT
+ and leave the OOB alone */
+ denali->nand.bbt_options |= NAND_BBT_NO_OOB;
+ } else {
+ /* skip the scan for now until we have OOB read and write support */
+ denali->nand.options |= NAND_SKIP_BBTSCAN;
+ }
+
+ /* no subpage writes on denali */
+ denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
+
+ /*
+ * Denali Controller only support 15bit and 8bit ECC in MRST,
+ * so just let controller do 15bit ECC for MLC and 8bit ECC for
+ * SLC if possible.
+ * */
+ if (!nand_is_slc(&denali->nand) &&
+ (denali->mtd.oobsize > (denali->bbtskipbytes +
+ ECC_15BITS * (denali->mtd.writesize /
+ ECC_SECTOR_SIZE)))) {
+ /* if MLC OOB size is large enough, use 15bit ECC*/
+ denali->nand.ecc.strength = 15;
+ denali->nand.ecc.layout = &nand_15bit_oob;
+ denali->nand.ecc.bytes = ECC_15BITS;
+ iowrite32(15, denali->flash_reg + ECC_CORRECTION);
+ } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
+ ECC_8BITS * (denali->mtd.writesize /
+ ECC_SECTOR_SIZE))) {
+ pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
+ goto failed_req_irq;
+ } else {
+ denali->nand.ecc.strength = 8;
+ denali->nand.ecc.layout = &nand_8bit_oob;
+ denali->nand.ecc.bytes = ECC_8BITS;
+ iowrite32(8, denali->flash_reg + ECC_CORRECTION);
+ }
+
+ denali->nand.ecc.bytes *= denali->devnum;
+ denali->nand.ecc.strength *= denali->devnum;
+ denali->nand.ecc.layout->eccbytes *=
+ denali->mtd.writesize / ECC_SECTOR_SIZE;
+ denali->nand.ecc.layout->oobfree[0].offset =
+ denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
+ denali->nand.ecc.layout->oobfree[0].length =
+ denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
+ denali->bbtskipbytes;
+
+ /*
+ * Let driver know the total blocks number and how many blocks
+ * contained by each nand chip. blksperchip will help driver to
+ * know how many blocks is taken by FW.
+ */
+ denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift;
+ denali->blksperchip = denali->totalblks / denali->nand.numchips;
+
+ /* override the default read operations */
+ denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
+ denali->nand.ecc.read_page = denali_read_page;
+ denali->nand.ecc.read_page_raw = denali_read_page_raw;
+ denali->nand.ecc.write_page = denali_write_page;
+ denali->nand.ecc.write_page_raw = denali_write_page_raw;
+ denali->nand.ecc.read_oob = denali_read_oob;
+ denali->nand.ecc.write_oob = denali_write_oob;
+
+ /* Occasionally the controller is in SPARE or MAIN+SPARE
+ mode upon startup, and we want it to be MAIN only */
+ val = ioread32(denali->flash_reg + TRANSFER_MODE);
+ if (val != 0) {
+ int i;
+ dev_dbg(denali->dev,
+ "setting TRANSFER_MODE (%08x) back to MAIN only\n", val);
+ /* put all banks in MAIN mode, no SPARE */
+ iowrite32(0, denali->flash_reg + TRANSFER_SPARE_REG);
+ for (i = 0; i < 4; i++)
+ index_addr(denali, MODE_10 | BANK(i) | 1,
+ MAIN_ACCESS);
+ }
+
+ if (nand_scan_tail(&denali->mtd)) {
+ ret = -ENXIO;
+ goto failed_req_irq;
+ }
+
+ return add_mtd_nand_device(&denali->mtd, "nand");
+
+failed_req_irq:
+ denali_irq_cleanup(denali->irq, denali);
+
+ return ret;
+}
+EXPORT_SYMBOL(denali_init);
+
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/nand_denali_dt.c b/drivers/mtd/nand/nand_denali_dt.c
new file mode 100644
index 0000000..09eb110
--- /dev/null
+++ b/drivers/mtd/nand/nand_denali_dt.c
@@ -0,0 +1,101 @@
+/*
+ * NAND Flash Controller Device Driver for DT
+ *
+ * Copyright © 2011, Picochip.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <mach/generic.h>
+#include <io.h>
+#include <of_mtd.h>
+#include <errno.h>
+
+#include <linux/clk.h>
+
+
+#include "denali.h"
+
+struct denali_dt {
+ struct denali_nand_info denali;
+ struct clk *clk;
+};
+
+
+static int denali_dt_probe(struct device_d *ofdev)
+{
+ struct denali_dt *dt;
+ struct denali_nand_info *denali;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_OFDEVICE))
+ return 1;
+
+ dt = kzalloc(sizeof(*dt), GFP_KERNEL);
+ if (!dt)
+ return -ENOMEM;
+ denali = &dt->denali;
+
+ denali->platform = DT;
+ denali->dev = ofdev;
+
+ denali->flash_mem = dev_request_mem_region(ofdev, 0);
+ if (IS_ERR(denali->flash_mem))
+ return PTR_ERR(denali->flash_mem);
+ denali->flash_reg = dev_request_mem_region(ofdev, 1);
+ if (IS_ERR(denali->flash_reg))
+ return PTR_ERR(denali->flash_reg);
+
+ dt->clk = clk_get(ofdev, NULL);
+ if (IS_ERR(dt->clk)) {
+ dev_err(ofdev, "no clk available\n");
+ return PTR_ERR(dt->clk);
+ }
+ clk_enable(dt->clk);
+
+ denali->have_hw_ecc_fixup = of_property_read_bool(ofdev->device_node,
+ "have-hw-ecc-fixup");
+
+ ret = denali_init(denali);
+ if (ret)
+ goto out_disable_clk;
+
+ return 0;
+
+out_disable_clk:
+ clk_disable(dt->clk);
+
+ return ret;
+}
+
+static __maybe_unused struct of_device_id denali_nand_compatible[] = {
+ {
+ .compatible = "denali,denali-nand-dt"
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d denali_dt_driver = {
+ .name = "denali-nand-dt",
+ .probe = denali_dt_probe,
+ .of_compatible = DRV_OF_COMPAT(denali_nand_compatible)
+};
+device_platform_driver(denali_dt_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jamie Iles");
+MODULE_DESCRIPTION("DT driver for Denali NAND controller");
--
2.5.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] mtd denali: pass col argument to READID operation
2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
2015-09-21 14:04 ` [PATCH 1/4] mtd nand: added 'bits_per_cell' property Enrico Jorns
2015-09-21 14:04 ` [PATCH 2/4] mtd nand_denali: Add denali nand driver Enrico Jorns
@ 2015-09-21 14:04 ` Enrico Jorns
2015-09-21 14:04 ` [PATCH 4/4] socfpga dts: set have-hw-ecc-fixup for nand Enrico Jorns
2015-09-23 8:36 ` [PATCH 0/4] New denali nand driver (ported from kernel) Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Enrico Jorns @ 2015-09-21 14:04 UTC (permalink / raw)
To: barebox; +Cc: Enrico Jorns
A read id operation followed by 0x00 reads the device ID while
a read id operation followed by 0x20 reads the possible ONFI identifier.
As the READID function did not propagate the second id parameter but had
a hard-coded call for 0x90 0x00, reading the ONFI identifier was not
possible and thus chips werde not detected (tested with
MT29F8G08ABABAWP)
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
---
drivers/mtd/nand/nand_denali.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_denali.c b/drivers/mtd/nand/nand_denali.c
index f2d9cb7..0ff4734 100644
--- a/drivers/mtd/nand/nand_denali.c
+++ b/drivers/mtd/nand/nand_denali.c
@@ -1251,7 +1251,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
*/
addr = MODE_11 | BANK(denali->flash_bank);
index_addr(denali, addr | 0, 0x90);
- index_addr(denali, addr | 1, 0);
+ index_addr(denali, addr | 1, col);
for (i = 0; i < 8; i++) {
index_addr_read_data(denali, addr | 2, &id);
write_byte_to_buf(denali, id);
--
2.5.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] socfpga dts: set have-hw-ecc-fixup for nand
2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
` (2 preceding siblings ...)
2015-09-21 14:04 ` [PATCH 3/4] mtd denali: pass col argument to READID operation Enrico Jorns
@ 2015-09-21 14:04 ` Enrico Jorns
2015-09-23 8:36 ` [PATCH 0/4] New denali nand driver (ported from kernel) Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Enrico Jorns @ 2015-09-21 14:04 UTC (permalink / raw)
To: barebox; +Cc: Enrico Jorns
This enables the denali driver ecc fixup as it is enabled in the kernel
dts, too, and the tested MT29F8G08ABABAWP does not work properly
without it when having ecc fixup active in kernel.
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
---
arch/arm/dts/socfpga.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 14c0654..e673541 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -540,6 +540,7 @@
interrupts = <0x0 0x90 0x4>;
dma-mask = <0xffffffff>;
clocks = <&nand_clk>;
+ have-hw-ecc-fixup;
status = "disabled";
};
--
2.5.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] New denali nand driver (ported from kernel)
2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
` (3 preceding siblings ...)
2015-09-21 14:04 ` [PATCH 4/4] socfpga dts: set have-hw-ecc-fixup for nand Enrico Jorns
@ 2015-09-23 8:36 ` Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2015-09-23 8:36 UTC (permalink / raw)
To: Enrico Jorns; +Cc: barebox
On Mon, Sep 21, 2015 at 04:04:40PM +0200, Enrico Jorns wrote:
> This series adds the denali NAND driver that is used, for example,
> on socfpga platforms.
>
> The driver is adapted from the mainline kernel driver with some bugfix patches
> from Altera.
>
> Enrico Jorns (4):
> mtd nand: added 'bits_per_cell' property
> mtd nand_denali: Add denali nand driver
> mtd denali: pass col argument to READID operation
> socfpga dts: set have-hw-ecc-fixup for nand
Applied all but the last one which does not apply. We currently do not
have the nand node you add a property to.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-09-23 8:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2015-09-21 14:04 [PATCH 0/4] New denali nand driver (ported from kernel) Enrico Jorns
2015-09-21 14:04 ` [PATCH 1/4] mtd nand: added 'bits_per_cell' property Enrico Jorns
2015-09-21 14:04 ` [PATCH 2/4] mtd nand_denali: Add denali nand driver Enrico Jorns
2015-09-21 14:04 ` [PATCH 3/4] mtd denali: pass col argument to READID operation Enrico Jorns
2015-09-21 14:04 ` [PATCH 4/4] socfpga dts: set have-hw-ecc-fixup for nand Enrico Jorns
2015-09-23 8:36 ` [PATCH 0/4] New denali nand driver (ported from kernel) Sascha Hauer
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