[PATCH 4/4] ARM: imx6: set shared attribute override bit in PL310

[Lucas Stach <l.stach@pengutronix.de>]

In order to make the system compliant to the ARMv7 ARM RevC clarifications
regarding conflicting memory aliases the shared override bit needs to be
set. This needs to be done in the bootloader, as the kernel will not apply
any modifications to the AUX_CTRL register by default, as it is a secure only
register.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 509ac8460216..c49de49209f3 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -222,6 +222,17 @@ static int imx6_mmu_init(void)
 
 	writel(val, l2x0_base + L2X0_PREFETCH_CTRL);
 
+	/*
+	 * Set shared attribute override bit in AUX_CTRL register, this is done
+	 * here as it must be done regardless of the usage of the L2 cache in
+	 * barebox itself. The kernel will not touch this bit, but it must be
+	 * set to make the system compliant to the ARMv7 ARM RevC clarifications
+	 * regarding conflicting memory aliases.
+	 */
+	val = readl(l2x0_base + L2X0_AUX_CTRL);
+	val |= (1 << 22);
+	writel(val, l2x0_base + L2X0_AUX_CTRL);
+
 	l2x0_init(l2x0_base, 0x0, ~0UL);
 
 	return 0;
-- 
2.6.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox